3 pinctrl: pinctrl@10000 {
4 compatible = "marvell,88f6281-pinctrl";
8 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
9 "mpp4", "mpp5", "mpp18",
11 marvell,function = "nand";
13 pmx_sata0: pmx-sata0 {
14 marvell,pins = "mpp5", "mpp21", "mpp23";
15 marvell,function = "sata0";
17 pmx_sata1: pmx-sata1 {
18 marvell,pins = "mpp4", "mpp20", "mpp22";
19 marvell,function = "sata1";
22 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
23 marvell,function = "spi";
25 pmx_twsi0: pmx-twsi0 {
26 marvell,pins = "mpp8", "mpp9";
27 marvell,function = "twsi0";
29 pmx_uart0: pmx-uart0 {
30 marvell,pins = "mpp10", "mpp11";
31 marvell,function = "uart0";
33 pmx_uart1: pmx-uart1 {
34 marvell,pins = "mpp13", "mpp14";
35 marvell,function = "uart1";
38 marvell,pins = "mpp12", "mpp13", "mpp14",
39 "mpp15", "mpp16", "mpp17";
40 marvell,function = "sdio";
45 compatible = "marvell,kirkwood-pcie";
52 bus-range = <0x00 0xff>;
54 ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
55 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
56 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
60 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
61 reg = <0x0800 0 0 0 0>;
64 #interrupt-cells = <1>;
66 interrupt-map-mask = <0 0 0 0>;
67 interrupt-map = <0 0 0 0 &intc 9>;
68 marvell,pcie-port = <0>;
69 marvell,pcie-lane = <0>;
70 clocks = <&gate_clk 2>;
76 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
79 clocks = <&gate_clk 7>;
83 compatible = "marvell,orion-sata";
84 reg = <0x80000 0x5000>;
86 clocks = <&gate_clk 14>, <&gate_clk 15>;
87 clock-names = "0", "1";
92 compatible = "marvell,orion-sdio";
93 reg = <0x90000 0x200>;
95 clocks = <&gate_clk 4>;