4 pinctrl: pinctrl@10000 {
5 compatible = "marvell,88f6282-pinctrl";
9 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
10 "mpp4", "mpp5", "mpp18", "mpp19";
11 marvell,function = "nand";
14 pmx_sata0: pmx-sata0 {
15 marvell,pins = "mpp5", "mpp21", "mpp23";
16 marvell,function = "sata0";
18 pmx_sata1: pmx-sata1 {
19 marvell,pins = "mpp4", "mpp20", "mpp22";
20 marvell,function = "sata1";
23 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
24 marvell,function = "spi";
26 pmx_twsi0: pmx-twsi0 {
27 marvell,pins = "mpp8", "mpp9";
28 marvell,function = "twsi0";
31 pmx_twsi1: pmx-twsi1 {
32 marvell,pins = "mpp36", "mpp37";
33 marvell,function = "twsi1";
36 pmx_uart0: pmx-uart0 {
37 marvell,pins = "mpp10", "mpp11";
38 marvell,function = "uart0";
41 pmx_uart1: pmx-uart1 {
42 marvell,pins = "mpp13", "mpp14";
43 marvell,function = "uart1";
46 marvell,pins = "mpp12", "mpp13", "mpp14",
47 "mpp15", "mpp16", "mpp17";
48 marvell,function = "sdio";
53 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
56 clocks = <&gate_clk 7>;
60 compatible = "marvell,orion-sata";
61 reg = <0x80000 0x5000>;
63 clocks = <&gate_clk 14>, <&gate_clk 15>;
64 clock-names = "0", "1";
69 compatible = "marvell,orion-sdio";
70 reg = <0x90000 0x200>;
72 clocks = <&gate_clk 4>;
81 compatible = "marvell,kirkwood-thermal";
87 compatible = "marvell,mv64xxx-i2c";
92 clock-frequency = <100000>;
93 clocks = <&gate_clk 7>;
98 compatible = "marvell,kirkwood-pcie";
102 #address-cells = <3>;
105 bus-range = <0x00 0xff>;
107 ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
108 0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */
109 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
110 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
114 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
115 reg = <0x0800 0 0 0 0>;
116 #address-cells = <3>;
118 #interrupt-cells = <1>;
120 interrupt-map-mask = <0 0 0 0>;
121 interrupt-map = <0 0 0 0 &intc 9>;
122 marvell,pcie-port = <0>;
123 marvell,pcie-lane = <0>;
124 clocks = <&gate_clk 2>;
130 assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
131 reg = <0x1000 0 0 0 0>;
132 #address-cells = <3>;
134 #interrupt-cells = <1>;
136 interrupt-map-mask = <0 0 0 0>;
137 interrupt-map = <0 0 0 0 &intc 10>;
138 marvell,pcie-port = <1>;
139 marvell,pcie-lane = <0>;
140 clocks = <&gate_clk 18>;