arch/arm/boot/dts/kirkwood.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
   4
   5 / {
   6         compatible = "marvell,kirkwood";
   7         interrupt-parent = <&intc>;
   8
   9         cpus {
  10                 #address-cells = <1>;
  11                 #size-cells = <0>;
  12
  13                 cpu@0 {
  14                         device_type = "cpu";
  15                         compatible = "marvell,feroceon";
  16                         clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
  17                         clock-names = "cpu_clk", "ddrclk", "powersave";
  18                 };
  19         };
  20
  21         aliases {
  22                gpio0 = &gpio0;
  23                gpio1 = &gpio1;
  24         };
  25         intc: interrupt-controller {
  26                 compatible = "marvell,orion-intc", "marvell,intc";
  27                 interrupt-controller;
  28                 #interrupt-cells = <1>;
  29                 reg = <0xf1020204 0x04>,
  30                       <0xf1020214 0x04>;
  31         };
  32
  33         mbus {
  34                 compatible = "marvell,kirkwood-mbus", "simple-bus";
  35                 controller = <&mbusc>;
  36         };
  37
  38         ocp@f1000000 {
  39                 compatible = "simple-bus";
  40                 ranges = <0x00000000 0xf1000000 0x0100000
  41                           0xe0000000 0xe0000000 0x8100000 /* PCIE */
  42                           0xf4000000 0xf4000000 0x0000400
  43                           0xf5000000 0xf5000000 0x0000400>;
  44                 #address-cells = <1>;
  45                 #size-cells = <1>;
  46
  47                 mbusc: mbus-controller@20000 {
  48                         compatible = "marvell,mbus-controller";
  49                         reg = <0x20000 0x80>, <0x1500 0x20>;
  50                 };
  51
  52                 core_clk: core-clocks@10030 {
  53                         compatible = "marvell,kirkwood-core-clock";
  54                         reg = <0x10030 0x4>;
  55                         #clock-cells = <1>;
  56                 };
  57
  58                 gpio0: gpio@10100 {
  59                         compatible = "marvell,orion-gpio";
  60                         #gpio-cells = <2>;
  61                         gpio-controller;
  62                         reg = <0x10100 0x40>;
  63                         ngpios = <32>;
  64                         interrupt-controller;
  65                         #interrupt-cells = <2>;
  66                         interrupts = <35>, <36>, <37>, <38>;
  67                         clocks = <&gate_clk 7>;
  68                 };
  69
  70                 gpio1: gpio@10140 {
  71                         compatible = "marvell,orion-gpio";
  72                         #gpio-cells = <2>;
  73                         gpio-controller;
  74                         reg = <0x10140 0x40>;
  75                         ngpios = <18>;
  76                         interrupt-controller;
  77                         #interrupt-cells = <2>;
  78                         interrupts = <39>, <40>, <41>;
  79                         clocks = <&gate_clk 7>;
  80                 };
  81
  82                 serial@12000 {
  83                         compatible = "ns16550a";
  84                         reg = <0x12000 0x100>;
  85                         reg-shift = <2>;
  86                         interrupts = <33>;
  87                         clocks = <&gate_clk 7>;
  88                         status = "disabled";
  89                 };
  90
  91                 serial@12100 {
  92                         compatible = "ns16550a";
  93                         reg = <0x12100 0x100>;
  94                         reg-shift = <2>;
  95                         interrupts = <34>;
  96                         clocks = <&gate_clk 7>;
  97                         status = "disabled";
  98                 };
  99
 100                 spi@10600 {
 101                         compatible = "marvell,orion-spi";
 102                         #address-cells = <1>;
 103                         #size-cells = <0>;
 104                         cell-index = <0>;
 105                         interrupts = <23>;
 106                         reg = <0x10600 0x28>;
 107                         clocks = <&gate_clk 7>;
 108                         status = "disabled";
 109                 };
 110
 111                 gate_clk: clock-gating-control@2011c {
 112                         compatible = "marvell,kirkwood-gating-clock";
 113                         reg = <0x2011c 0x4>;
 114                         clocks = <&core_clk 0>;
 115                         #clock-cells = <1>;
 116                 };
 117
 118                 wdt@20300 {
 119                         compatible = "marvell,orion-wdt";
 120                         reg = <0x20300 0x28>;
 121                         clocks = <&gate_clk 7>;
 122                         status = "okay";
 123                 };
 124
 125                 xor@60800 {
 126                         compatible = "marvell,orion-xor";
 127                         reg = <0x60800 0x100
 128                                0x60A00 0x100>;
 129                         status = "okay";
 130                         clocks = <&gate_clk 8>;
 131
 132                         xor00 {
 133                               interrupts = <5>;
 134                               dmacap,memcpy;
 135                               dmacap,xor;
 136                         };
 137                         xor01 {
 138                               interrupts = <6>;
 139                               dmacap,memcpy;
 140                               dmacap,xor;
 141                               dmacap,memset;
 142                         };
 143                 };
 144
 145                 xor@60900 {
 146                         compatible = "marvell,orion-xor";
 147                         reg = <0x60900 0x100
 148                                0xd0B00 0x100>;
 149                         status = "okay";
 150                         clocks = <&gate_clk 16>;
 151
 152                         xor00 {
 153                               interrupts = <7>;
 154                               dmacap,memcpy;
 155                               dmacap,xor;
 156                         };
 157                         xor01 {
 158                               interrupts = <8>;
 159                               dmacap,memcpy;
 160                               dmacap,xor;
 161                               dmacap,memset;
 162                         };
 163                 };
 164
 165                 ehci@50000 {
 166                         compatible = "marvell,orion-ehci";
 167                         reg = <0x50000 0x1000>;
 168                         interrupts = <19>;
 169                         clocks = <&gate_clk 3>;
 170                         status = "okay";
 171                 };
 172
 173                 nand@3000000 {
 174                         #address-cells = <1>;
 175                         #size-cells = <1>;
 176                         cle = <0>;
 177                         ale = <1>;
 178                         bank-width = <1>;
 179                         compatible = "marvell,orion-nand";
 180                         reg = <0xf4000000 0x400>;
 181                         chip-delay = <25>;
 182                         /* set partition map and/or chip-delay in board dts */
 183                         clocks = <&gate_clk 7>;
 184                         status = "disabled";
 185                 };
 186
 187                 i2c@11000 {
 188                         compatible = "marvell,mv64xxx-i2c";
 189                         reg = <0x11000 0x20>;
 190                         #address-cells = <1>;
 191                         #size-cells = <0>;
 192                         interrupts = <29>;
 193                         clock-frequency = <100000>;
 194                         clocks = <&gate_clk 7>;
 195                         status = "disabled";
 196                 };
 197
 198                 crypto@30000 {
 199                         compatible = "marvell,orion-crypto";
 200                         reg = <0x30000 0x10000>,
 201                               <0xf5000000 0x800>;
 202                         reg-names = "regs", "sram";
 203                         interrupts = <22>;
 204                         clocks = <&gate_clk 17>;
 205                         status = "okay";
 206                 };
 207         };
 208 };