arch/arm/boot/dts/mmp2.dtsi

   1 /*
   2  *  Copyright (C) 2012 Marvell Technology Group Ltd.
   3  *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
   4  *
   5  *  This program is free software; you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License version 2 as
   7  *  publishhed by the Free Software Foundation.
   8  */
   9
  10 /include/ "skeleton.dtsi"
  11
  12 / {
  13         aliases {
  14                 serial0 = &uart1;
  15                 serial1 = &uart2;
  16                 serial2 = &uart3;
  17                 serial3 = &uart4;
  18                 i2c0 = &twsi1;
  19                 i2c1 = &twsi2;
  20         };
  21
  22         soc {
  23                 #address-cells = <1>;
  24                 #size-cells = <1>;
  25                 compatible = "simple-bus";
  26                 interrupt-parent = <&intc>;
  27                 ranges;
  28
  29                 L2: l2-cache {
  30                         compatible = "marvell,tauros2-cache";
  31                         marvell,tauros2-cache-features = <0x3>;
  32                 };
  33
  34                 axi@d4200000 {  /* AXI */
  35                         compatible = "mrvl,axi-bus", "simple-bus";
  36                         #address-cells = <1>;
  37                         #size-cells = <1>;
  38                         reg = <0xd4200000 0x00200000>;
  39                         ranges;
  40
  41                         intc: interrupt-controller@d4282000 {
  42                                 compatible = "mrvl,mmp2-intc";
  43                                 interrupt-controller;
  44                                 #interrupt-cells = <1>;
  45                                 reg = <0xd4282000 0x1000>;
  46                                 mrvl,intc-nr-irqs = <64>;
  47                         };
  48
  49                         intcmux4: interrupt-controller@d4282150 {
  50                                 compatible = "mrvl,mmp2-mux-intc";
  51                                 interrupts = <4>;
  52                                 interrupt-controller;
  53                                 #interrupt-cells = <1>;
  54                                 reg = <0x150 0x4>, <0x168 0x4>;
  55                                 reg-names = "mux status", "mux mask";
  56                                 mrvl,intc-nr-irqs = <2>;
  57                         };
  58
  59                         intcmux5: interrupt-controller@d4282154 {
  60                                 compatible = "mrvl,mmp2-mux-intc";
  61                                 interrupts = <5>;
  62                                 interrupt-controller;
  63                                 #interrupt-cells = <1>;
  64                                 reg = <0x154 0x4>, <0x16c 0x4>;
  65                                 reg-names = "mux status", "mux mask";
  66                                 mrvl,intc-nr-irqs = <2>;
  67                                 mrvl,clr-mfp-irq = <1>;
  68                         };
  69
  70                         intcmux9: interrupt-controller@d4282180 {
  71                                 compatible = "mrvl,mmp2-mux-intc";
  72                                 interrupts = <9>;
  73                                 interrupt-controller;
  74                                 #interrupt-cells = <1>;
  75                                 reg = <0x180 0x4>, <0x17c 0x4>;
  76                                 reg-names = "mux status", "mux mask";
  77                                 mrvl,intc-nr-irqs = <3>;
  78                         };
  79
  80                         intcmux17: interrupt-controller@d4282158 {
  81                                 compatible = "mrvl,mmp2-mux-intc";
  82                                 interrupts = <17>;
  83                                 interrupt-controller;
  84                                 #interrupt-cells = <1>;
  85                                 reg = <0x158 0x4>, <0x170 0x4>;
  86                                 reg-names = "mux status", "mux mask";
  87                                 mrvl,intc-nr-irqs = <5>;
  88                         };
  89
  90                         intcmux35: interrupt-controller@d428215c {
  91                                 compatible = "mrvl,mmp2-mux-intc";
  92                                 interrupts = <35>;
  93                                 interrupt-controller;
  94                                 #interrupt-cells = <1>;
  95                                 reg = <0x15c 0x4>, <0x174 0x4>;
  96                                 reg-names = "mux status", "mux mask";
  97                                 mrvl,intc-nr-irqs = <15>;
  98                         };
  99
 100                         intcmux51: interrupt-controller@d4282160 {
 101                                 compatible = "mrvl,mmp2-mux-intc";
 102                                 interrupts = <51>;
 103                                 interrupt-controller;
 104                                 #interrupt-cells = <1>;
 105                                 reg = <0x160 0x4>, <0x178 0x4>;
 106                                 reg-names = "mux status", "mux mask";
 107                                 mrvl,intc-nr-irqs = <2>;
 108                         };
 109
 110                         intcmux55: interrupt-controller@d4282188 {
 111                                 compatible = "mrvl,mmp2-mux-intc";
 112                                 interrupts = <55>;
 113                                 interrupt-controller;
 114                                 #interrupt-cells = <1>;
 115                                 reg = <0x188 0x4>, <0x184 0x4>;
 116                                 reg-names = "mux status", "mux mask";
 117                                 mrvl,intc-nr-irqs = <2>;
 118                         };
 119                 };
 120
 121                 apb@d4000000 {  /* APB */
 122                         compatible = "mrvl,apb-bus", "simple-bus";
 123                         #address-cells = <1>;
 124                         #size-cells = <1>;
 125                         reg = <0xd4000000 0x00200000>;
 126                         ranges;
 127
 128                         timer0: timer@d4014000 {
 129                                 compatible = "mrvl,mmp-timer";
 130                                 reg = <0xd4014000 0x100>;
 131                                 interrupts = <13>;
 132                         };
 133
 134                         uart1: uart@d4030000 {
 135                                 compatible = "mrvl,mmp-uart";
 136                                 reg = <0xd4030000 0x1000>;
 137                                 interrupts = <27>;
 138                                 status = "disabled";
 139                         };
 140
 141                         uart2: uart@d4017000 {
 142                                 compatible = "mrvl,mmp-uart";
 143                                 reg = <0xd4017000 0x1000>;
 144                                 interrupts = <28>;
 145                                 status = "disabled";
 146                         };
 147
 148                         uart3: uart@d4018000 {
 149                                 compatible = "mrvl,mmp-uart";
 150                                 reg = <0xd4018000 0x1000>;
 151                                 interrupts = <24>;
 152                                 status = "disabled";
 153                         };
 154
 155                         uart4: uart@d4016000 {
 156                                 compatible = "mrvl,mmp-uart";
 157                                 reg = <0xd4016000 0x1000>;
 158                                 interrupts = <46>;
 159                                 status = "disabled";
 160                         };
 161
 162                         gpio@d4019000 {
 163                                 compatible = "marvell,mmp2-gpio";
 164                                 #address-cells = <1>;
 165                                 #size-cells = <1>;
 166                                 reg = <0xd4019000 0x1000>;
 167                                 gpio-controller;
 168                                 #gpio-cells = <2>;
 169                                 interrupts = <49>;
 170                                 interrupt-names = "gpio_mux";
 171                                 interrupt-controller;
 172                                 #interrupt-cells = <1>;
 173                                 ranges;
 174
 175                                 gcb0: gpio@d4019000 {
 176                                         reg = <0xd4019000 0x4>;
 177                                 };
 178
 179                                 gcb1: gpio@d4019004 {
 180                                         reg = <0xd4019004 0x4>;
 181                                 };
 182
 183                                 gcb2: gpio@d4019008 {
 184                                         reg = <0xd4019008 0x4>;
 185                                 };
 186
 187                                 gcb3: gpio@d4019100 {
 188                                         reg = <0xd4019100 0x4>;
 189                                 };
 190
 191                                 gcb4: gpio@d4019104 {
 192                                         reg = <0xd4019104 0x4>;
 193                                 };
 194
 195                                 gcb5: gpio@d4019108 {
 196                                         reg = <0xd4019108 0x4>;
 197                                 };
 198                         };
 199
 200                         twsi1: i2c@d4011000 {
 201                                 compatible = "mrvl,mmp-twsi";
 202                                 reg = <0xd4011000 0x1000>;
 203                                 interrupts = <7>;
 204                                 #address-cells = <1>;
 205                                 #size-cells = <0>;
 206                                 mrvl,i2c-fast-mode;
 207                                 status = "disabled";
 208                         };
 209
 210                         twsi2: i2c@d4025000 {
 211                                 compatible = "mrvl,mmp-twsi";
 212                                 reg = <0xd4025000 0x1000>;
 213                                 interrupts = <58>;
 214                                 status = "disabled";
 215                         };
 216
 217                         rtc: rtc@d4010000 {
 218                                 compatible = "mrvl,mmp-rtc";
 219                                 reg = <0xd4010000 0x1000>;
 220                                 interrupts = <1 0>;
 221                                 interrupt-names = "rtc 1Hz", "rtc alarm";
 222                                 interrupt-parent = <&intcmux5>;
 223                                 status = "disabled";
 224                         };
 225                 };
 226         };
 227 };