2 * Device Tree Source for OMAP3 SoC
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/omap.h>
15 #include "skeleton.dtsi"
18 compatible = "ti,omap3430", "ti,omap3";
19 interrupt-parent = <&intc>;
35 compatible = "arm,cortex-a8";
42 clock-latency = <300000>; /* From omap-cpufreq driver */
47 compatible = "arm,cortex-a8-pmu";
48 reg = <0x54000000 0x800000>;
50 ti,hwmods = "debugss";
54 * The soc node represents the soc top level view. It is used for IPs
55 * that are not memory mapped in the MPU view or for the MPU itself.
58 compatible = "ti,omap-infra";
60 compatible = "ti,omap3-mpu";
65 compatible = "ti,iva2.2";
69 compatible = "ti,omap3-c64";
75 * XXX: Use a flat representation of the OMAP3 interconnect.
76 * The real OMAP interconnect network is quite complex.
77 * Since it will not bring real advantage to represent that in DT for
78 * the moment, just use a fake OCP bus entry to represent the whole bus
82 compatible = "ti,omap3-l3-smx", "simple-bus";
83 reg = <0x68000000 0x10000>;
88 ti,hwmods = "l3_main";
91 compatible = "ti,omap3-aes";
93 reg = <0x480c5000 0x50>;
98 compatible = "ti,omap3-prm";
99 reg = <0x48306000 0x4000>;
103 #address-cells = <1>;
107 prm_clockdomains: clockdomains {
112 compatible = "ti,omap3-cm";
113 reg = <0x48004000 0x4000>;
116 #address-cells = <1>;
120 cm_clockdomains: clockdomains {
124 scrm: scrm@48002000 {
125 compatible = "ti,omap3-scrm";
126 reg = <0x48002000 0x2000>;
128 scrm_clocks: clocks {
129 #address-cells = <1>;
133 scrm_clockdomains: clockdomains {
137 counter32k: counter@48320000 {
138 compatible = "ti,omap-counter32k";
139 reg = <0x48320000 0x20>;
140 ti,hwmods = "counter_32k";
143 intc: interrupt-controller@48200000 {
144 compatible = "ti,omap3-intc";
145 interrupt-controller;
146 #interrupt-cells = <1>;
147 reg = <0x48200000 0x1000>;
150 sdma: dma-controller@48056000 {
151 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
152 reg = <0x48056000 0x1000>;
158 #dma-channels = <32>;
159 #dma-requests = <96>;
162 omap3_pmx_core: pinmux@48002030 {
163 compatible = "ti,omap3-padconf", "pinctrl-single";
164 reg = <0x48002030 0x0238>;
165 #address-cells = <1>;
167 #interrupt-cells = <1>;
168 interrupt-controller;
169 pinctrl-single,register-width = <16>;
170 pinctrl-single,function-mask = <0xff1f>;
173 omap3_pmx_wkup: pinmux@48002a00 {
174 compatible = "ti,omap3-padconf", "pinctrl-single";
175 reg = <0x48002a00 0x5c>;
176 #address-cells = <1>;
178 #interrupt-cells = <1>;
179 interrupt-controller;
180 pinctrl-single,register-width = <16>;
181 pinctrl-single,function-mask = <0xff1f>;
184 omap3_scm_general: tisyscon@48002270 {
185 compatible = "syscon";
186 reg = <0x48002270 0x2f0>;
189 pbias_regulator: pbias_regulator {
190 compatible = "ti,pbias-omap";
192 syscon = <&omap3_scm_general>;
193 pbias_mmc_reg: pbias_mmc_omap2430 {
194 regulator-name = "pbias_mmc_omap2430";
195 regulator-min-microvolt = <1800000>;
196 regulator-max-microvolt = <3000000>;
200 gpio1: gpio@48310000 {
201 compatible = "ti,omap3-gpio";
202 reg = <0x48310000 0x200>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
212 gpio2: gpio@49050000 {
213 compatible = "ti,omap3-gpio";
214 reg = <0x49050000 0x200>;
219 interrupt-controller;
220 #interrupt-cells = <2>;
223 gpio3: gpio@49052000 {
224 compatible = "ti,omap3-gpio";
225 reg = <0x49052000 0x200>;
230 interrupt-controller;
231 #interrupt-cells = <2>;
234 gpio4: gpio@49054000 {
235 compatible = "ti,omap3-gpio";
236 reg = <0x49054000 0x200>;
241 interrupt-controller;
242 #interrupt-cells = <2>;
245 gpio5: gpio@49056000 {
246 compatible = "ti,omap3-gpio";
247 reg = <0x49056000 0x200>;
252 interrupt-controller;
253 #interrupt-cells = <2>;
256 gpio6: gpio@49058000 {
257 compatible = "ti,omap3-gpio";
258 reg = <0x49058000 0x200>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
267 uart1: serial@4806a000 {
268 compatible = "ti,omap3-uart";
269 reg = <0x4806a000 0x2000>;
270 interrupts-extended = <&intc 72>;
271 dmas = <&sdma 49 &sdma 50>;
272 dma-names = "tx", "rx";
274 clock-frequency = <48000000>;
277 uart2: serial@4806c000 {
278 compatible = "ti,omap3-uart";
279 reg = <0x4806c000 0x400>;
280 interrupts-extended = <&intc 73>;
281 dmas = <&sdma 51 &sdma 52>;
282 dma-names = "tx", "rx";
284 clock-frequency = <48000000>;
287 uart3: serial@49020000 {
288 compatible = "ti,omap3-uart";
289 reg = <0x49020000 0x400>;
290 interrupts-extended = <&intc 74>;
291 dmas = <&sdma 53 &sdma 54>;
292 dma-names = "tx", "rx";
294 clock-frequency = <48000000>;
298 compatible = "ti,omap3-i2c";
299 reg = <0x48070000 0x80>;
301 dmas = <&sdma 27 &sdma 28>;
302 dma-names = "tx", "rx";
303 #address-cells = <1>;
309 compatible = "ti,omap3-i2c";
310 reg = <0x48072000 0x80>;
312 dmas = <&sdma 29 &sdma 30>;
313 dma-names = "tx", "rx";
314 #address-cells = <1>;
320 compatible = "ti,omap3-i2c";
321 reg = <0x48060000 0x80>;
323 dmas = <&sdma 25 &sdma 26>;
324 dma-names = "tx", "rx";
325 #address-cells = <1>;
330 mailbox: mailbox@48094000 {
331 compatible = "ti,omap3-mailbox";
332 ti,hwmods = "mailbox";
333 reg = <0x48094000 0x200>;
336 ti,mbox-num-users = <2>;
337 ti,mbox-num-fifos = <2>;
339 ti,mbox-tx = <0 0 0>;
340 ti,mbox-rx = <1 0 0>;
344 mcspi1: spi@48098000 {
345 compatible = "ti,omap2-mcspi";
346 reg = <0x48098000 0x100>;
348 #address-cells = <1>;
350 ti,hwmods = "mcspi1";
360 dma-names = "tx0", "rx0", "tx1", "rx1",
361 "tx2", "rx2", "tx3", "rx3";
364 mcspi2: spi@4809a000 {
365 compatible = "ti,omap2-mcspi";
366 reg = <0x4809a000 0x100>;
368 #address-cells = <1>;
370 ti,hwmods = "mcspi2";
376 dma-names = "tx0", "rx0", "tx1", "rx1";
379 mcspi3: spi@480b8000 {
380 compatible = "ti,omap2-mcspi";
381 reg = <0x480b8000 0x100>;
383 #address-cells = <1>;
385 ti,hwmods = "mcspi3";
391 dma-names = "tx0", "rx0", "tx1", "rx1";
394 mcspi4: spi@480ba000 {
395 compatible = "ti,omap2-mcspi";
396 reg = <0x480ba000 0x100>;
398 #address-cells = <1>;
400 ti,hwmods = "mcspi4";
402 dmas = <&sdma 70>, <&sdma 71>;
403 dma-names = "tx0", "rx0";
406 hdqw1w: 1w@480b2000 {
407 compatible = "ti,omap3-1w";
408 reg = <0x480b2000 0x1000>;
414 compatible = "ti,omap3-hsmmc";
415 reg = <0x4809c000 0x200>;
419 dmas = <&sdma 61>, <&sdma 62>;
420 dma-names = "tx", "rx";
421 pbias-supply = <&pbias_mmc_reg>;
425 compatible = "ti,omap3-hsmmc";
426 reg = <0x480b4000 0x200>;
429 dmas = <&sdma 47>, <&sdma 48>;
430 dma-names = "tx", "rx";
434 compatible = "ti,omap3-hsmmc";
435 reg = <0x480ad000 0x200>;
438 dmas = <&sdma 77>, <&sdma 78>;
439 dma-names = "tx", "rx";
442 mmu_isp: mmu@480bd400 {
443 compatible = "ti,omap2-iommu";
444 reg = <0x480bd400 0x80>;
446 ti,hwmods = "mmu_isp";
447 ti,#tlb-entries = <8>;
450 mmu_iva: mmu@5d000000 {
451 compatible = "ti,omap2-iommu";
452 reg = <0x5d000000 0x80>;
454 ti,hwmods = "mmu_iva";
459 compatible = "ti,omap3-wdt";
460 reg = <0x48314000 0x80>;
461 ti,hwmods = "wd_timer2";
464 mcbsp1: mcbsp@48074000 {
465 compatible = "ti,omap3-mcbsp";
466 reg = <0x48074000 0xff>;
468 interrupts = <16>, /* OCP compliant interrupt */
469 <59>, /* TX interrupt */
470 <60>; /* RX interrupt */
471 interrupt-names = "common", "tx", "rx";
472 ti,buffer-size = <128>;
473 ti,hwmods = "mcbsp1";
476 dma-names = "tx", "rx";
480 mcbsp2: mcbsp@49022000 {
481 compatible = "ti,omap3-mcbsp";
482 reg = <0x49022000 0xff>,
484 reg-names = "mpu", "sidetone";
485 interrupts = <17>, /* OCP compliant interrupt */
486 <62>, /* TX interrupt */
487 <63>, /* RX interrupt */
489 interrupt-names = "common", "tx", "rx", "sidetone";
490 ti,buffer-size = <1280>;
491 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
494 dma-names = "tx", "rx";
498 mcbsp3: mcbsp@49024000 {
499 compatible = "ti,omap3-mcbsp";
500 reg = <0x49024000 0xff>,
502 reg-names = "mpu", "sidetone";
503 interrupts = <22>, /* OCP compliant interrupt */
504 <89>, /* TX interrupt */
505 <90>, /* RX interrupt */
507 interrupt-names = "common", "tx", "rx", "sidetone";
508 ti,buffer-size = <128>;
509 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
512 dma-names = "tx", "rx";
516 mcbsp4: mcbsp@49026000 {
517 compatible = "ti,omap3-mcbsp";
518 reg = <0x49026000 0xff>;
520 interrupts = <23>, /* OCP compliant interrupt */
521 <54>, /* TX interrupt */
522 <55>; /* RX interrupt */
523 interrupt-names = "common", "tx", "rx";
524 ti,buffer-size = <128>;
525 ti,hwmods = "mcbsp4";
528 dma-names = "tx", "rx";
532 mcbsp5: mcbsp@48096000 {
533 compatible = "ti,omap3-mcbsp";
534 reg = <0x48096000 0xff>;
536 interrupts = <27>, /* OCP compliant interrupt */
537 <81>, /* TX interrupt */
538 <82>; /* RX interrupt */
539 interrupt-names = "common", "tx", "rx";
540 ti,buffer-size = <128>;
541 ti,hwmods = "mcbsp5";
544 dma-names = "tx", "rx";
548 sham: sham@480c3000 {
549 compatible = "ti,omap3-sham";
551 reg = <0x480c3000 0x64>;
555 smartreflex_core: smartreflex@480cb000 {
556 compatible = "ti,omap3-smartreflex-core";
557 ti,hwmods = "smartreflex_core";
558 reg = <0x480cb000 0x400>;
562 smartreflex_mpu_iva: smartreflex@480c9000 {
563 compatible = "ti,omap3-smartreflex-iva";
564 ti,hwmods = "smartreflex_mpu_iva";
565 reg = <0x480c9000 0x400>;
569 timer1: timer@48318000 {
570 compatible = "ti,omap3430-timer";
571 reg = <0x48318000 0x400>;
573 ti,hwmods = "timer1";
577 timer2: timer@49032000 {
578 compatible = "ti,omap3430-timer";
579 reg = <0x49032000 0x400>;
581 ti,hwmods = "timer2";
584 timer3: timer@49034000 {
585 compatible = "ti,omap3430-timer";
586 reg = <0x49034000 0x400>;
588 ti,hwmods = "timer3";
591 timer4: timer@49036000 {
592 compatible = "ti,omap3430-timer";
593 reg = <0x49036000 0x400>;
595 ti,hwmods = "timer4";
598 timer5: timer@49038000 {
599 compatible = "ti,omap3430-timer";
600 reg = <0x49038000 0x400>;
602 ti,hwmods = "timer5";
606 timer6: timer@4903a000 {
607 compatible = "ti,omap3430-timer";
608 reg = <0x4903a000 0x400>;
610 ti,hwmods = "timer6";
614 timer7: timer@4903c000 {
615 compatible = "ti,omap3430-timer";
616 reg = <0x4903c000 0x400>;
618 ti,hwmods = "timer7";
622 timer8: timer@4903e000 {
623 compatible = "ti,omap3430-timer";
624 reg = <0x4903e000 0x400>;
626 ti,hwmods = "timer8";
631 timer9: timer@49040000 {
632 compatible = "ti,omap3430-timer";
633 reg = <0x49040000 0x400>;
635 ti,hwmods = "timer9";
639 timer10: timer@48086000 {
640 compatible = "ti,omap3430-timer";
641 reg = <0x48086000 0x400>;
643 ti,hwmods = "timer10";
647 timer11: timer@48088000 {
648 compatible = "ti,omap3430-timer";
649 reg = <0x48088000 0x400>;
651 ti,hwmods = "timer11";
655 timer12: timer@48304000 {
656 compatible = "ti,omap3430-timer";
657 reg = <0x48304000 0x400>;
659 ti,hwmods = "timer12";
664 usbhstll: usbhstll@48062000 {
665 compatible = "ti,usbhs-tll";
666 reg = <0x48062000 0x1000>;
668 ti,hwmods = "usb_tll_hs";
671 usbhshost: usbhshost@48064000 {
672 compatible = "ti,usbhs-host";
673 reg = <0x48064000 0x400>;
674 ti,hwmods = "usb_host_hs";
675 #address-cells = <1>;
679 usbhsohci: ohci@48064400 {
680 compatible = "ti,ohci-omap3";
681 reg = <0x48064400 0x400>;
682 interrupt-parent = <&intc>;
686 usbhsehci: ehci@48064800 {
687 compatible = "ti,ehci-omap";
688 reg = <0x48064800 0x400>;
689 interrupt-parent = <&intc>;
694 gpmc: gpmc@6e000000 {
695 compatible = "ti,omap3430-gpmc";
697 reg = <0x6e000000 0x02d0>;
700 gpmc,num-waitpins = <4>;
701 #address-cells = <2>;
705 usb_otg_hs: usb_otg_hs@480ab000 {
706 compatible = "ti,omap3-musb";
707 reg = <0x480ab000 0x1000>;
708 interrupts = <92>, <93>;
709 interrupt-names = "mc", "dma";
710 ti,hwmods = "usb_otg_hs";
717 compatible = "ti,omap3-dss";
718 reg = <0x48050000 0x200>;
720 ti,hwmods = "dss_core";
721 clocks = <&dss1_alwon_fck>;
723 #address-cells = <1>;
728 compatible = "ti,omap3-dispc";
729 reg = <0x48050400 0x400>;
731 ti,hwmods = "dss_dispc";
732 clocks = <&dss1_alwon_fck>;
736 dsi: encoder@4804fc00 {
737 compatible = "ti,omap3-dsi";
738 reg = <0x4804fc00 0x200>,
741 reg-names = "proto", "phy", "pll";
744 ti,hwmods = "dss_dsi1";
745 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
746 clock-names = "fck", "sys_clk";
749 rfbi: encoder@48050800 {
750 compatible = "ti,omap3-rfbi";
751 reg = <0x48050800 0x100>;
753 ti,hwmods = "dss_rfbi";
754 clocks = <&dss1_alwon_fck>, <&dss_ick>;
755 clock-names = "fck", "ick";
758 venc: encoder@48050c00 {
759 compatible = "ti,omap3-venc";
760 reg = <0x48050c00 0x100>;
762 ti,hwmods = "dss_venc";
763 clocks = <&dss_tv_fck>;
768 ssi: ssi-controller@48058000 {
769 compatible = "ti,omap3-ssi";
774 reg = <0x48058000 0x1000>,
780 interrupt-names = "gdd_mpu";
782 #address-cells = <1>;
786 ssi_port1: ssi-port@4805a000 {
787 compatible = "ti,omap3-ssi-port";
789 reg = <0x4805a000 0x800>,
794 interrupt-parent = <&intc>;
799 ssi_port2: ssi-port@4805b000 {
800 compatible = "ti,omap3-ssi-port";
802 reg = <0x4805b000 0x800>,
807 interrupt-parent = <&intc>;
815 /include/ "omap3xxx-clocks.dtsi"