2 * Device Tree Source for OMAP3 SoC
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/omap.h>
15 #include "skeleton.dtsi"
18 compatible = "ti,omap3430", "ti,omap3";
19 interrupt-parent = <&intc>;
35 compatible = "arm,cortex-a8";
42 clock-latency = <300000>; /* From omap-cpufreq driver */
47 compatible = "arm,cortex-a8-pmu";
48 reg = <0x54000000 0x800000>;
50 ti,hwmods = "debugss";
54 * The soc node represents the soc top level view. It is used for IPs
55 * that are not memory mapped in the MPU view or for the MPU itself.
58 compatible = "ti,omap-infra";
60 compatible = "ti,omap3-mpu";
65 compatible = "ti,iva2.2";
69 compatible = "ti,omap3-c64";
75 * XXX: Use a flat representation of the OMAP3 interconnect.
76 * The real OMAP interconnect network is quite complex.
77 * Since it will not bring real advantage to represent that in DT for
78 * the moment, just use a fake OCP bus entry to represent the whole bus
82 compatible = "simple-bus";
83 reg = <0x68000000 0x10000>;
88 ti,hwmods = "l3_main";
91 compatible = "ti,omap3-aes";
93 reg = <0x480c5000 0x50>;
98 compatible = "ti,omap3-prm";
99 reg = <0x48306000 0x4000>;
102 #address-cells = <1>;
106 prm_clockdomains: clockdomains {
111 compatible = "ti,omap3-cm";
112 reg = <0x48004000 0x4000>;
115 #address-cells = <1>;
119 cm_clockdomains: clockdomains {
123 scrm: scrm@48002000 {
124 compatible = "ti,omap3-scrm";
125 reg = <0x48002000 0x2000>;
127 scrm_clocks: clocks {
128 #address-cells = <1>;
132 scrm_clockdomains: clockdomains {
136 counter32k: counter@48320000 {
137 compatible = "ti,omap-counter32k";
138 reg = <0x48320000 0x20>;
139 ti,hwmods = "counter_32k";
142 intc: interrupt-controller@48200000 {
143 compatible = "ti,omap2-intc";
144 interrupt-controller;
145 #interrupt-cells = <1>;
147 reg = <0x48200000 0x1000>;
150 sdma: dma-controller@48056000 {
151 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
152 reg = <0x48056000 0x1000>;
158 #dma-channels = <32>;
159 #dma-requests = <96>;
162 omap3_pmx_core: pinmux@48002030 {
163 compatible = "ti,omap3-padconf", "pinctrl-single";
164 reg = <0x48002030 0x0238>;
165 #address-cells = <1>;
167 #interrupt-cells = <1>;
168 interrupt-controller;
169 pinctrl-single,register-width = <16>;
170 pinctrl-single,function-mask = <0xff1f>;
173 omap3_pmx_wkup: pinmux@48002a00 {
174 compatible = "ti,omap3-padconf", "pinctrl-single";
175 reg = <0x48002a00 0x5c>;
176 #address-cells = <1>;
178 #interrupt-cells = <1>;
179 interrupt-controller;
180 pinctrl-single,register-width = <16>;
181 pinctrl-single,function-mask = <0xff1f>;
184 omap3_scm_general: tisyscon@48002270 {
185 compatible = "syscon";
186 reg = <0x48002270 0x2f0>;
189 pbias_regulator: pbias_regulator {
190 compatible = "ti,pbias-omap";
192 syscon = <&omap3_scm_general>;
193 pbias_mmc_reg: pbias_mmc_omap2430 {
194 regulator-name = "pbias_mmc_omap2430";
195 regulator-min-microvolt = <1800000>;
196 regulator-max-microvolt = <3000000>;
200 gpio1: gpio@48310000 {
201 compatible = "ti,omap3-gpio";
202 reg = <0x48310000 0x200>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
212 gpio2: gpio@49050000 {
213 compatible = "ti,omap3-gpio";
214 reg = <0x49050000 0x200>;
219 interrupt-controller;
220 #interrupt-cells = <2>;
223 gpio3: gpio@49052000 {
224 compatible = "ti,omap3-gpio";
225 reg = <0x49052000 0x200>;
230 interrupt-controller;
231 #interrupt-cells = <2>;
234 gpio4: gpio@49054000 {
235 compatible = "ti,omap3-gpio";
236 reg = <0x49054000 0x200>;
241 interrupt-controller;
242 #interrupt-cells = <2>;
245 gpio5: gpio@49056000 {
246 compatible = "ti,omap3-gpio";
247 reg = <0x49056000 0x200>;
252 interrupt-controller;
253 #interrupt-cells = <2>;
256 gpio6: gpio@49058000 {
257 compatible = "ti,omap3-gpio";
258 reg = <0x49058000 0x200>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
267 uart1: serial@4806a000 {
268 compatible = "ti,omap3-uart";
269 reg = <0x4806a000 0x2000>;
270 interrupts-extended = <&intc 72>;
271 dmas = <&sdma 49 &sdma 50>;
272 dma-names = "tx", "rx";
274 clock-frequency = <48000000>;
277 uart2: serial@4806c000 {
278 compatible = "ti,omap3-uart";
279 reg = <0x4806c000 0x400>;
280 interrupts-extended = <&intc 73>;
281 dmas = <&sdma 51 &sdma 52>;
282 dma-names = "tx", "rx";
284 clock-frequency = <48000000>;
287 uart3: serial@49020000 {
288 compatible = "ti,omap3-uart";
289 reg = <0x49020000 0x400>;
290 interrupts-extended = <&intc 74>;
291 dmas = <&sdma 53 &sdma 54>;
292 dma-names = "tx", "rx";
294 clock-frequency = <48000000>;
298 compatible = "ti,omap3-i2c";
299 reg = <0x48070000 0x80>;
301 dmas = <&sdma 27 &sdma 28>;
302 dma-names = "tx", "rx";
303 #address-cells = <1>;
309 compatible = "ti,omap3-i2c";
310 reg = <0x48072000 0x80>;
312 dmas = <&sdma 29 &sdma 30>;
313 dma-names = "tx", "rx";
314 #address-cells = <1>;
320 compatible = "ti,omap3-i2c";
321 reg = <0x48060000 0x80>;
323 dmas = <&sdma 25 &sdma 26>;
324 dma-names = "tx", "rx";
325 #address-cells = <1>;
330 mailbox: mailbox@48094000 {
331 compatible = "ti,omap3-mailbox";
332 ti,hwmods = "mailbox";
333 reg = <0x48094000 0x200>;
335 ti,mbox-num-users = <2>;
336 ti,mbox-num-fifos = <2>;
339 mcspi1: spi@48098000 {
340 compatible = "ti,omap2-mcspi";
341 reg = <0x48098000 0x100>;
343 #address-cells = <1>;
345 ti,hwmods = "mcspi1";
355 dma-names = "tx0", "rx0", "tx1", "rx1",
356 "tx2", "rx2", "tx3", "rx3";
359 mcspi2: spi@4809a000 {
360 compatible = "ti,omap2-mcspi";
361 reg = <0x4809a000 0x100>;
363 #address-cells = <1>;
365 ti,hwmods = "mcspi2";
371 dma-names = "tx0", "rx0", "tx1", "rx1";
374 mcspi3: spi@480b8000 {
375 compatible = "ti,omap2-mcspi";
376 reg = <0x480b8000 0x100>;
378 #address-cells = <1>;
380 ti,hwmods = "mcspi3";
386 dma-names = "tx0", "rx0", "tx1", "rx1";
389 mcspi4: spi@480ba000 {
390 compatible = "ti,omap2-mcspi";
391 reg = <0x480ba000 0x100>;
393 #address-cells = <1>;
395 ti,hwmods = "mcspi4";
397 dmas = <&sdma 70>, <&sdma 71>;
398 dma-names = "tx0", "rx0";
401 hdqw1w: 1w@480b2000 {
402 compatible = "ti,omap3-1w";
403 reg = <0x480b2000 0x1000>;
409 compatible = "ti,omap3-hsmmc";
410 reg = <0x4809c000 0x200>;
414 dmas = <&sdma 61>, <&sdma 62>;
415 dma-names = "tx", "rx";
416 pbias-supply = <&pbias_mmc_reg>;
420 compatible = "ti,omap3-hsmmc";
421 reg = <0x480b4000 0x200>;
424 dmas = <&sdma 47>, <&sdma 48>;
425 dma-names = "tx", "rx";
429 compatible = "ti,omap3-hsmmc";
430 reg = <0x480ad000 0x200>;
433 dmas = <&sdma 77>, <&sdma 78>;
434 dma-names = "tx", "rx";
437 mmu_isp: mmu@480bd400 {
438 compatible = "ti,omap2-iommu";
439 reg = <0x480bd400 0x80>;
441 ti,hwmods = "mmu_isp";
442 ti,#tlb-entries = <8>;
445 mmu_iva: mmu@5d000000 {
446 compatible = "ti,omap2-iommu";
447 reg = <0x5d000000 0x80>;
449 ti,hwmods = "mmu_iva";
454 compatible = "ti,omap3-wdt";
455 reg = <0x48314000 0x80>;
456 ti,hwmods = "wd_timer2";
459 mcbsp1: mcbsp@48074000 {
460 compatible = "ti,omap3-mcbsp";
461 reg = <0x48074000 0xff>;
463 interrupts = <16>, /* OCP compliant interrupt */
464 <59>, /* TX interrupt */
465 <60>; /* RX interrupt */
466 interrupt-names = "common", "tx", "rx";
467 ti,buffer-size = <128>;
468 ti,hwmods = "mcbsp1";
471 dma-names = "tx", "rx";
475 mcbsp2: mcbsp@49022000 {
476 compatible = "ti,omap3-mcbsp";
477 reg = <0x49022000 0xff>,
479 reg-names = "mpu", "sidetone";
480 interrupts = <17>, /* OCP compliant interrupt */
481 <62>, /* TX interrupt */
482 <63>, /* RX interrupt */
484 interrupt-names = "common", "tx", "rx", "sidetone";
485 ti,buffer-size = <1280>;
486 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
489 dma-names = "tx", "rx";
493 mcbsp3: mcbsp@49024000 {
494 compatible = "ti,omap3-mcbsp";
495 reg = <0x49024000 0xff>,
497 reg-names = "mpu", "sidetone";
498 interrupts = <22>, /* OCP compliant interrupt */
499 <89>, /* TX interrupt */
500 <90>, /* RX interrupt */
502 interrupt-names = "common", "tx", "rx", "sidetone";
503 ti,buffer-size = <128>;
504 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
507 dma-names = "tx", "rx";
511 mcbsp4: mcbsp@49026000 {
512 compatible = "ti,omap3-mcbsp";
513 reg = <0x49026000 0xff>;
515 interrupts = <23>, /* OCP compliant interrupt */
516 <54>, /* TX interrupt */
517 <55>; /* RX interrupt */
518 interrupt-names = "common", "tx", "rx";
519 ti,buffer-size = <128>;
520 ti,hwmods = "mcbsp4";
523 dma-names = "tx", "rx";
527 mcbsp5: mcbsp@48096000 {
528 compatible = "ti,omap3-mcbsp";
529 reg = <0x48096000 0xff>;
531 interrupts = <27>, /* OCP compliant interrupt */
532 <81>, /* TX interrupt */
533 <82>; /* RX interrupt */
534 interrupt-names = "common", "tx", "rx";
535 ti,buffer-size = <128>;
536 ti,hwmods = "mcbsp5";
539 dma-names = "tx", "rx";
543 sham: sham@480c3000 {
544 compatible = "ti,omap3-sham";
546 reg = <0x480c3000 0x64>;
550 smartreflex_core: smartreflex@480cb000 {
551 compatible = "ti,omap3-smartreflex-core";
552 ti,hwmods = "smartreflex_core";
553 reg = <0x480cb000 0x400>;
557 smartreflex_mpu_iva: smartreflex@480c9000 {
558 compatible = "ti,omap3-smartreflex-iva";
559 ti,hwmods = "smartreflex_mpu_iva";
560 reg = <0x480c9000 0x400>;
564 timer1: timer@48318000 {
565 compatible = "ti,omap3430-timer";
566 reg = <0x48318000 0x400>;
568 ti,hwmods = "timer1";
572 timer2: timer@49032000 {
573 compatible = "ti,omap3430-timer";
574 reg = <0x49032000 0x400>;
576 ti,hwmods = "timer2";
579 timer3: timer@49034000 {
580 compatible = "ti,omap3430-timer";
581 reg = <0x49034000 0x400>;
583 ti,hwmods = "timer3";
586 timer4: timer@49036000 {
587 compatible = "ti,omap3430-timer";
588 reg = <0x49036000 0x400>;
590 ti,hwmods = "timer4";
593 timer5: timer@49038000 {
594 compatible = "ti,omap3430-timer";
595 reg = <0x49038000 0x400>;
597 ti,hwmods = "timer5";
601 timer6: timer@4903a000 {
602 compatible = "ti,omap3430-timer";
603 reg = <0x4903a000 0x400>;
605 ti,hwmods = "timer6";
609 timer7: timer@4903c000 {
610 compatible = "ti,omap3430-timer";
611 reg = <0x4903c000 0x400>;
613 ti,hwmods = "timer7";
617 timer8: timer@4903e000 {
618 compatible = "ti,omap3430-timer";
619 reg = <0x4903e000 0x400>;
621 ti,hwmods = "timer8";
626 timer9: timer@49040000 {
627 compatible = "ti,omap3430-timer";
628 reg = <0x49040000 0x400>;
630 ti,hwmods = "timer9";
634 timer10: timer@48086000 {
635 compatible = "ti,omap3430-timer";
636 reg = <0x48086000 0x400>;
638 ti,hwmods = "timer10";
642 timer11: timer@48088000 {
643 compatible = "ti,omap3430-timer";
644 reg = <0x48088000 0x400>;
646 ti,hwmods = "timer11";
650 timer12: timer@48304000 {
651 compatible = "ti,omap3430-timer";
652 reg = <0x48304000 0x400>;
654 ti,hwmods = "timer12";
659 usbhstll: usbhstll@48062000 {
660 compatible = "ti,usbhs-tll";
661 reg = <0x48062000 0x1000>;
663 ti,hwmods = "usb_tll_hs";
666 usbhshost: usbhshost@48064000 {
667 compatible = "ti,usbhs-host";
668 reg = <0x48064000 0x400>;
669 ti,hwmods = "usb_host_hs";
670 #address-cells = <1>;
674 usbhsohci: ohci@48064400 {
675 compatible = "ti,ohci-omap3";
676 reg = <0x48064400 0x400>;
677 interrupt-parent = <&intc>;
681 usbhsehci: ehci@48064800 {
682 compatible = "ti,ehci-omap";
683 reg = <0x48064800 0x400>;
684 interrupt-parent = <&intc>;
689 gpmc: gpmc@6e000000 {
690 compatible = "ti,omap3430-gpmc";
692 reg = <0x6e000000 0x02d0>;
695 gpmc,num-waitpins = <4>;
696 #address-cells = <2>;
700 usb_otg_hs: usb_otg_hs@480ab000 {
701 compatible = "ti,omap3-musb";
702 reg = <0x480ab000 0x1000>;
703 interrupts = <92>, <93>;
704 interrupt-names = "mc", "dma";
705 ti,hwmods = "usb_otg_hs";
712 compatible = "ti,omap3-dss";
713 reg = <0x48050000 0x200>;
715 ti,hwmods = "dss_core";
716 clocks = <&dss1_alwon_fck>;
718 #address-cells = <1>;
723 compatible = "ti,omap3-dispc";
724 reg = <0x48050400 0x400>;
726 ti,hwmods = "dss_dispc";
727 clocks = <&dss1_alwon_fck>;
731 dsi: encoder@4804fc00 {
732 compatible = "ti,omap3-dsi";
733 reg = <0x4804fc00 0x200>,
736 reg-names = "proto", "phy", "pll";
739 ti,hwmods = "dss_dsi1";
740 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
741 clock-names = "fck", "sys_clk";
744 rfbi: encoder@48050800 {
745 compatible = "ti,omap3-rfbi";
746 reg = <0x48050800 0x100>;
748 ti,hwmods = "dss_rfbi";
749 clocks = <&dss1_alwon_fck>, <&dss_ick>;
750 clock-names = "fck", "ick";
753 venc: encoder@48050c00 {
754 compatible = "ti,omap3-venc";
755 reg = <0x48050c00 0x100>;
757 ti,hwmods = "dss_venc";
758 clocks = <&dss_tv_fck>;
763 ssi: ssi-controller@48058000 {
764 compatible = "ti,omap3-ssi";
769 reg = <0x48058000 0x1000>,
775 interrupt-names = "gdd_mpu";
777 #address-cells = <1>;
781 ssi_port1: ssi-port@4805a000 {
782 compatible = "ti,omap3-ssi-port";
784 reg = <0x4805a000 0x800>,
789 interrupt-parent = <&intc>;
794 ssi_port2: ssi-port@4805b000 {
795 compatible = "ti,omap3-ssi-port";
797 reg = <0x4805b000 0x800>,
802 interrupt-parent = <&intc>;
810 /include/ "omap3xxx-clocks.dtsi"