2 * Device Tree Source for OMAP3 clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 virt_16_8m_ck: virt_16_8m_ck {
13 compatible = "fixed-clock";
14 clock-frequency = <16800000>;
17 osc_sys_ck: osc_sys_ck {
19 compatible = "ti,mux-clock";
20 clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
26 compatible = "ti,divider-clock";
27 clocks = <&osc_sys_ck>;
31 ti,index-starts-at-one;
34 sys_clkout1: sys_clkout1 {
36 compatible = "ti,gate-clock";
37 clocks = <&osc_sys_ck>;
42 dpll3_x2_ck: dpll3_x2_ck {
44 compatible = "fixed-factor-clock";
50 dpll3_m2x2_ck: dpll3_m2x2_ck {
52 compatible = "fixed-factor-clock";
53 clocks = <&dpll3_m2_ck>;
58 dpll4_x2_ck: dpll4_x2_ck {
60 compatible = "fixed-factor-clock";
66 corex2_fck: corex2_fck {
68 compatible = "fixed-factor-clock";
69 clocks = <&dpll3_m2x2_ck>;
74 wkup_l4_ick: wkup_l4_ick {
76 compatible = "fixed-factor-clock";
83 mcbsp5_mux_fck: mcbsp5_mux_fck {
85 compatible = "ti,composite-mux-clock";
86 clocks = <&core_96m_fck>, <&mcbsp_clks>;
91 mcbsp5_fck: mcbsp5_fck {
93 compatible = "ti,composite-clock";
94 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
97 mcbsp1_mux_fck: mcbsp1_mux_fck {
99 compatible = "ti,composite-mux-clock";
100 clocks = <&core_96m_fck>, <&mcbsp_clks>;
105 mcbsp1_fck: mcbsp1_fck {
107 compatible = "ti,composite-clock";
108 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
111 mcbsp2_mux_fck: mcbsp2_mux_fck {
113 compatible = "ti,composite-mux-clock";
114 clocks = <&per_96m_fck>, <&mcbsp_clks>;
119 mcbsp2_fck: mcbsp2_fck {
121 compatible = "ti,composite-clock";
122 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
125 mcbsp3_mux_fck: mcbsp3_mux_fck {
127 compatible = "ti,composite-mux-clock";
128 clocks = <&per_96m_fck>, <&mcbsp_clks>;
132 mcbsp3_fck: mcbsp3_fck {
134 compatible = "ti,composite-clock";
135 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
138 mcbsp4_mux_fck: mcbsp4_mux_fck {
140 compatible = "ti,composite-mux-clock";
141 clocks = <&per_96m_fck>, <&mcbsp_clks>;
146 mcbsp4_fck: mcbsp4_fck {
148 compatible = "ti,composite-clock";
149 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
153 dummy_apb_pclk: dummy_apb_pclk {
155 compatible = "fixed-clock";
156 clock-frequency = <0x0>;
159 omap_32k_fck: omap_32k_fck {
161 compatible = "fixed-clock";
162 clock-frequency = <32768>;
165 virt_12m_ck: virt_12m_ck {
167 compatible = "fixed-clock";
168 clock-frequency = <12000000>;
171 virt_13m_ck: virt_13m_ck {
173 compatible = "fixed-clock";
174 clock-frequency = <13000000>;
177 virt_19200000_ck: virt_19200000_ck {
179 compatible = "fixed-clock";
180 clock-frequency = <19200000>;
183 virt_26000000_ck: virt_26000000_ck {
185 compatible = "fixed-clock";
186 clock-frequency = <26000000>;
189 virt_38_4m_ck: virt_38_4m_ck {
191 compatible = "fixed-clock";
192 clock-frequency = <38400000>;
197 compatible = "ti,omap3-dpll-per-clock";
198 clocks = <&sys_ck>, <&sys_ck>;
199 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
202 dpll4_m2_ck: dpll4_m2_ck {
204 compatible = "ti,divider-clock";
205 clocks = <&dpll4_ck>;
208 ti,index-starts-at-one;
211 dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
213 compatible = "fixed-factor-clock";
214 clocks = <&dpll4_m2_ck>;
219 dpll4_m2x2_ck: dpll4_m2x2_ck {
221 compatible = "ti,gate-clock";
222 clocks = <&dpll4_m2x2_mul_ck>;
223 ti,bit-shift = <0x1b>;
225 ti,set-bit-to-disable;
228 omap_96m_alwon_fck: omap_96m_alwon_fck {
230 compatible = "fixed-factor-clock";
231 clocks = <&dpll4_m2x2_ck>;
238 compatible = "ti,omap3-dpll-core-clock";
239 clocks = <&sys_ck>, <&sys_ck>;
240 reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
243 dpll3_m3_ck: dpll3_m3_ck {
245 compatible = "ti,divider-clock";
246 clocks = <&dpll3_ck>;
250 ti,index-starts-at-one;
253 dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
255 compatible = "fixed-factor-clock";
256 clocks = <&dpll3_m3_ck>;
261 dpll3_m3x2_ck: dpll3_m3x2_ck {
263 compatible = "ti,gate-clock";
264 clocks = <&dpll3_m3x2_mul_ck>;
265 ti,bit-shift = <0xc>;
267 ti,set-bit-to-disable;
270 emu_core_alwon_ck: emu_core_alwon_ck {
272 compatible = "fixed-factor-clock";
273 clocks = <&dpll3_m3x2_ck>;
278 sys_altclk: sys_altclk {
280 compatible = "fixed-clock";
281 clock-frequency = <0x0>;
284 mcbsp_clks: mcbsp_clks {
286 compatible = "fixed-clock";
287 clock-frequency = <0x0>;
290 dpll3_m2_ck: dpll3_m2_ck {
292 compatible = "ti,divider-clock";
293 clocks = <&dpll3_ck>;
297 ti,index-starts-at-one;
302 compatible = "fixed-factor-clock";
303 clocks = <&dpll3_m2_ck>;
308 dpll1_fck: dpll1_fck {
310 compatible = "ti,divider-clock";
315 ti,index-starts-at-one;
320 compatible = "ti,omap3-dpll-clock";
321 clocks = <&sys_ck>, <&dpll1_fck>;
322 reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
325 dpll1_x2_ck: dpll1_x2_ck {
327 compatible = "fixed-factor-clock";
328 clocks = <&dpll1_ck>;
333 dpll1_x2m2_ck: dpll1_x2m2_ck {
335 compatible = "ti,divider-clock";
336 clocks = <&dpll1_x2_ck>;
339 ti,index-starts-at-one;
342 cm_96m_fck: cm_96m_fck {
344 compatible = "fixed-factor-clock";
345 clocks = <&omap_96m_alwon_fck>;
350 omap_96m_fck: omap_96m_fck {
352 compatible = "ti,mux-clock";
353 clocks = <&cm_96m_fck>, <&sys_ck>;
358 dpll4_m3_ck: dpll4_m3_ck {
360 compatible = "ti,divider-clock";
361 clocks = <&dpll4_ck>;
365 ti,index-starts-at-one;
368 dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
370 compatible = "fixed-factor-clock";
371 clocks = <&dpll4_m3_ck>;
376 dpll4_m3x2_ck: dpll4_m3x2_ck {
378 compatible = "ti,gate-clock";
379 clocks = <&dpll4_m3x2_mul_ck>;
380 ti,bit-shift = <0x1c>;
382 ti,set-bit-to-disable;
385 omap_54m_fck: omap_54m_fck {
387 compatible = "ti,mux-clock";
388 clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
393 cm_96m_d2_fck: cm_96m_d2_fck {
395 compatible = "fixed-factor-clock";
396 clocks = <&cm_96m_fck>;
401 omap_48m_fck: omap_48m_fck {
403 compatible = "ti,mux-clock";
404 clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
409 omap_12m_fck: omap_12m_fck {
411 compatible = "fixed-factor-clock";
412 clocks = <&omap_48m_fck>;
417 dpll4_m4_ck: dpll4_m4_ck {
419 compatible = "ti,divider-clock";
420 clocks = <&dpll4_ck>;
423 ti,index-starts-at-one;
426 dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
428 compatible = "fixed-factor-clock";
429 clocks = <&dpll4_m4_ck>;
434 dpll4_m4x2_ck: dpll4_m4x2_ck {
436 compatible = "ti,gate-clock";
437 clocks = <&dpll4_m4x2_mul_ck>;
438 ti,bit-shift = <0x1d>;
440 ti,set-bit-to-disable;
443 dpll4_m5_ck: dpll4_m5_ck {
445 compatible = "ti,divider-clock";
446 clocks = <&dpll4_ck>;
449 ti,index-starts-at-one;
452 dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
454 compatible = "fixed-factor-clock";
455 clocks = <&dpll4_m5_ck>;
460 dpll4_m5x2_ck: dpll4_m5x2_ck {
462 compatible = "ti,gate-clock";
463 clocks = <&dpll4_m5x2_mul_ck>;
464 ti,bit-shift = <0x1e>;
466 ti,set-bit-to-disable;
469 dpll4_m6_ck: dpll4_m6_ck {
471 compatible = "ti,divider-clock";
472 clocks = <&dpll4_ck>;
476 ti,index-starts-at-one;
479 dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
481 compatible = "fixed-factor-clock";
482 clocks = <&dpll4_m6_ck>;
487 dpll4_m6x2_ck: dpll4_m6x2_ck {
489 compatible = "ti,gate-clock";
490 clocks = <&dpll4_m6x2_mul_ck>;
491 ti,bit-shift = <0x1f>;
493 ti,set-bit-to-disable;
496 emu_per_alwon_ck: emu_per_alwon_ck {
498 compatible = "fixed-factor-clock";
499 clocks = <&dpll4_m6x2_ck>;
504 clkout2_src_gate_ck: clkout2_src_gate_ck {
506 compatible = "ti,composite-no-wait-gate-clock";
512 clkout2_src_mux_ck: clkout2_src_mux_ck {
514 compatible = "ti,composite-mux-clock";
515 clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
519 clkout2_src_ck: clkout2_src_ck {
521 compatible = "ti,composite-clock";
522 clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
525 sys_clkout2: sys_clkout2 {
527 compatible = "ti,divider-clock";
528 clocks = <&clkout2_src_ck>;
532 ti,index-power-of-two;
537 compatible = "fixed-factor-clock";
538 clocks = <&dpll1_x2m2_ck>;
545 compatible = "ti,divider-clock";
551 emu_mpu_alwon_ck: emu_mpu_alwon_ck {
553 compatible = "fixed-factor-clock";
561 compatible = "ti,divider-clock";
565 ti,index-starts-at-one;
570 compatible = "ti,divider-clock";
575 ti,index-starts-at-one;
580 compatible = "ti,divider-clock";
585 ti,index-starts-at-one;
588 gpt10_gate_fck: gpt10_gate_fck {
590 compatible = "ti,composite-gate-clock";
596 gpt10_mux_fck: gpt10_mux_fck {
598 compatible = "ti,composite-mux-clock";
599 clocks = <&omap_32k_fck>, <&sys_ck>;
604 gpt10_fck: gpt10_fck {
606 compatible = "ti,composite-clock";
607 clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
610 gpt11_gate_fck: gpt11_gate_fck {
612 compatible = "ti,composite-gate-clock";
618 gpt11_mux_fck: gpt11_mux_fck {
620 compatible = "ti,composite-mux-clock";
621 clocks = <&omap_32k_fck>, <&sys_ck>;
626 gpt11_fck: gpt11_fck {
628 compatible = "ti,composite-clock";
629 clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
632 core_96m_fck: core_96m_fck {
634 compatible = "fixed-factor-clock";
635 clocks = <&omap_96m_fck>;
640 mmchs2_fck: mmchs2_fck {
642 compatible = "ti,wait-gate-clock";
643 clocks = <&core_96m_fck>;
648 mmchs1_fck: mmchs1_fck {
650 compatible = "ti,wait-gate-clock";
651 clocks = <&core_96m_fck>;
658 compatible = "ti,wait-gate-clock";
659 clocks = <&core_96m_fck>;
666 compatible = "ti,wait-gate-clock";
667 clocks = <&core_96m_fck>;
674 compatible = "ti,wait-gate-clock";
675 clocks = <&core_96m_fck>;
680 mcbsp5_gate_fck: mcbsp5_gate_fck {
682 compatible = "ti,composite-gate-clock";
683 clocks = <&mcbsp_clks>;
688 mcbsp1_gate_fck: mcbsp1_gate_fck {
690 compatible = "ti,composite-gate-clock";
691 clocks = <&mcbsp_clks>;
696 core_48m_fck: core_48m_fck {
698 compatible = "fixed-factor-clock";
699 clocks = <&omap_48m_fck>;
704 mcspi4_fck: mcspi4_fck {
706 compatible = "ti,wait-gate-clock";
707 clocks = <&core_48m_fck>;
712 mcspi3_fck: mcspi3_fck {
714 compatible = "ti,wait-gate-clock";
715 clocks = <&core_48m_fck>;
720 mcspi2_fck: mcspi2_fck {
722 compatible = "ti,wait-gate-clock";
723 clocks = <&core_48m_fck>;
728 mcspi1_fck: mcspi1_fck {
730 compatible = "ti,wait-gate-clock";
731 clocks = <&core_48m_fck>;
736 uart2_fck: uart2_fck {
738 compatible = "ti,wait-gate-clock";
739 clocks = <&core_48m_fck>;
744 uart1_fck: uart1_fck {
746 compatible = "ti,wait-gate-clock";
747 clocks = <&core_48m_fck>;
752 core_12m_fck: core_12m_fck {
754 compatible = "fixed-factor-clock";
755 clocks = <&omap_12m_fck>;
762 compatible = "ti,wait-gate-clock";
763 clocks = <&core_12m_fck>;
768 core_l3_ick: core_l3_ick {
770 compatible = "fixed-factor-clock";
778 compatible = "ti,wait-gate-clock";
779 clocks = <&core_l3_ick>;
786 compatible = "fixed-factor-clock";
787 clocks = <&core_l3_ick>;
792 core_l4_ick: core_l4_ick {
794 compatible = "fixed-factor-clock";
800 mmchs2_ick: mmchs2_ick {
802 compatible = "ti,omap3-interface-clock";
803 clocks = <&core_l4_ick>;
808 mmchs1_ick: mmchs1_ick {
810 compatible = "ti,omap3-interface-clock";
811 clocks = <&core_l4_ick>;
818 compatible = "ti,omap3-interface-clock";
819 clocks = <&core_l4_ick>;
824 mcspi4_ick: mcspi4_ick {
826 compatible = "ti,omap3-interface-clock";
827 clocks = <&core_l4_ick>;
832 mcspi3_ick: mcspi3_ick {
834 compatible = "ti,omap3-interface-clock";
835 clocks = <&core_l4_ick>;
840 mcspi2_ick: mcspi2_ick {
842 compatible = "ti,omap3-interface-clock";
843 clocks = <&core_l4_ick>;
848 mcspi1_ick: mcspi1_ick {
850 compatible = "ti,omap3-interface-clock";
851 clocks = <&core_l4_ick>;
858 compatible = "ti,omap3-interface-clock";
859 clocks = <&core_l4_ick>;
866 compatible = "ti,omap3-interface-clock";
867 clocks = <&core_l4_ick>;
874 compatible = "ti,omap3-interface-clock";
875 clocks = <&core_l4_ick>;
880 uart2_ick: uart2_ick {
882 compatible = "ti,omap3-interface-clock";
883 clocks = <&core_l4_ick>;
888 uart1_ick: uart1_ick {
890 compatible = "ti,omap3-interface-clock";
891 clocks = <&core_l4_ick>;
896 gpt11_ick: gpt11_ick {
898 compatible = "ti,omap3-interface-clock";
899 clocks = <&core_l4_ick>;
904 gpt10_ick: gpt10_ick {
906 compatible = "ti,omap3-interface-clock";
907 clocks = <&core_l4_ick>;
912 mcbsp5_ick: mcbsp5_ick {
914 compatible = "ti,omap3-interface-clock";
915 clocks = <&core_l4_ick>;
920 mcbsp1_ick: mcbsp1_ick {
922 compatible = "ti,omap3-interface-clock";
923 clocks = <&core_l4_ick>;
928 omapctrl_ick: omapctrl_ick {
930 compatible = "ti,omap3-interface-clock";
931 clocks = <&core_l4_ick>;
936 dss_tv_fck: dss_tv_fck {
938 compatible = "ti,gate-clock";
939 clocks = <&omap_54m_fck>;
944 dss_96m_fck: dss_96m_fck {
946 compatible = "ti,gate-clock";
947 clocks = <&omap_96m_fck>;
952 dss2_alwon_fck: dss2_alwon_fck {
954 compatible = "ti,gate-clock";
962 compatible = "fixed-clock";
963 clock-frequency = <0>;
966 gpt1_gate_fck: gpt1_gate_fck {
968 compatible = "ti,composite-gate-clock";
974 gpt1_mux_fck: gpt1_mux_fck {
976 compatible = "ti,composite-mux-clock";
977 clocks = <&omap_32k_fck>, <&sys_ck>;
983 compatible = "ti,composite-clock";
984 clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
989 compatible = "ti,omap3-interface-clock";
990 clocks = <&core_l4_ick>;
995 wkup_32k_fck: wkup_32k_fck {
997 compatible = "fixed-factor-clock";
998 clocks = <&omap_32k_fck>;
1003 gpio1_dbck: gpio1_dbck {
1005 compatible = "ti,gate-clock";
1006 clocks = <&wkup_32k_fck>;
1011 sha12_ick: sha12_ick {
1013 compatible = "ti,omap3-interface-clock";
1014 clocks = <&core_l4_ick>;
1016 ti,bit-shift = <27>;
1019 wdt2_fck: wdt2_fck {
1021 compatible = "ti,wait-gate-clock";
1022 clocks = <&wkup_32k_fck>;
1027 wdt2_ick: wdt2_ick {
1029 compatible = "ti,omap3-interface-clock";
1030 clocks = <&wkup_l4_ick>;
1035 wdt1_ick: wdt1_ick {
1037 compatible = "ti,omap3-interface-clock";
1038 clocks = <&wkup_l4_ick>;
1043 gpio1_ick: gpio1_ick {
1045 compatible = "ti,omap3-interface-clock";
1046 clocks = <&wkup_l4_ick>;
1051 omap_32ksync_ick: omap_32ksync_ick {
1053 compatible = "ti,omap3-interface-clock";
1054 clocks = <&wkup_l4_ick>;
1059 gpt12_ick: gpt12_ick {
1061 compatible = "ti,omap3-interface-clock";
1062 clocks = <&wkup_l4_ick>;
1067 gpt1_ick: gpt1_ick {
1069 compatible = "ti,omap3-interface-clock";
1070 clocks = <&wkup_l4_ick>;
1075 per_96m_fck: per_96m_fck {
1077 compatible = "fixed-factor-clock";
1078 clocks = <&omap_96m_alwon_fck>;
1083 per_48m_fck: per_48m_fck {
1085 compatible = "fixed-factor-clock";
1086 clocks = <&omap_48m_fck>;
1091 uart3_fck: uart3_fck {
1093 compatible = "ti,wait-gate-clock";
1094 clocks = <&per_48m_fck>;
1096 ti,bit-shift = <11>;
1099 gpt2_gate_fck: gpt2_gate_fck {
1101 compatible = "ti,composite-gate-clock";
1107 gpt2_mux_fck: gpt2_mux_fck {
1109 compatible = "ti,composite-mux-clock";
1110 clocks = <&omap_32k_fck>, <&sys_ck>;
1114 gpt2_fck: gpt2_fck {
1116 compatible = "ti,composite-clock";
1117 clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
1120 gpt3_gate_fck: gpt3_gate_fck {
1122 compatible = "ti,composite-gate-clock";
1128 gpt3_mux_fck: gpt3_mux_fck {
1130 compatible = "ti,composite-mux-clock";
1131 clocks = <&omap_32k_fck>, <&sys_ck>;
1136 gpt3_fck: gpt3_fck {
1138 compatible = "ti,composite-clock";
1139 clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
1142 gpt4_gate_fck: gpt4_gate_fck {
1144 compatible = "ti,composite-gate-clock";
1150 gpt4_mux_fck: gpt4_mux_fck {
1152 compatible = "ti,composite-mux-clock";
1153 clocks = <&omap_32k_fck>, <&sys_ck>;
1158 gpt4_fck: gpt4_fck {
1160 compatible = "ti,composite-clock";
1161 clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
1164 gpt5_gate_fck: gpt5_gate_fck {
1166 compatible = "ti,composite-gate-clock";
1172 gpt5_mux_fck: gpt5_mux_fck {
1174 compatible = "ti,composite-mux-clock";
1175 clocks = <&omap_32k_fck>, <&sys_ck>;
1180 gpt5_fck: gpt5_fck {
1182 compatible = "ti,composite-clock";
1183 clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
1186 gpt6_gate_fck: gpt6_gate_fck {
1188 compatible = "ti,composite-gate-clock";
1194 gpt6_mux_fck: gpt6_mux_fck {
1196 compatible = "ti,composite-mux-clock";
1197 clocks = <&omap_32k_fck>, <&sys_ck>;
1202 gpt6_fck: gpt6_fck {
1204 compatible = "ti,composite-clock";
1205 clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
1208 gpt7_gate_fck: gpt7_gate_fck {
1210 compatible = "ti,composite-gate-clock";
1216 gpt7_mux_fck: gpt7_mux_fck {
1218 compatible = "ti,composite-mux-clock";
1219 clocks = <&omap_32k_fck>, <&sys_ck>;
1224 gpt7_fck: gpt7_fck {
1226 compatible = "ti,composite-clock";
1227 clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
1230 gpt8_gate_fck: gpt8_gate_fck {
1232 compatible = "ti,composite-gate-clock";
1238 gpt8_mux_fck: gpt8_mux_fck {
1240 compatible = "ti,composite-mux-clock";
1241 clocks = <&omap_32k_fck>, <&sys_ck>;
1246 gpt8_fck: gpt8_fck {
1248 compatible = "ti,composite-clock";
1249 clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
1252 gpt9_gate_fck: gpt9_gate_fck {
1254 compatible = "ti,composite-gate-clock";
1256 ti,bit-shift = <10>;
1260 gpt9_mux_fck: gpt9_mux_fck {
1262 compatible = "ti,composite-mux-clock";
1263 clocks = <&omap_32k_fck>, <&sys_ck>;
1268 gpt9_fck: gpt9_fck {
1270 compatible = "ti,composite-clock";
1271 clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
1274 per_32k_alwon_fck: per_32k_alwon_fck {
1276 compatible = "fixed-factor-clock";
1277 clocks = <&omap_32k_fck>;
1282 gpio6_dbck: gpio6_dbck {
1284 compatible = "ti,gate-clock";
1285 clocks = <&per_32k_alwon_fck>;
1287 ti,bit-shift = <17>;
1290 gpio5_dbck: gpio5_dbck {
1292 compatible = "ti,gate-clock";
1293 clocks = <&per_32k_alwon_fck>;
1295 ti,bit-shift = <16>;
1298 gpio4_dbck: gpio4_dbck {
1300 compatible = "ti,gate-clock";
1301 clocks = <&per_32k_alwon_fck>;
1303 ti,bit-shift = <15>;
1306 gpio3_dbck: gpio3_dbck {
1308 compatible = "ti,gate-clock";
1309 clocks = <&per_32k_alwon_fck>;
1311 ti,bit-shift = <14>;
1314 gpio2_dbck: gpio2_dbck {
1316 compatible = "ti,gate-clock";
1317 clocks = <&per_32k_alwon_fck>;
1319 ti,bit-shift = <13>;
1322 wdt3_fck: wdt3_fck {
1324 compatible = "ti,wait-gate-clock";
1325 clocks = <&per_32k_alwon_fck>;
1327 ti,bit-shift = <12>;
1330 per_l4_ick: per_l4_ick {
1332 compatible = "fixed-factor-clock";
1338 gpio6_ick: gpio6_ick {
1340 compatible = "ti,omap3-interface-clock";
1341 clocks = <&per_l4_ick>;
1343 ti,bit-shift = <17>;
1346 gpio5_ick: gpio5_ick {
1348 compatible = "ti,omap3-interface-clock";
1349 clocks = <&per_l4_ick>;
1351 ti,bit-shift = <16>;
1354 gpio4_ick: gpio4_ick {
1356 compatible = "ti,omap3-interface-clock";
1357 clocks = <&per_l4_ick>;
1359 ti,bit-shift = <15>;
1362 gpio3_ick: gpio3_ick {
1364 compatible = "ti,omap3-interface-clock";
1365 clocks = <&per_l4_ick>;
1367 ti,bit-shift = <14>;
1370 gpio2_ick: gpio2_ick {
1372 compatible = "ti,omap3-interface-clock";
1373 clocks = <&per_l4_ick>;
1375 ti,bit-shift = <13>;
1378 wdt3_ick: wdt3_ick {
1380 compatible = "ti,omap3-interface-clock";
1381 clocks = <&per_l4_ick>;
1383 ti,bit-shift = <12>;
1386 uart3_ick: uart3_ick {
1388 compatible = "ti,omap3-interface-clock";
1389 clocks = <&per_l4_ick>;
1391 ti,bit-shift = <11>;
1394 uart4_ick: uart4_ick {
1396 compatible = "ti,omap3-interface-clock";
1397 clocks = <&per_l4_ick>;
1399 ti,bit-shift = <18>;
1402 gpt9_ick: gpt9_ick {
1404 compatible = "ti,omap3-interface-clock";
1405 clocks = <&per_l4_ick>;
1407 ti,bit-shift = <10>;
1410 gpt8_ick: gpt8_ick {
1412 compatible = "ti,omap3-interface-clock";
1413 clocks = <&per_l4_ick>;
1418 gpt7_ick: gpt7_ick {
1420 compatible = "ti,omap3-interface-clock";
1421 clocks = <&per_l4_ick>;
1426 gpt6_ick: gpt6_ick {
1428 compatible = "ti,omap3-interface-clock";
1429 clocks = <&per_l4_ick>;
1434 gpt5_ick: gpt5_ick {
1436 compatible = "ti,omap3-interface-clock";
1437 clocks = <&per_l4_ick>;
1442 gpt4_ick: gpt4_ick {
1444 compatible = "ti,omap3-interface-clock";
1445 clocks = <&per_l4_ick>;
1450 gpt3_ick: gpt3_ick {
1452 compatible = "ti,omap3-interface-clock";
1453 clocks = <&per_l4_ick>;
1458 gpt2_ick: gpt2_ick {
1460 compatible = "ti,omap3-interface-clock";
1461 clocks = <&per_l4_ick>;
1466 mcbsp2_ick: mcbsp2_ick {
1468 compatible = "ti,omap3-interface-clock";
1469 clocks = <&per_l4_ick>;
1474 mcbsp3_ick: mcbsp3_ick {
1476 compatible = "ti,omap3-interface-clock";
1477 clocks = <&per_l4_ick>;
1482 mcbsp4_ick: mcbsp4_ick {
1484 compatible = "ti,omap3-interface-clock";
1485 clocks = <&per_l4_ick>;
1490 mcbsp2_gate_fck: mcbsp2_gate_fck {
1492 compatible = "ti,composite-gate-clock";
1493 clocks = <&mcbsp_clks>;
1498 mcbsp3_gate_fck: mcbsp3_gate_fck {
1500 compatible = "ti,composite-gate-clock";
1501 clocks = <&mcbsp_clks>;
1506 mcbsp4_gate_fck: mcbsp4_gate_fck {
1508 compatible = "ti,composite-gate-clock";
1509 clocks = <&mcbsp_clks>;
1514 emu_src_mux_ck: emu_src_mux_ck {
1516 compatible = "ti,mux-clock";
1517 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
1521 emu_src_ck: emu_src_ck {
1523 compatible = "ti,clkdm-gate-clock";
1524 clocks = <&emu_src_mux_ck>;
1527 pclk_fck: pclk_fck {
1529 compatible = "ti,divider-clock";
1530 clocks = <&emu_src_ck>;
1534 ti,index-starts-at-one;
1537 pclkx2_fck: pclkx2_fck {
1539 compatible = "ti,divider-clock";
1540 clocks = <&emu_src_ck>;
1544 ti,index-starts-at-one;
1547 atclk_fck: atclk_fck {
1549 compatible = "ti,divider-clock";
1550 clocks = <&emu_src_ck>;
1554 ti,index-starts-at-one;
1557 traceclk_src_fck: traceclk_src_fck {
1559 compatible = "ti,mux-clock";
1560 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
1565 traceclk_fck: traceclk_fck {
1567 compatible = "ti,divider-clock";
1568 clocks = <&traceclk_src_fck>;
1569 ti,bit-shift = <11>;
1572 ti,index-starts-at-one;
1575 secure_32k_fck: secure_32k_fck {
1577 compatible = "fixed-clock";
1578 clock-frequency = <32768>;
1581 gpt12_fck: gpt12_fck {
1583 compatible = "fixed-factor-clock";
1584 clocks = <&secure_32k_fck>;
1589 wdt1_fck: wdt1_fck {
1591 compatible = "fixed-factor-clock";
1592 clocks = <&secure_32k_fck>;
1599 core_l3_clkdm: core_l3_clkdm {
1600 compatible = "ti,clockdomain";
1601 clocks = <&sdrc_ick>;
1604 dpll3_clkdm: dpll3_clkdm {
1605 compatible = "ti,clockdomain";
1606 clocks = <&dpll3_ck>;
1609 dpll1_clkdm: dpll1_clkdm {
1610 compatible = "ti,clockdomain";
1611 clocks = <&dpll1_ck>;
1614 per_clkdm: per_clkdm {
1615 compatible = "ti,clockdomain";
1616 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
1617 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
1618 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
1619 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
1620 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
1621 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
1622 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
1626 emu_clkdm: emu_clkdm {
1627 compatible = "ti,clockdomain";
1628 clocks = <&emu_src_ck>;
1631 dpll4_clkdm: dpll4_clkdm {
1632 compatible = "ti,clockdomain";
1633 clocks = <&dpll4_ck>;
1636 wkup_clkdm: wkup_clkdm {
1637 compatible = "ti,clockdomain";
1638 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
1639 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
1643 dss_clkdm: dss_clkdm {
1644 compatible = "ti,clockdomain";
1645 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
1648 core_l4_clkdm: core_l4_clkdm {
1649 compatible = "ti,clockdomain";
1650 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
1651 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
1652 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
1653 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
1654 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
1655 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
1656 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
1657 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
1658 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;