2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
13 #include "skeleton.dtsi"
16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
40 clocks = <&dpll_mpu_ck>;
43 clock-latency = <300000>; /* From omap-cpufreq driver */
46 compatible = "arm,cortex-a9";
48 next-level-cache = <&L2>;
53 gic: interrupt-controller@48241000 {
54 compatible = "arm,cortex-a9-gic";
56 #interrupt-cells = <3>;
57 reg = <0x48241000 0x1000>,
61 L2: l2-cache-controller@48242000 {
62 compatible = "arm,pl310-cache";
63 reg = <0x48242000 0x1000>;
68 local-timer@48240600 {
69 compatible = "arm,cortex-a9-twd-timer";
70 reg = <0x48240600 0x20>;
71 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
75 * The soc node represents the soc top level view. It is uses for IPs
76 * that are not memory mapped in the MPU view or for the MPU itself.
79 compatible = "ti,omap-infra";
81 compatible = "ti,omap4-mpu";
86 compatible = "ti,omap3-c64";
91 compatible = "ti,ivahd";
97 * XXX: Use a flat representation of the OMAP4 interconnect.
98 * The real OMAP interconnect network is quite complex.
99 * Since that will not bring real advantage to represent that in DT for
100 * the moment, just use a fake OCP bus entry to represent the whole bus
104 compatible = "ti,omap4-l3-noc", "simple-bus";
105 #address-cells = <1>;
108 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
109 reg = <0x44000000 0x1000>,
112 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
116 compatible = "ti,omap4-cm1";
117 reg = <0x4a004000 0x2000>;
120 #address-cells = <1>;
124 cm1_clockdomains: clockdomains {
129 compatible = "ti,omap4-prm";
130 reg = <0x4a306000 0x3000>;
133 #address-cells = <1>;
137 prm_clockdomains: clockdomains {
142 compatible = "ti,omap4-cm2";
143 reg = <0x4a008000 0x3000>;
146 #address-cells = <1>;
150 cm2_clockdomains: clockdomains {
154 scrm: scrm@4a30a000 {
155 compatible = "ti,omap4-scrm";
156 reg = <0x4a30a000 0x2000>;
158 scrm_clocks: clocks {
159 #address-cells = <1>;
163 scrm_clockdomains: clockdomains {
167 counter32k: counter@4a304000 {
168 compatible = "ti,omap-counter32k";
169 reg = <0x4a304000 0x20>;
170 ti,hwmods = "counter_32k";
173 omap4_pmx_core: pinmux@4a100040 {
174 compatible = "ti,omap4-padconf", "pinctrl-single";
175 reg = <0x4a100040 0x0196>;
176 #address-cells = <1>;
178 #interrupt-cells = <1>;
179 interrupt-controller;
180 pinctrl-single,register-width = <16>;
181 pinctrl-single,function-mask = <0x7fff>;
183 omap4_pmx_wkup: pinmux@4a31e040 {
184 compatible = "ti,omap4-padconf", "pinctrl-single";
185 reg = <0x4a31e040 0x0038>;
186 #address-cells = <1>;
188 #interrupt-cells = <1>;
189 interrupt-controller;
190 pinctrl-single,register-width = <16>;
191 pinctrl-single,function-mask = <0x7fff>;
194 omap4_padconf_global: tisyscon@4a1005a0 {
195 compatible = "syscon";
196 reg = <0x4a1005a0 0x170>;
199 pbias_regulator: pbias_regulator {
200 compatible = "ti,pbias-omap";
202 syscon = <&omap4_padconf_global>;
203 pbias_mmc_reg: pbias_mmc_omap4 {
204 regulator-name = "pbias_mmc_omap4";
205 regulator-min-microvolt = <1800000>;
206 regulator-max-microvolt = <3000000>;
210 sdma: dma-controller@4a056000 {
211 compatible = "ti,omap4430-sdma";
212 reg = <0x4a056000 0x1000>;
213 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
218 #dma-channels = <32>;
219 #dma-requests = <127>;
222 gpio1: gpio@4a310000 {
223 compatible = "ti,omap4-gpio";
224 reg = <0x4a310000 0x200>;
225 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
230 interrupt-controller;
231 #interrupt-cells = <2>;
234 gpio2: gpio@48055000 {
235 compatible = "ti,omap4-gpio";
236 reg = <0x48055000 0x200>;
237 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
241 interrupt-controller;
242 #interrupt-cells = <2>;
245 gpio3: gpio@48057000 {
246 compatible = "ti,omap4-gpio";
247 reg = <0x48057000 0x200>;
248 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
252 interrupt-controller;
253 #interrupt-cells = <2>;
256 gpio4: gpio@48059000 {
257 compatible = "ti,omap4-gpio";
258 reg = <0x48059000 0x200>;
259 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
267 gpio5: gpio@4805b000 {
268 compatible = "ti,omap4-gpio";
269 reg = <0x4805b000 0x200>;
270 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
278 gpio6: gpio@4805d000 {
279 compatible = "ti,omap4-gpio";
280 reg = <0x4805d000 0x200>;
281 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
289 gpmc: gpmc@50000000 {
290 compatible = "ti,omap4430-gpmc";
291 reg = <0x50000000 0x1000>;
292 #address-cells = <2>;
294 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
296 gpmc,num-waitpins = <4>;
299 clocks = <&l3_div_ck>;
303 uart1: serial@4806a000 {
304 compatible = "ti,omap4-uart";
305 reg = <0x4806a000 0x100>;
306 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
308 clock-frequency = <48000000>;
311 uart2: serial@4806c000 {
312 compatible = "ti,omap4-uart";
313 reg = <0x4806c000 0x100>;
314 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
316 clock-frequency = <48000000>;
319 uart3: serial@48020000 {
320 compatible = "ti,omap4-uart";
321 reg = <0x48020000 0x100>;
322 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
324 clock-frequency = <48000000>;
327 uart4: serial@4806e000 {
328 compatible = "ti,omap4-uart";
329 reg = <0x4806e000 0x100>;
330 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
332 clock-frequency = <48000000>;
335 hwspinlock: spinlock@4a0f6000 {
336 compatible = "ti,omap4-hwspinlock";
337 reg = <0x4a0f6000 0x1000>;
338 ti,hwmods = "spinlock";
343 compatible = "ti,omap4-i2c";
344 reg = <0x48070000 0x100>;
345 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
352 compatible = "ti,omap4-i2c";
353 reg = <0x48072000 0x100>;
354 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
355 #address-cells = <1>;
361 compatible = "ti,omap4-i2c";
362 reg = <0x48060000 0x100>;
363 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
364 #address-cells = <1>;
370 compatible = "ti,omap4-i2c";
371 reg = <0x48350000 0x100>;
372 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
373 #address-cells = <1>;
378 mcspi1: spi@48098000 {
379 compatible = "ti,omap4-mcspi";
380 reg = <0x48098000 0x200>;
381 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
382 #address-cells = <1>;
384 ti,hwmods = "mcspi1";
394 dma-names = "tx0", "rx0", "tx1", "rx1",
395 "tx2", "rx2", "tx3", "rx3";
398 mcspi2: spi@4809a000 {
399 compatible = "ti,omap4-mcspi";
400 reg = <0x4809a000 0x200>;
401 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
402 #address-cells = <1>;
404 ti,hwmods = "mcspi2";
410 dma-names = "tx0", "rx0", "tx1", "rx1";
413 mcspi3: spi@480b8000 {
414 compatible = "ti,omap4-mcspi";
415 reg = <0x480b8000 0x200>;
416 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
417 #address-cells = <1>;
419 ti,hwmods = "mcspi3";
421 dmas = <&sdma 15>, <&sdma 16>;
422 dma-names = "tx0", "rx0";
425 mcspi4: spi@480ba000 {
426 compatible = "ti,omap4-mcspi";
427 reg = <0x480ba000 0x200>;
428 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
429 #address-cells = <1>;
431 ti,hwmods = "mcspi4";
433 dmas = <&sdma 70>, <&sdma 71>;
434 dma-names = "tx0", "rx0";
438 compatible = "ti,omap4-hsmmc";
439 reg = <0x4809c000 0x400>;
440 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
443 ti,needs-special-reset;
444 dmas = <&sdma 61>, <&sdma 62>;
445 dma-names = "tx", "rx";
446 pbias-supply = <&pbias_mmc_reg>;
450 compatible = "ti,omap4-hsmmc";
451 reg = <0x480b4000 0x400>;
452 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
454 ti,needs-special-reset;
455 dmas = <&sdma 47>, <&sdma 48>;
456 dma-names = "tx", "rx";
460 compatible = "ti,omap4-hsmmc";
461 reg = <0x480ad000 0x400>;
462 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
464 ti,needs-special-reset;
465 dmas = <&sdma 77>, <&sdma 78>;
466 dma-names = "tx", "rx";
470 compatible = "ti,omap4-hsmmc";
471 reg = <0x480d1000 0x400>;
472 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
474 ti,needs-special-reset;
475 dmas = <&sdma 57>, <&sdma 58>;
476 dma-names = "tx", "rx";
480 compatible = "ti,omap4-hsmmc";
481 reg = <0x480d5000 0x400>;
482 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
484 ti,needs-special-reset;
485 dmas = <&sdma 59>, <&sdma 60>;
486 dma-names = "tx", "rx";
489 mmu_dsp: mmu@4a066000 {
490 compatible = "ti,omap4-iommu";
491 reg = <0x4a066000 0x100>;
492 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
493 ti,hwmods = "mmu_dsp";
496 mmu_ipu: mmu@55082000 {
497 compatible = "ti,omap4-iommu";
498 reg = <0x55082000 0x100>;
499 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
500 ti,hwmods = "mmu_ipu";
501 ti,iommu-bus-err-back;
505 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
506 reg = <0x4a314000 0x80>;
507 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
508 ti,hwmods = "wd_timer2";
511 mcpdm: mcpdm@40132000 {
512 compatible = "ti,omap4-mcpdm";
513 reg = <0x40132000 0x7f>, /* MPU private access */
514 <0x49032000 0x7f>; /* L3 Interconnect */
515 reg-names = "mpu", "dma";
516 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
520 dma-names = "up_link", "dn_link";
524 dmic: dmic@4012e000 {
525 compatible = "ti,omap4-dmic";
526 reg = <0x4012e000 0x7f>, /* MPU private access */
527 <0x4902e000 0x7f>; /* L3 Interconnect */
528 reg-names = "mpu", "dma";
529 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
532 dma-names = "up_link";
536 mcbsp1: mcbsp@40122000 {
537 compatible = "ti,omap4-mcbsp";
538 reg = <0x40122000 0xff>, /* MPU private access */
539 <0x49022000 0xff>; /* L3 Interconnect */
540 reg-names = "mpu", "dma";
541 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
542 interrupt-names = "common";
543 ti,buffer-size = <128>;
544 ti,hwmods = "mcbsp1";
547 dma-names = "tx", "rx";
551 mcbsp2: mcbsp@40124000 {
552 compatible = "ti,omap4-mcbsp";
553 reg = <0x40124000 0xff>, /* MPU private access */
554 <0x49024000 0xff>; /* L3 Interconnect */
555 reg-names = "mpu", "dma";
556 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
557 interrupt-names = "common";
558 ti,buffer-size = <128>;
559 ti,hwmods = "mcbsp2";
562 dma-names = "tx", "rx";
566 mcbsp3: mcbsp@40126000 {
567 compatible = "ti,omap4-mcbsp";
568 reg = <0x40126000 0xff>, /* MPU private access */
569 <0x49026000 0xff>; /* L3 Interconnect */
570 reg-names = "mpu", "dma";
571 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
572 interrupt-names = "common";
573 ti,buffer-size = <128>;
574 ti,hwmods = "mcbsp3";
577 dma-names = "tx", "rx";
581 mcbsp4: mcbsp@48096000 {
582 compatible = "ti,omap4-mcbsp";
583 reg = <0x48096000 0xff>; /* L4 Interconnect */
585 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
586 interrupt-names = "common";
587 ti,buffer-size = <128>;
588 ti,hwmods = "mcbsp4";
591 dma-names = "tx", "rx";
595 keypad: keypad@4a31c000 {
596 compatible = "ti,omap4-keypad";
597 reg = <0x4a31c000 0x80>;
598 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
604 compatible = "ti,omap4-dmm";
605 reg = <0x4e000000 0x800>;
606 interrupts = <0 113 0x4>;
610 emif1: emif@4c000000 {
611 compatible = "ti,emif-4d";
612 reg = <0x4c000000 0x100>;
613 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
617 hw-caps-read-idle-ctrl;
618 hw-caps-ll-interface;
622 emif2: emif@4d000000 {
623 compatible = "ti,emif-4d";
624 reg = <0x4d000000 0x100>;
625 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
629 hw-caps-read-idle-ctrl;
630 hw-caps-ll-interface;
635 compatible = "ti,omap-ocp2scp";
636 reg = <0x4a0ad000 0x1f>;
637 #address-cells = <1>;
640 ti,hwmods = "ocp2scp_usb_phy";
641 usb2_phy: usb2phy@4a0ad080 {
642 compatible = "ti,omap-usb2";
643 reg = <0x4a0ad080 0x58>;
644 ctrl-module = <&omap_control_usb2phy>;
649 timer1: timer@4a318000 {
650 compatible = "ti,omap3430-timer";
651 reg = <0x4a318000 0x80>;
652 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
653 ti,hwmods = "timer1";
657 timer2: timer@48032000 {
658 compatible = "ti,omap3430-timer";
659 reg = <0x48032000 0x80>;
660 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
661 ti,hwmods = "timer2";
664 timer3: timer@48034000 {
665 compatible = "ti,omap4430-timer";
666 reg = <0x48034000 0x80>;
667 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
668 ti,hwmods = "timer3";
671 timer4: timer@48036000 {
672 compatible = "ti,omap4430-timer";
673 reg = <0x48036000 0x80>;
674 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
675 ti,hwmods = "timer4";
678 timer5: timer@40138000 {
679 compatible = "ti,omap4430-timer";
680 reg = <0x40138000 0x80>,
682 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
683 ti,hwmods = "timer5";
687 timer6: timer@4013a000 {
688 compatible = "ti,omap4430-timer";
689 reg = <0x4013a000 0x80>,
691 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
692 ti,hwmods = "timer6";
696 timer7: timer@4013c000 {
697 compatible = "ti,omap4430-timer";
698 reg = <0x4013c000 0x80>,
700 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
701 ti,hwmods = "timer7";
705 timer8: timer@4013e000 {
706 compatible = "ti,omap4430-timer";
707 reg = <0x4013e000 0x80>,
709 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
710 ti,hwmods = "timer8";
715 timer9: timer@4803e000 {
716 compatible = "ti,omap4430-timer";
717 reg = <0x4803e000 0x80>;
718 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
719 ti,hwmods = "timer9";
723 timer10: timer@48086000 {
724 compatible = "ti,omap3430-timer";
725 reg = <0x48086000 0x80>;
726 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
727 ti,hwmods = "timer10";
731 timer11: timer@48088000 {
732 compatible = "ti,omap4430-timer";
733 reg = <0x48088000 0x80>;
734 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
735 ti,hwmods = "timer11";
739 usbhstll: usbhstll@4a062000 {
740 compatible = "ti,usbhs-tll";
741 reg = <0x4a062000 0x1000>;
742 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
743 ti,hwmods = "usb_tll_hs";
746 usbhshost: usbhshost@4a064000 {
747 compatible = "ti,usbhs-host";
748 reg = <0x4a064000 0x800>;
749 ti,hwmods = "usb_host_hs";
750 #address-cells = <1>;
753 clocks = <&init_60m_fclk>,
756 clock-names = "refclk_60m_int",
760 usbhsohci: ohci@4a064800 {
761 compatible = "ti,ohci-omap3";
762 reg = <0x4a064800 0x400>;
763 interrupt-parent = <&gic>;
764 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
767 usbhsehci: ehci@4a064c00 {
768 compatible = "ti,ehci-omap";
769 reg = <0x4a064c00 0x400>;
770 interrupt-parent = <&gic>;
771 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
775 omap_control_usb2phy: control-phy@4a002300 {
776 compatible = "ti,control-phy-usb2";
777 reg = <0x4a002300 0x4>;
781 omap_control_usbotg: control-phy@4a00233c {
782 compatible = "ti,control-phy-otghs";
783 reg = <0x4a00233c 0x4>;
784 reg-names = "otghs_control";
787 usb_otg_hs: usb_otg_hs@4a0ab000 {
788 compatible = "ti,omap4-musb";
789 reg = <0x4a0ab000 0x7ff>;
790 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
791 interrupt-names = "mc", "dma";
792 ti,hwmods = "usb_otg_hs";
793 usb-phy = <&usb2_phy>;
795 phy-names = "usb2-phy";
799 ctrl-module = <&omap_control_usbotg>;
803 compatible = "ti,omap4-aes";
805 reg = <0x4b501000 0xa0>;
806 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
807 dmas = <&sdma 111>, <&sdma 110>;
808 dma-names = "tx", "rx";
812 compatible = "ti,omap4-des";
814 reg = <0x480a5000 0xa0>;
815 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
816 dmas = <&sdma 117>, <&sdma 116>;
817 dma-names = "tx", "rx";
820 abb_mpu: regulator-abb-mpu {
821 compatible = "ti,abb-v2";
822 regulator-name = "abb_mpu";
823 #address-cells = <0>;
825 ti,tranxdone-status-mask = <0x80>;
826 clocks = <&sys_clkin_ck>;
827 ti,settling-time = <50>;
828 ti,clock-cycles = <16>;
833 abb_iva: regulator-abb-iva {
834 compatible = "ti,abb-v2";
835 regulator-name = "abb_iva";
836 #address-cells = <0>;
838 ti,tranxdone-status-mask = <0x80000000>;
839 clocks = <&sys_clkin_ck>;
840 ti,settling-time = <50>;
841 ti,clock-cycles = <16>;
847 compatible = "ti,omap4-dss";
848 reg = <0x58000000 0x80>;
850 ti,hwmods = "dss_core";
851 clocks = <&dss_dss_clk>;
853 #address-cells = <1>;
858 compatible = "ti,omap4-dispc";
859 reg = <0x58001000 0x1000>;
860 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
861 ti,hwmods = "dss_dispc";
862 clocks = <&dss_dss_clk>;
866 rfbi: encoder@58002000 {
867 compatible = "ti,omap4-rfbi";
868 reg = <0x58002000 0x1000>;
870 ti,hwmods = "dss_rfbi";
871 clocks = <&dss_dss_clk>, <&dss_fck>;
872 clock-names = "fck", "ick";
875 venc: encoder@58003000 {
876 compatible = "ti,omap4-venc";
877 reg = <0x58003000 0x1000>;
879 ti,hwmods = "dss_venc";
880 clocks = <&dss_tv_clk>;
884 dsi1: encoder@58004000 {
885 compatible = "ti,omap4-dsi";
886 reg = <0x58004000 0x200>,
889 reg-names = "proto", "phy", "pll";
890 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
892 ti,hwmods = "dss_dsi1";
893 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
894 clock-names = "fck", "sys_clk";
897 dsi2: encoder@58005000 {
898 compatible = "ti,omap4-dsi";
899 reg = <0x58005000 0x200>,
902 reg-names = "proto", "phy", "pll";
903 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
905 ti,hwmods = "dss_dsi2";
906 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
907 clock-names = "fck", "sys_clk";
910 hdmi: encoder@58006000 {
911 compatible = "ti,omap4-hdmi";
912 reg = <0x58006000 0x200>,
916 reg-names = "wp", "pll", "phy", "core";
917 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
919 ti,hwmods = "dss_hdmi";
920 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
921 clock-names = "fck", "sys_clk";
927 /include/ "omap44xx-clocks.dtsi"