2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
13 #include "skeleton.dtsi"
16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
40 clocks = <&dpll_mpu_ck>;
43 clock-latency = <300000>; /* From omap-cpufreq driver */
46 compatible = "arm,cortex-a9";
48 next-level-cache = <&L2>;
53 gic: interrupt-controller@48241000 {
54 compatible = "arm,cortex-a9-gic";
56 #interrupt-cells = <3>;
57 reg = <0x48241000 0x1000>,
61 L2: l2-cache-controller@48242000 {
62 compatible = "arm,pl310-cache";
63 reg = <0x48242000 0x1000>;
68 local-timer@48240600 {
69 compatible = "arm,cortex-a9-twd-timer";
70 reg = <0x48240600 0x20>;
71 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
75 * The soc node represents the soc top level view. It is uses for IPs
76 * that are not memory mapped in the MPU view or for the MPU itself.
79 compatible = "ti,omap-infra";
81 compatible = "ti,omap4-mpu";
86 compatible = "ti,omap3-c64";
91 compatible = "ti,ivahd";
97 * XXX: Use a flat representation of the OMAP4 interconnect.
98 * The real OMAP interconnect network is quite complex.
99 * Since that will not bring real advantage to represent that in DT for
100 * the moment, just use a fake OCP bus entry to represent the whole bus
104 compatible = "ti,omap4-l3-noc", "simple-bus";
105 #address-cells = <1>;
108 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
109 reg = <0x44000000 0x1000>,
112 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
116 compatible = "ti,omap4-cm1";
117 reg = <0x4a004000 0x2000>;
120 #address-cells = <1>;
124 cm1_clockdomains: clockdomains {
129 compatible = "ti,omap4-prm";
130 reg = <0x4a306000 0x3000>;
133 #address-cells = <1>;
137 prm_clockdomains: clockdomains {
142 compatible = "ti,omap4-cm2";
143 reg = <0x4a008000 0x3000>;
146 #address-cells = <1>;
150 cm2_clockdomains: clockdomains {
154 scrm: scrm@4a30a000 {
155 compatible = "ti,omap4-scrm";
156 reg = <0x4a30a000 0x2000>;
158 scrm_clocks: clocks {
159 #address-cells = <1>;
163 scrm_clockdomains: clockdomains {
167 counter32k: counter@4a304000 {
168 compatible = "ti,omap-counter32k";
169 reg = <0x4a304000 0x20>;
170 ti,hwmods = "counter_32k";
173 omap4_pmx_core: pinmux@4a100040 {
174 compatible = "ti,omap4-padconf", "pinctrl-single";
175 reg = <0x4a100040 0x0196>;
176 #address-cells = <1>;
178 #interrupt-cells = <1>;
179 interrupt-controller;
180 pinctrl-single,register-width = <16>;
181 pinctrl-single,function-mask = <0x7fff>;
183 omap4_pmx_wkup: pinmux@4a31e040 {
184 compatible = "ti,omap4-padconf", "pinctrl-single";
185 reg = <0x4a31e040 0x0038>;
186 #address-cells = <1>;
188 #interrupt-cells = <1>;
189 interrupt-controller;
190 pinctrl-single,register-width = <16>;
191 pinctrl-single,function-mask = <0x7fff>;
194 sdma: dma-controller@4a056000 {
195 compatible = "ti,omap4430-sdma";
196 reg = <0x4a056000 0x1000>;
197 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
202 #dma-channels = <32>;
203 #dma-requests = <127>;
206 gpio1: gpio@4a310000 {
207 compatible = "ti,omap4-gpio";
208 reg = <0x4a310000 0x200>;
209 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
214 interrupt-controller;
215 #interrupt-cells = <2>;
218 gpio2: gpio@48055000 {
219 compatible = "ti,omap4-gpio";
220 reg = <0x48055000 0x200>;
221 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
225 interrupt-controller;
226 #interrupt-cells = <2>;
229 gpio3: gpio@48057000 {
230 compatible = "ti,omap4-gpio";
231 reg = <0x48057000 0x200>;
232 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
236 interrupt-controller;
237 #interrupt-cells = <2>;
240 gpio4: gpio@48059000 {
241 compatible = "ti,omap4-gpio";
242 reg = <0x48059000 0x200>;
243 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
247 interrupt-controller;
248 #interrupt-cells = <2>;
251 gpio5: gpio@4805b000 {
252 compatible = "ti,omap4-gpio";
253 reg = <0x4805b000 0x200>;
254 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
258 interrupt-controller;
259 #interrupt-cells = <2>;
262 gpio6: gpio@4805d000 {
263 compatible = "ti,omap4-gpio";
264 reg = <0x4805d000 0x200>;
265 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
269 interrupt-controller;
270 #interrupt-cells = <2>;
273 gpmc: gpmc@50000000 {
274 compatible = "ti,omap4430-gpmc";
275 reg = <0x50000000 0x1000>;
276 #address-cells = <2>;
278 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
280 gpmc,num-waitpins = <4>;
283 clocks = <&l3_div_ck>;
287 uart1: serial@4806a000 {
288 compatible = "ti,omap4-uart";
289 reg = <0x4806a000 0x100>;
290 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
292 clock-frequency = <48000000>;
295 uart2: serial@4806c000 {
296 compatible = "ti,omap4-uart";
297 reg = <0x4806c000 0x100>;
298 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
300 clock-frequency = <48000000>;
303 uart3: serial@48020000 {
304 compatible = "ti,omap4-uart";
305 reg = <0x48020000 0x100>;
306 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
308 clock-frequency = <48000000>;
311 uart4: serial@4806e000 {
312 compatible = "ti,omap4-uart";
313 reg = <0x4806e000 0x100>;
314 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
316 clock-frequency = <48000000>;
319 hwspinlock: spinlock@4a0f6000 {
320 compatible = "ti,omap4-hwspinlock";
321 reg = <0x4a0f6000 0x1000>;
322 ti,hwmods = "spinlock";
327 compatible = "ti,omap4-i2c";
328 reg = <0x48070000 0x100>;
329 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
330 #address-cells = <1>;
336 compatible = "ti,omap4-i2c";
337 reg = <0x48072000 0x100>;
338 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
339 #address-cells = <1>;
345 compatible = "ti,omap4-i2c";
346 reg = <0x48060000 0x100>;
347 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
354 compatible = "ti,omap4-i2c";
355 reg = <0x48350000 0x100>;
356 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
357 #address-cells = <1>;
362 mcspi1: spi@48098000 {
363 compatible = "ti,omap4-mcspi";
364 reg = <0x48098000 0x200>;
365 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
366 #address-cells = <1>;
368 ti,hwmods = "mcspi1";
378 dma-names = "tx0", "rx0", "tx1", "rx1",
379 "tx2", "rx2", "tx3", "rx3";
382 mcspi2: spi@4809a000 {
383 compatible = "ti,omap4-mcspi";
384 reg = <0x4809a000 0x200>;
385 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
386 #address-cells = <1>;
388 ti,hwmods = "mcspi2";
394 dma-names = "tx0", "rx0", "tx1", "rx1";
397 mcspi3: spi@480b8000 {
398 compatible = "ti,omap4-mcspi";
399 reg = <0x480b8000 0x200>;
400 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
401 #address-cells = <1>;
403 ti,hwmods = "mcspi3";
405 dmas = <&sdma 15>, <&sdma 16>;
406 dma-names = "tx0", "rx0";
409 mcspi4: spi@480ba000 {
410 compatible = "ti,omap4-mcspi";
411 reg = <0x480ba000 0x200>;
412 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
413 #address-cells = <1>;
415 ti,hwmods = "mcspi4";
417 dmas = <&sdma 70>, <&sdma 71>;
418 dma-names = "tx0", "rx0";
422 compatible = "ti,omap4-hsmmc";
423 reg = <0x4809c000 0x400>;
424 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
427 ti,needs-special-reset;
428 dmas = <&sdma 61>, <&sdma 62>;
429 dma-names = "tx", "rx";
433 compatible = "ti,omap4-hsmmc";
434 reg = <0x480b4000 0x400>;
435 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
437 ti,needs-special-reset;
438 dmas = <&sdma 47>, <&sdma 48>;
439 dma-names = "tx", "rx";
443 compatible = "ti,omap4-hsmmc";
444 reg = <0x480ad000 0x400>;
445 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
447 ti,needs-special-reset;
448 dmas = <&sdma 77>, <&sdma 78>;
449 dma-names = "tx", "rx";
453 compatible = "ti,omap4-hsmmc";
454 reg = <0x480d1000 0x400>;
455 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
457 ti,needs-special-reset;
458 dmas = <&sdma 57>, <&sdma 58>;
459 dma-names = "tx", "rx";
463 compatible = "ti,omap4-hsmmc";
464 reg = <0x480d5000 0x400>;
465 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
467 ti,needs-special-reset;
468 dmas = <&sdma 59>, <&sdma 60>;
469 dma-names = "tx", "rx";
472 mmu_dsp: mmu@4a066000 {
473 compatible = "ti,omap4-iommu";
474 reg = <0x4a066000 0x100>;
475 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
476 ti,hwmods = "mmu_dsp";
479 mmu_ipu: mmu@55082000 {
480 compatible = "ti,omap4-iommu";
481 reg = <0x55082000 0x100>;
482 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
483 ti,hwmods = "mmu_ipu";
484 ti,iommu-bus-err-back;
488 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
489 reg = <0x4a314000 0x80>;
490 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
491 ti,hwmods = "wd_timer2";
494 mcpdm: mcpdm@40132000 {
495 compatible = "ti,omap4-mcpdm";
496 reg = <0x40132000 0x7f>, /* MPU private access */
497 <0x49032000 0x7f>; /* L3 Interconnect */
498 reg-names = "mpu", "dma";
499 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
503 dma-names = "up_link", "dn_link";
507 dmic: dmic@4012e000 {
508 compatible = "ti,omap4-dmic";
509 reg = <0x4012e000 0x7f>, /* MPU private access */
510 <0x4902e000 0x7f>; /* L3 Interconnect */
511 reg-names = "mpu", "dma";
512 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
515 dma-names = "up_link";
519 mcbsp1: mcbsp@40122000 {
520 compatible = "ti,omap4-mcbsp";
521 reg = <0x40122000 0xff>, /* MPU private access */
522 <0x49022000 0xff>; /* L3 Interconnect */
523 reg-names = "mpu", "dma";
524 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
525 interrupt-names = "common";
526 ti,buffer-size = <128>;
527 ti,hwmods = "mcbsp1";
530 dma-names = "tx", "rx";
534 mcbsp2: mcbsp@40124000 {
535 compatible = "ti,omap4-mcbsp";
536 reg = <0x40124000 0xff>, /* MPU private access */
537 <0x49024000 0xff>; /* L3 Interconnect */
538 reg-names = "mpu", "dma";
539 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
540 interrupt-names = "common";
541 ti,buffer-size = <128>;
542 ti,hwmods = "mcbsp2";
545 dma-names = "tx", "rx";
549 mcbsp3: mcbsp@40126000 {
550 compatible = "ti,omap4-mcbsp";
551 reg = <0x40126000 0xff>, /* MPU private access */
552 <0x49026000 0xff>; /* L3 Interconnect */
553 reg-names = "mpu", "dma";
554 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
555 interrupt-names = "common";
556 ti,buffer-size = <128>;
557 ti,hwmods = "mcbsp3";
560 dma-names = "tx", "rx";
564 mcbsp4: mcbsp@48096000 {
565 compatible = "ti,omap4-mcbsp";
566 reg = <0x48096000 0xff>; /* L4 Interconnect */
568 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
569 interrupt-names = "common";
570 ti,buffer-size = <128>;
571 ti,hwmods = "mcbsp4";
574 dma-names = "tx", "rx";
578 keypad: keypad@4a31c000 {
579 compatible = "ti,omap4-keypad";
580 reg = <0x4a31c000 0x80>;
581 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
587 compatible = "ti,omap4-dmm";
588 reg = <0x4e000000 0x800>;
589 interrupts = <0 113 0x4>;
593 emif1: emif@4c000000 {
594 compatible = "ti,emif-4d";
595 reg = <0x4c000000 0x100>;
596 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
600 hw-caps-read-idle-ctrl;
601 hw-caps-ll-interface;
605 emif2: emif@4d000000 {
606 compatible = "ti,emif-4d";
607 reg = <0x4d000000 0x100>;
608 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
612 hw-caps-read-idle-ctrl;
613 hw-caps-ll-interface;
618 compatible = "ti,omap-ocp2scp";
619 reg = <0x4a0ad000 0x1f>;
620 #address-cells = <1>;
623 ti,hwmods = "ocp2scp_usb_phy";
624 usb2_phy: usb2phy@4a0ad080 {
625 compatible = "ti,omap-usb2";
626 reg = <0x4a0ad080 0x58>;
627 ctrl-module = <&omap_control_usb2phy>;
632 timer1: timer@4a318000 {
633 compatible = "ti,omap3430-timer";
634 reg = <0x4a318000 0x80>;
635 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
636 ti,hwmods = "timer1";
640 timer2: timer@48032000 {
641 compatible = "ti,omap3430-timer";
642 reg = <0x48032000 0x80>;
643 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
644 ti,hwmods = "timer2";
647 timer3: timer@48034000 {
648 compatible = "ti,omap4430-timer";
649 reg = <0x48034000 0x80>;
650 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
651 ti,hwmods = "timer3";
654 timer4: timer@48036000 {
655 compatible = "ti,omap4430-timer";
656 reg = <0x48036000 0x80>;
657 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
658 ti,hwmods = "timer4";
661 timer5: timer@40138000 {
662 compatible = "ti,omap4430-timer";
663 reg = <0x40138000 0x80>,
665 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
666 ti,hwmods = "timer5";
670 timer6: timer@4013a000 {
671 compatible = "ti,omap4430-timer";
672 reg = <0x4013a000 0x80>,
674 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
675 ti,hwmods = "timer6";
679 timer7: timer@4013c000 {
680 compatible = "ti,omap4430-timer";
681 reg = <0x4013c000 0x80>,
683 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
684 ti,hwmods = "timer7";
688 timer8: timer@4013e000 {
689 compatible = "ti,omap4430-timer";
690 reg = <0x4013e000 0x80>,
692 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
693 ti,hwmods = "timer8";
698 timer9: timer@4803e000 {
699 compatible = "ti,omap4430-timer";
700 reg = <0x4803e000 0x80>;
701 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
702 ti,hwmods = "timer9";
706 timer10: timer@48086000 {
707 compatible = "ti,omap3430-timer";
708 reg = <0x48086000 0x80>;
709 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
710 ti,hwmods = "timer10";
714 timer11: timer@48088000 {
715 compatible = "ti,omap4430-timer";
716 reg = <0x48088000 0x80>;
717 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
718 ti,hwmods = "timer11";
722 usbhstll: usbhstll@4a062000 {
723 compatible = "ti,usbhs-tll";
724 reg = <0x4a062000 0x1000>;
725 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
726 ti,hwmods = "usb_tll_hs";
729 usbhshost: usbhshost@4a064000 {
730 compatible = "ti,usbhs-host";
731 reg = <0x4a064000 0x800>;
732 ti,hwmods = "usb_host_hs";
733 #address-cells = <1>;
737 usbhsohci: ohci@4a064800 {
738 compatible = "ti,ohci-omap3";
739 reg = <0x4a064800 0x400>;
740 interrupt-parent = <&gic>;
741 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
744 usbhsehci: ehci@4a064c00 {
745 compatible = "ti,ehci-omap";
746 reg = <0x4a064c00 0x400>;
747 interrupt-parent = <&gic>;
748 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
752 omap_control_usb2phy: control-phy@4a002300 {
753 compatible = "ti,control-phy-usb2";
754 reg = <0x4a002300 0x4>;
758 omap_control_usbotg: control-phy@4a00233c {
759 compatible = "ti,control-phy-otghs";
760 reg = <0x4a00233c 0x4>;
761 reg-names = "otghs_control";
764 usb_otg_hs: usb_otg_hs@4a0ab000 {
765 compatible = "ti,omap4-musb";
766 reg = <0x4a0ab000 0x7ff>;
767 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
768 interrupt-names = "mc", "dma";
769 ti,hwmods = "usb_otg_hs";
770 usb-phy = <&usb2_phy>;
772 phy-names = "usb2-phy";
776 ctrl-module = <&omap_control_usbotg>;
780 compatible = "ti,omap4-aes";
782 reg = <0x4b501000 0xa0>;
783 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
784 dmas = <&sdma 111>, <&sdma 110>;
785 dma-names = "tx", "rx";
789 compatible = "ti,omap4-des";
791 reg = <0x480a5000 0xa0>;
792 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
793 dmas = <&sdma 117>, <&sdma 116>;
794 dma-names = "tx", "rx";
797 abb_mpu: regulator-abb-mpu {
798 compatible = "ti,abb-v2";
799 regulator-name = "abb_mpu";
800 #address-cells = <0>;
802 ti,tranxdone-status-mask = <0x80>;
803 clocks = <&sys_clkin_ck>;
804 ti,settling-time = <50>;
805 ti,clock-cycles = <16>;
810 abb_iva: regulator-abb-iva {
811 compatible = "ti,abb-v2";
812 regulator-name = "abb_iva";
813 #address-cells = <0>;
815 ti,tranxdone-status-mask = <0x80000000>;
816 clocks = <&sys_clkin_ck>;
817 ti,settling-time = <50>;
818 ti,clock-cycles = <16>;
825 /include/ "omap44xx-clocks.dtsi"