2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
14 #include "skeleton.dtsi"
20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
43 compatible = "arm,cortex-a15";
52 clocks = <&dpll_mpu_ck>;
55 clock-latency = <300000>; /* From omap-cpufreq driver */
58 cooling-min-level = <0>;
59 cooling-max-level = <2>;
60 #cooling-cells = <2>; /* min followed by max */
64 compatible = "arm,cortex-a15";
70 #include "omap4-cpu-thermal.dtsi"
71 #include "omap5-gpu-thermal.dtsi"
72 #include "omap5-core-thermal.dtsi"
76 compatible = "arm,armv7-timer";
77 /* PPI secure/nonsecure IRQ */
78 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
85 compatible = "arm,cortex-a15-pmu";
86 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
90 gic: interrupt-controller@48211000 {
91 compatible = "arm,cortex-a15-gic";
93 #interrupt-cells = <3>;
94 reg = <0x48211000 0x1000>,
101 * The soc node represents the soc top level view. It is used for IPs
102 * that are not memory mapped in the MPU view or for the MPU itself.
105 compatible = "ti,omap-infra";
107 compatible = "ti,omap4-mpu";
114 * XXX: Use a flat representation of the OMAP3 interconnect.
115 * The real OMAP interconnect network is quite complex.
116 * Since it will not bring real advantage to represent that in DT for
117 * the moment, just use a fake OCP bus entry to represent the whole bus
121 compatible = "ti,omap4-l3-noc", "simple-bus";
122 #address-cells = <1>;
125 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
126 reg = <0x44000000 0x2000>,
129 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
133 compatible = "ti,omap5-prm";
134 reg = <0x4ae06000 0x3000>;
135 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
138 #address-cells = <1>;
142 prm_clockdomains: clockdomains {
146 cm_core_aon: cm_core_aon@4a004000 {
147 compatible = "ti,omap5-cm-core-aon";
148 reg = <0x4a004000 0x2000>;
150 cm_core_aon_clocks: clocks {
151 #address-cells = <1>;
155 cm_core_aon_clockdomains: clockdomains {
159 scrm: scrm@4ae0a000 {
160 compatible = "ti,omap5-scrm";
161 reg = <0x4ae0a000 0x2000>;
163 scrm_clocks: clocks {
164 #address-cells = <1>;
168 scrm_clockdomains: clockdomains {
172 cm_core: cm_core@4a008000 {
173 compatible = "ti,omap5-cm-core";
174 reg = <0x4a008000 0x3000>;
176 cm_core_clocks: clocks {
177 #address-cells = <1>;
181 cm_core_clockdomains: clockdomains {
185 counter32k: counter@4ae04000 {
186 compatible = "ti,omap-counter32k";
187 reg = <0x4ae04000 0x40>;
188 ti,hwmods = "counter_32k";
191 omap5_pmx_core: pinmux@4a002840 {
192 compatible = "ti,omap5-padconf", "pinctrl-single";
193 reg = <0x4a002840 0x01b6>;
194 #address-cells = <1>;
196 #interrupt-cells = <1>;
197 interrupt-controller;
198 pinctrl-single,register-width = <16>;
199 pinctrl-single,function-mask = <0x7fff>;
201 omap5_pmx_wkup: pinmux@4ae0c840 {
202 compatible = "ti,omap5-padconf", "pinctrl-single";
203 reg = <0x4ae0c840 0x0038>;
204 #address-cells = <1>;
206 #interrupt-cells = <1>;
207 interrupt-controller;
208 pinctrl-single,register-width = <16>;
209 pinctrl-single,function-mask = <0x7fff>;
212 omap5_padconf_global: tisyscon@4a002da0 {
213 compatible = "syscon";
214 reg = <0x4A002da0 0xec>;
217 pbias_regulator: pbias_regulator {
218 compatible = "ti,pbias-omap";
220 syscon = <&omap5_padconf_global>;
221 pbias_mmc_reg: pbias_mmc_omap5 {
222 regulator-name = "pbias_mmc_omap5";
223 regulator-min-microvolt = <1800000>;
224 regulator-max-microvolt = <3000000>;
228 ocmcram: ocmcram@40300000 {
229 compatible = "mmio-sram";
230 reg = <0x40300000 0x20000>; /* 128k */
233 sdma: dma-controller@4a056000 {
234 compatible = "ti,omap4430-sdma";
235 reg = <0x4a056000 0x1000>;
236 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
242 dma-requests = <127>;
245 gpio1: gpio@4ae10000 {
246 compatible = "ti,omap4-gpio";
247 reg = <0x4ae10000 0x200>;
248 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
253 interrupt-controller;
254 #interrupt-cells = <2>;
257 gpio2: gpio@48055000 {
258 compatible = "ti,omap4-gpio";
259 reg = <0x48055000 0x200>;
260 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
268 gpio3: gpio@48057000 {
269 compatible = "ti,omap4-gpio";
270 reg = <0x48057000 0x200>;
271 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
279 gpio4: gpio@48059000 {
280 compatible = "ti,omap4-gpio";
281 reg = <0x48059000 0x200>;
282 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
286 interrupt-controller;
287 #interrupt-cells = <2>;
290 gpio5: gpio@4805b000 {
291 compatible = "ti,omap4-gpio";
292 reg = <0x4805b000 0x200>;
293 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
297 interrupt-controller;
298 #interrupt-cells = <2>;
301 gpio6: gpio@4805d000 {
302 compatible = "ti,omap4-gpio";
303 reg = <0x4805d000 0x200>;
304 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
308 interrupt-controller;
309 #interrupt-cells = <2>;
312 gpio7: gpio@48051000 {
313 compatible = "ti,omap4-gpio";
314 reg = <0x48051000 0x200>;
315 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
323 gpio8: gpio@48053000 {
324 compatible = "ti,omap4-gpio";
325 reg = <0x48053000 0x200>;
326 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
334 gpmc: gpmc@50000000 {
335 compatible = "ti,omap4430-gpmc";
336 reg = <0x50000000 0x1000>;
337 #address-cells = <2>;
339 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
341 gpmc,num-waitpins = <4>;
343 clocks = <&l3_iclk_div>;
348 compatible = "ti,omap4-i2c";
349 reg = <0x48070000 0x100>;
350 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
351 #address-cells = <1>;
357 compatible = "ti,omap4-i2c";
358 reg = <0x48072000 0x100>;
359 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
360 #address-cells = <1>;
366 compatible = "ti,omap4-i2c";
367 reg = <0x48060000 0x100>;
368 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
369 #address-cells = <1>;
375 compatible = "ti,omap4-i2c";
376 reg = <0x4807a000 0x100>;
377 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
384 compatible = "ti,omap4-i2c";
385 reg = <0x4807c000 0x100>;
386 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
387 #address-cells = <1>;
392 hwspinlock: spinlock@4a0f6000 {
393 compatible = "ti,omap4-hwspinlock";
394 reg = <0x4a0f6000 0x1000>;
395 ti,hwmods = "spinlock";
399 mcspi1: spi@48098000 {
400 compatible = "ti,omap4-mcspi";
401 reg = <0x48098000 0x200>;
402 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
403 #address-cells = <1>;
405 ti,hwmods = "mcspi1";
415 dma-names = "tx0", "rx0", "tx1", "rx1",
416 "tx2", "rx2", "tx3", "rx3";
419 mcspi2: spi@4809a000 {
420 compatible = "ti,omap4-mcspi";
421 reg = <0x4809a000 0x200>;
422 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
423 #address-cells = <1>;
425 ti,hwmods = "mcspi2";
431 dma-names = "tx0", "rx0", "tx1", "rx1";
434 mcspi3: spi@480b8000 {
435 compatible = "ti,omap4-mcspi";
436 reg = <0x480b8000 0x200>;
437 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
438 #address-cells = <1>;
440 ti,hwmods = "mcspi3";
442 dmas = <&sdma 15>, <&sdma 16>;
443 dma-names = "tx0", "rx0";
446 mcspi4: spi@480ba000 {
447 compatible = "ti,omap4-mcspi";
448 reg = <0x480ba000 0x200>;
449 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
450 #address-cells = <1>;
452 ti,hwmods = "mcspi4";
454 dmas = <&sdma 70>, <&sdma 71>;
455 dma-names = "tx0", "rx0";
458 uart1: serial@4806a000 {
459 compatible = "ti,omap4-uart";
460 reg = <0x4806a000 0x100>;
461 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
463 clock-frequency = <48000000>;
466 uart2: serial@4806c000 {
467 compatible = "ti,omap4-uart";
468 reg = <0x4806c000 0x100>;
469 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
471 clock-frequency = <48000000>;
474 uart3: serial@48020000 {
475 compatible = "ti,omap4-uart";
476 reg = <0x48020000 0x100>;
477 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
479 clock-frequency = <48000000>;
482 uart4: serial@4806e000 {
483 compatible = "ti,omap4-uart";
484 reg = <0x4806e000 0x100>;
485 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
487 clock-frequency = <48000000>;
490 uart5: serial@48066000 {
491 compatible = "ti,omap4-uart";
492 reg = <0x48066000 0x100>;
493 interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
495 clock-frequency = <48000000>;
498 uart6: serial@48068000 {
499 compatible = "ti,omap4-uart";
500 reg = <0x48068000 0x100>;
501 interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
503 clock-frequency = <48000000>;
507 compatible = "ti,omap4-hsmmc";
508 reg = <0x4809c000 0x400>;
509 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
512 ti,needs-special-reset;
513 dmas = <&sdma 61>, <&sdma 62>;
514 dma-names = "tx", "rx";
515 pbias-supply = <&pbias_mmc_reg>;
519 compatible = "ti,omap4-hsmmc";
520 reg = <0x480b4000 0x400>;
521 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
523 ti,needs-special-reset;
524 dmas = <&sdma 47>, <&sdma 48>;
525 dma-names = "tx", "rx";
529 compatible = "ti,omap4-hsmmc";
530 reg = <0x480ad000 0x400>;
531 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
533 ti,needs-special-reset;
534 dmas = <&sdma 77>, <&sdma 78>;
535 dma-names = "tx", "rx";
539 compatible = "ti,omap4-hsmmc";
540 reg = <0x480d1000 0x400>;
541 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
543 ti,needs-special-reset;
544 dmas = <&sdma 57>, <&sdma 58>;
545 dma-names = "tx", "rx";
549 compatible = "ti,omap4-hsmmc";
550 reg = <0x480d5000 0x400>;
551 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
553 ti,needs-special-reset;
554 dmas = <&sdma 59>, <&sdma 60>;
555 dma-names = "tx", "rx";
558 mmu_dsp: mmu@4a066000 {
559 compatible = "ti,omap4-iommu";
560 reg = <0x4a066000 0x100>;
561 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
562 ti,hwmods = "mmu_dsp";
565 mmu_ipu: mmu@55082000 {
566 compatible = "ti,omap4-iommu";
567 reg = <0x55082000 0x100>;
568 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
569 ti,hwmods = "mmu_ipu";
570 ti,iommu-bus-err-back;
573 keypad: keypad@4ae1c000 {
574 compatible = "ti,omap4-keypad";
575 reg = <0x4ae1c000 0x400>;
579 mcpdm: mcpdm@40132000 {
580 compatible = "ti,omap4-mcpdm";
581 reg = <0x40132000 0x7f>, /* MPU private access */
582 <0x49032000 0x7f>; /* L3 Interconnect */
583 reg-names = "mpu", "dma";
584 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
588 dma-names = "up_link", "dn_link";
592 dmic: dmic@4012e000 {
593 compatible = "ti,omap4-dmic";
594 reg = <0x4012e000 0x7f>, /* MPU private access */
595 <0x4902e000 0x7f>; /* L3 Interconnect */
596 reg-names = "mpu", "dma";
597 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
600 dma-names = "up_link";
604 mcbsp1: mcbsp@40122000 {
605 compatible = "ti,omap4-mcbsp";
606 reg = <0x40122000 0xff>, /* MPU private access */
607 <0x49022000 0xff>; /* L3 Interconnect */
608 reg-names = "mpu", "dma";
609 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
610 interrupt-names = "common";
611 ti,buffer-size = <128>;
612 ti,hwmods = "mcbsp1";
615 dma-names = "tx", "rx";
619 mcbsp2: mcbsp@40124000 {
620 compatible = "ti,omap4-mcbsp";
621 reg = <0x40124000 0xff>, /* MPU private access */
622 <0x49024000 0xff>; /* L3 Interconnect */
623 reg-names = "mpu", "dma";
624 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
625 interrupt-names = "common";
626 ti,buffer-size = <128>;
627 ti,hwmods = "mcbsp2";
630 dma-names = "tx", "rx";
634 mcbsp3: mcbsp@40126000 {
635 compatible = "ti,omap4-mcbsp";
636 reg = <0x40126000 0xff>, /* MPU private access */
637 <0x49026000 0xff>; /* L3 Interconnect */
638 reg-names = "mpu", "dma";
639 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
640 interrupt-names = "common";
641 ti,buffer-size = <128>;
642 ti,hwmods = "mcbsp3";
645 dma-names = "tx", "rx";
649 mailbox: mailbox@4a0f4000 {
650 compatible = "ti,omap4-mailbox";
651 reg = <0x4a0f4000 0x200>;
652 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
653 ti,hwmods = "mailbox";
655 ti,mbox-num-users = <3>;
656 ti,mbox-num-fifos = <8>;
658 ti,mbox-tx = <0 0 0>;
659 ti,mbox-rx = <1 0 0>;
662 ti,mbox-tx = <3 0 0>;
663 ti,mbox-rx = <2 0 0>;
667 timer1: timer@4ae18000 {
668 compatible = "ti,omap5430-timer";
669 reg = <0x4ae18000 0x80>;
670 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
671 ti,hwmods = "timer1";
675 timer2: timer@48032000 {
676 compatible = "ti,omap5430-timer";
677 reg = <0x48032000 0x80>;
678 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
679 ti,hwmods = "timer2";
682 timer3: timer@48034000 {
683 compatible = "ti,omap5430-timer";
684 reg = <0x48034000 0x80>;
685 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
686 ti,hwmods = "timer3";
689 timer4: timer@48036000 {
690 compatible = "ti,omap5430-timer";
691 reg = <0x48036000 0x80>;
692 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
693 ti,hwmods = "timer4";
696 timer5: timer@40138000 {
697 compatible = "ti,omap5430-timer";
698 reg = <0x40138000 0x80>,
700 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
701 ti,hwmods = "timer5";
706 timer6: timer@4013a000 {
707 compatible = "ti,omap5430-timer";
708 reg = <0x4013a000 0x80>,
710 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
711 ti,hwmods = "timer6";
716 timer7: timer@4013c000 {
717 compatible = "ti,omap5430-timer";
718 reg = <0x4013c000 0x80>,
720 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
721 ti,hwmods = "timer7";
725 timer8: timer@4013e000 {
726 compatible = "ti,omap5430-timer";
727 reg = <0x4013e000 0x80>,
729 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
730 ti,hwmods = "timer8";
735 timer9: timer@4803e000 {
736 compatible = "ti,omap5430-timer";
737 reg = <0x4803e000 0x80>;
738 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
739 ti,hwmods = "timer9";
743 timer10: timer@48086000 {
744 compatible = "ti,omap5430-timer";
745 reg = <0x48086000 0x80>;
746 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
747 ti,hwmods = "timer10";
751 timer11: timer@48088000 {
752 compatible = "ti,omap5430-timer";
753 reg = <0x48088000 0x80>;
754 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
755 ti,hwmods = "timer11";
760 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
761 reg = <0x4ae14000 0x80>;
762 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
763 ti,hwmods = "wd_timer2";
767 compatible = "ti,omap5-dmm";
768 reg = <0x4e000000 0x800>;
769 interrupts = <0 113 0x4>;
773 emif1: emif@4c000000 {
774 compatible = "ti,emif-4d5";
777 phy-type = <2>; /* DDR PHY type: Intelli PHY */
778 reg = <0x4c000000 0x400>;
779 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
780 hw-caps-read-idle-ctrl;
781 hw-caps-ll-interface;
785 emif2: emif@4d000000 {
786 compatible = "ti,emif-4d5";
789 phy-type = <2>; /* DDR PHY type: Intelli PHY */
790 reg = <0x4d000000 0x400>;
791 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
792 hw-caps-read-idle-ctrl;
793 hw-caps-ll-interface;
797 omap_control_usb2phy: control-phy@4a002300 {
798 compatible = "ti,control-phy-usb2";
799 reg = <0x4a002300 0x4>;
803 omap_control_usb3phy: control-phy@4a002370 {
804 compatible = "ti,control-phy-pipe3";
805 reg = <0x4a002370 0x4>;
809 usb3: omap_dwc3@4a020000 {
810 compatible = "ti,dwc3";
811 ti,hwmods = "usb_otg_ss";
812 reg = <0x4a020000 0x10000>;
813 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
814 #address-cells = <1>;
819 compatible = "snps,dwc3";
820 reg = <0x4a030000 0x10000>;
821 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
822 phys = <&usb2_phy>, <&usb3_phy>;
823 phy-names = "usb2-phy", "usb3-phy";
824 dr_mode = "peripheral";
830 compatible = "ti,omap-ocp2scp";
831 #address-cells = <1>;
833 reg = <0x4a080000 0x20>;
835 ti,hwmods = "ocp2scp1";
836 usb2_phy: usb2phy@4a084000 {
837 compatible = "ti,omap-usb2";
838 reg = <0x4a084000 0x7c>;
839 ctrl-module = <&omap_control_usb2phy>;
840 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
841 clock-names = "wkupclk", "refclk";
845 usb3_phy: usb3phy@4a084400 {
846 compatible = "ti,omap-usb3";
847 reg = <0x4a084400 0x80>,
850 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
851 ctrl-module = <&omap_control_usb3phy>;
852 clocks = <&usb_phy_cm_clk32k>,
854 <&usb_otg_ss_refclk960m>;
855 clock-names = "wkupclk",
862 usbhstll: usbhstll@4a062000 {
863 compatible = "ti,usbhs-tll";
864 reg = <0x4a062000 0x1000>;
865 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
866 ti,hwmods = "usb_tll_hs";
869 usbhshost: usbhshost@4a064000 {
870 compatible = "ti,usbhs-host";
871 reg = <0x4a064000 0x800>;
872 ti,hwmods = "usb_host_hs";
873 #address-cells = <1>;
876 clocks = <&l3init_60m_fclk>,
879 clock-names = "refclk_60m_int",
883 usbhsohci: ohci@4a064800 {
884 compatible = "ti,ohci-omap3";
885 reg = <0x4a064800 0x400>;
886 interrupt-parent = <&gic>;
887 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
890 usbhsehci: ehci@4a064c00 {
891 compatible = "ti,ehci-omap";
892 reg = <0x4a064c00 0x400>;
893 interrupt-parent = <&gic>;
894 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
898 bandgap: bandgap@4a0021e0 {
899 reg = <0x4a0021e0 0xc
903 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
904 compatible = "ti,omap5430-bandgap";
906 #thermal-sensor-cells = <1>;
909 omap_control_sata: control-phy@4a002374 {
910 compatible = "ti,control-phy-pipe3";
911 reg = <0x4a002374 0x4>;
913 clocks = <&sys_clkin>;
914 clock-names = "sysclk";
919 compatible = "ti,omap-ocp2scp";
920 #address-cells = <1>;
922 reg = <0x4a090000 0x20>;
924 ti,hwmods = "ocp2scp3";
925 sata_phy: phy@4a096000 {
926 compatible = "ti,phy-pipe3-sata";
927 reg = <0x4A096000 0x80>, /* phy_rx */
928 <0x4A096400 0x64>, /* phy_tx */
929 <0x4A096800 0x40>; /* pll_ctrl */
930 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
931 ctrl-module = <&omap_control_sata>;
932 clocks = <&sys_clkin>, <&sata_ref_clk>;
933 clock-names = "sysclk", "refclk";
938 sata: sata@4a141100 {
939 compatible = "snps,dwc-ahci";
940 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
941 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
943 phy-names = "sata-phy";
944 clocks = <&sata_ref_clk>;
949 compatible = "ti,omap5-dss";
950 reg = <0x58000000 0x80>;
952 ti,hwmods = "dss_core";
953 clocks = <&dss_dss_clk>;
955 #address-cells = <1>;
960 compatible = "ti,omap5-dispc";
961 reg = <0x58001000 0x1000>;
962 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
963 ti,hwmods = "dss_dispc";
964 clocks = <&dss_dss_clk>;
968 rfbi: encoder@58002000 {
969 compatible = "ti,omap5-rfbi";
970 reg = <0x58002000 0x100>;
972 ti,hwmods = "dss_rfbi";
973 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
974 clock-names = "fck", "ick";
977 dsi1: encoder@58004000 {
978 compatible = "ti,omap5-dsi";
979 reg = <0x58004000 0x200>,
982 reg-names = "proto", "phy", "pll";
983 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
985 ti,hwmods = "dss_dsi1";
986 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
987 clock-names = "fck", "sys_clk";
990 dsi2: encoder@58005000 {
991 compatible = "ti,omap5-dsi";
992 reg = <0x58009000 0x200>,
995 reg-names = "proto", "phy", "pll";
996 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
998 ti,hwmods = "dss_dsi2";
999 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1000 clock-names = "fck", "sys_clk";
1003 hdmi: encoder@58060000 {
1004 compatible = "ti,omap5-hdmi";
1005 reg = <0x58040000 0x200>,
1008 <0x58060000 0x19000>;
1009 reg-names = "wp", "pll", "phy", "core";
1010 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1011 status = "disabled";
1012 ti,hwmods = "dss_hdmi";
1013 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1014 clock-names = "fck", "sys_clk";
1016 dma-names = "audio_tx";
1020 abb_mpu: regulator-abb-mpu {
1021 compatible = "ti,abb-v2";
1022 regulator-name = "abb_mpu";
1023 #address-cells = <0>;
1025 clocks = <&sys_clkin>;
1026 ti,settling-time = <50>;
1027 ti,clock-cycles = <16>;
1029 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1030 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1031 reg-names = "base-address", "int-address",
1032 "efuse-address", "ldo-address";
1033 ti,tranxdone-status-mask = <0x80>;
1034 /* LDOVBBMPU_MUX_CTRL */
1035 ti,ldovbb-override-mask = <0x400>;
1036 /* LDOVBBMPU_VSET_OUT */
1037 ti,ldovbb-vset-mask = <0x1F>;
1040 * NOTE: only FBB mode used but actual vset will
1041 * determine final biasing
1044 /*uV ABB efuse rbb_m fbb_m vset_m*/
1045 1060000 0 0x0 0 0x02000000 0x01F00000
1046 1250000 0 0x4 0 0x02000000 0x01F00000
1050 abb_mm: regulator-abb-mm {
1051 compatible = "ti,abb-v2";
1052 regulator-name = "abb_mm";
1053 #address-cells = <0>;
1055 clocks = <&sys_clkin>;
1056 ti,settling-time = <50>;
1057 ti,clock-cycles = <16>;
1059 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1060 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1061 reg-names = "base-address", "int-address",
1062 "efuse-address", "ldo-address";
1063 ti,tranxdone-status-mask = <0x80000000>;
1064 /* LDOVBBMM_MUX_CTRL */
1065 ti,ldovbb-override-mask = <0x400>;
1066 /* LDOVBBMM_VSET_OUT */
1067 ti,ldovbb-vset-mask = <0x1F>;
1070 * NOTE: only FBB mode used but actual vset will
1071 * determine final biasing
1074 /*uV ABB efuse rbb_m fbb_m vset_m*/
1075 1025000 0 0x0 0 0x02000000 0x01F00000
1076 1120000 0 0x4 0 0x02000000 0x01F00000
1083 polling-delay = <500>; /* milliseconds */
1086 /include/ "omap54xx-clocks.dtsi"