2 * Device Tree Source for OMAP5 clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 pad_clks_src_ck: pad_clks_src_ck {
13 compatible = "fixed-clock";
14 clock-frequency = <12000000>;
17 pad_clks_ck: pad_clks_ck {
19 compatible = "ti,gate-clock";
20 clocks = <&pad_clks_src_ck>;
25 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
27 compatible = "fixed-clock";
28 clock-frequency = <32768>;
31 slimbus_src_clk: slimbus_src_clk {
33 compatible = "fixed-clock";
34 clock-frequency = <12000000>;
37 slimbus_clk: slimbus_clk {
39 compatible = "ti,gate-clock";
40 clocks = <&slimbus_src_clk>;
45 sys_32k_ck: sys_32k_ck {
47 compatible = "fixed-clock";
48 clock-frequency = <32768>;
51 virt_12000000_ck: virt_12000000_ck {
53 compatible = "fixed-clock";
54 clock-frequency = <12000000>;
57 virt_13000000_ck: virt_13000000_ck {
59 compatible = "fixed-clock";
60 clock-frequency = <13000000>;
63 virt_16800000_ck: virt_16800000_ck {
65 compatible = "fixed-clock";
66 clock-frequency = <16800000>;
69 virt_19200000_ck: virt_19200000_ck {
71 compatible = "fixed-clock";
72 clock-frequency = <19200000>;
75 virt_26000000_ck: virt_26000000_ck {
77 compatible = "fixed-clock";
78 clock-frequency = <26000000>;
81 virt_27000000_ck: virt_27000000_ck {
83 compatible = "fixed-clock";
84 clock-frequency = <27000000>;
87 virt_38400000_ck: virt_38400000_ck {
89 compatible = "fixed-clock";
90 clock-frequency = <38400000>;
93 xclk60mhsp1_ck: xclk60mhsp1_ck {
95 compatible = "fixed-clock";
96 clock-frequency = <60000000>;
99 xclk60mhsp2_ck: xclk60mhsp2_ck {
101 compatible = "fixed-clock";
102 clock-frequency = <60000000>;
105 dpll_abe_ck: dpll_abe_ck {
107 compatible = "ti,omap4-dpll-m4xen-clock";
108 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
109 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
112 dpll_abe_x2_ck: dpll_abe_x2_ck {
114 compatible = "ti,omap4-dpll-x2-clock";
115 clocks = <&dpll_abe_ck>;
118 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
120 compatible = "ti,divider-clock";
121 clocks = <&dpll_abe_x2_ck>;
124 ti,index-starts-at-one;
127 abe_24m_fclk: abe_24m_fclk {
129 compatible = "fixed-factor-clock";
130 clocks = <&dpll_abe_m2x2_ck>;
137 compatible = "ti,divider-clock";
138 clocks = <&dpll_abe_m2x2_ck>;
141 ti,index-power-of-two;
146 compatible = "ti,divider-clock";
147 clocks = <&aess_fclk>;
150 ti,dividers = <2>, <1>;
153 abe_lp_clk_div: abe_lp_clk_div {
155 compatible = "fixed-factor-clock";
156 clocks = <&dpll_abe_m2x2_ck>;
161 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
163 compatible = "ti,divider-clock";
164 clocks = <&dpll_abe_x2_ck>;
167 ti,index-starts-at-one;
170 dpll_core_ck: dpll_core_ck {
172 compatible = "ti,omap4-dpll-core-clock";
173 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
174 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
177 dpll_core_x2_ck: dpll_core_x2_ck {
179 compatible = "ti,omap4-dpll-x2-clock";
180 clocks = <&dpll_core_ck>;
183 dpll_core_h21x2_ck: dpll_core_h21x2_ck {
185 compatible = "ti,divider-clock";
186 clocks = <&dpll_core_x2_ck>;
189 ti,index-starts-at-one;
194 compatible = "fixed-factor-clock";
195 clocks = <&dpll_core_h21x2_ck>;
202 compatible = "fixed-factor-clock";
203 clocks = <&c2c_fclk>;
208 dpll_core_h11x2_ck: dpll_core_h11x2_ck {
210 compatible = "ti,divider-clock";
211 clocks = <&dpll_core_x2_ck>;
214 ti,index-starts-at-one;
217 dpll_core_h12x2_ck: dpll_core_h12x2_ck {
219 compatible = "ti,divider-clock";
220 clocks = <&dpll_core_x2_ck>;
223 ti,index-starts-at-one;
226 dpll_core_h13x2_ck: dpll_core_h13x2_ck {
228 compatible = "ti,divider-clock";
229 clocks = <&dpll_core_x2_ck>;
232 ti,index-starts-at-one;
235 dpll_core_h14x2_ck: dpll_core_h14x2_ck {
237 compatible = "ti,divider-clock";
238 clocks = <&dpll_core_x2_ck>;
241 ti,index-starts-at-one;
244 dpll_core_h22x2_ck: dpll_core_h22x2_ck {
246 compatible = "ti,divider-clock";
247 clocks = <&dpll_core_x2_ck>;
250 ti,index-starts-at-one;
253 dpll_core_h23x2_ck: dpll_core_h23x2_ck {
255 compatible = "ti,divider-clock";
256 clocks = <&dpll_core_x2_ck>;
259 ti,index-starts-at-one;
262 dpll_core_h24x2_ck: dpll_core_h24x2_ck {
264 compatible = "ti,divider-clock";
265 clocks = <&dpll_core_x2_ck>;
268 ti,index-starts-at-one;
271 dpll_core_m2_ck: dpll_core_m2_ck {
273 compatible = "ti,divider-clock";
274 clocks = <&dpll_core_ck>;
277 ti,index-starts-at-one;
280 dpll_core_m3x2_ck: dpll_core_m3x2_ck {
282 compatible = "ti,divider-clock";
283 clocks = <&dpll_core_x2_ck>;
286 ti,index-starts-at-one;
289 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
291 compatible = "fixed-factor-clock";
292 clocks = <&dpll_core_h12x2_ck>;
297 dpll_iva_ck: dpll_iva_ck {
299 compatible = "ti,omap4-dpll-clock";
300 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
301 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
304 dpll_iva_x2_ck: dpll_iva_x2_ck {
306 compatible = "ti,omap4-dpll-x2-clock";
307 clocks = <&dpll_iva_ck>;
310 dpll_iva_h11x2_ck: dpll_iva_h11x2_ck {
312 compatible = "ti,divider-clock";
313 clocks = <&dpll_iva_x2_ck>;
316 ti,index-starts-at-one;
319 dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
321 compatible = "ti,divider-clock";
322 clocks = <&dpll_iva_x2_ck>;
325 ti,index-starts-at-one;
328 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
330 compatible = "fixed-factor-clock";
331 clocks = <&dpll_core_h12x2_ck>;
336 dpll_mpu_ck: dpll_mpu_ck {
338 compatible = "ti,omap5-mpu-dpll-clock";
339 clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
340 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
343 dpll_mpu_m2_ck: dpll_mpu_m2_ck {
345 compatible = "ti,divider-clock";
346 clocks = <&dpll_mpu_ck>;
349 ti,index-starts-at-one;
352 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
354 compatible = "fixed-factor-clock";
355 clocks = <&dpll_abe_m3x2_ck>;
360 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
362 compatible = "fixed-factor-clock";
363 clocks = <&dpll_abe_m3x2_ck>;
368 l3_iclk_div: l3_iclk_div {
370 compatible = "ti,divider-clock";
374 clocks = <&dpll_core_h12x2_ck>;
375 ti,index-power-of-two;
378 gpu_l3_iclk: gpu_l3_iclk {
380 compatible = "fixed-factor-clock";
381 clocks = <&l3_iclk_div>;
386 l4_root_clk_div: l4_root_clk_div {
388 compatible = "ti,divider-clock";
392 clocks = <&l3_iclk_div>;
393 ti,index-power-of-two;
396 slimbus1_slimbus_clk: slimbus1_slimbus_clk {
398 compatible = "ti,gate-clock";
399 clocks = <&slimbus_clk>;
404 aess_fclk: aess_fclk {
406 compatible = "ti,divider-clock";
413 dmic_sync_mux_ck: dmic_sync_mux_ck {
415 compatible = "ti,mux-clock";
416 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
421 dmic_gfclk: dmic_gfclk {
423 compatible = "ti,mux-clock";
424 clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
429 mcasp_sync_mux_ck: mcasp_sync_mux_ck {
431 compatible = "ti,mux-clock";
432 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
437 mcasp_gfclk: mcasp_gfclk {
439 compatible = "ti,mux-clock";
440 clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
445 mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
447 compatible = "ti,mux-clock";
448 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
453 mcbsp1_gfclk: mcbsp1_gfclk {
455 compatible = "ti,mux-clock";
456 clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
461 mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
463 compatible = "ti,mux-clock";
464 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
469 mcbsp2_gfclk: mcbsp2_gfclk {
471 compatible = "ti,mux-clock";
472 clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
477 mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
479 compatible = "ti,mux-clock";
480 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
485 mcbsp3_gfclk: mcbsp3_gfclk {
487 compatible = "ti,mux-clock";
488 clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
493 timer5_gfclk_mux: timer5_gfclk_mux {
495 compatible = "ti,mux-clock";
496 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
501 timer6_gfclk_mux: timer6_gfclk_mux {
503 compatible = "ti,mux-clock";
504 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
509 timer7_gfclk_mux: timer7_gfclk_mux {
511 compatible = "ti,mux-clock";
512 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
517 timer8_gfclk_mux: timer8_gfclk_mux {
519 compatible = "ti,mux-clock";
520 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
527 compatible = "fixed-clock";
528 clock-frequency = <0>;
532 sys_clkin: sys_clkin {
534 compatible = "ti,mux-clock";
535 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
537 ti,index-starts-at-one;
540 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
542 compatible = "ti,mux-clock";
543 clocks = <&sys_clkin>, <&sys_32k_ck>;
547 abe_dpll_clk_mux: abe_dpll_clk_mux {
549 compatible = "ti,mux-clock";
550 clocks = <&sys_clkin>, <&sys_32k_ck>;
554 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
556 compatible = "fixed-factor-clock";
557 clocks = <&sys_clkin>;
562 dss_syc_gfclk_div: dss_syc_gfclk_div {
564 compatible = "fixed-factor-clock";
565 clocks = <&sys_clkin>;
570 wkupaon_iclk_mux: wkupaon_iclk_mux {
572 compatible = "ti,mux-clock";
573 clocks = <&sys_clkin>, <&abe_lp_clk_div>;
577 l3instr_ts_gclk_div: l3instr_ts_gclk_div {
579 compatible = "fixed-factor-clock";
580 clocks = <&wkupaon_iclk_mux>;
585 gpio1_dbclk: gpio1_dbclk {
587 compatible = "ti,gate-clock";
588 clocks = <&sys_32k_ck>;
593 timer1_gfclk_mux: timer1_gfclk_mux {
595 compatible = "ti,mux-clock";
596 clocks = <&sys_clkin>, <&sys_32k_ck>;
602 dpll_per_ck: dpll_per_ck {
604 compatible = "ti,omap4-dpll-clock";
605 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
606 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
609 dpll_per_x2_ck: dpll_per_x2_ck {
611 compatible = "ti,omap4-dpll-x2-clock";
612 clocks = <&dpll_per_ck>;
615 dpll_per_h11x2_ck: dpll_per_h11x2_ck {
617 compatible = "ti,divider-clock";
618 clocks = <&dpll_per_x2_ck>;
621 ti,index-starts-at-one;
624 dpll_per_h12x2_ck: dpll_per_h12x2_ck {
626 compatible = "ti,divider-clock";
627 clocks = <&dpll_per_x2_ck>;
630 ti,index-starts-at-one;
633 dpll_per_h14x2_ck: dpll_per_h14x2_ck {
635 compatible = "ti,divider-clock";
636 clocks = <&dpll_per_x2_ck>;
639 ti,index-starts-at-one;
642 dpll_per_m2_ck: dpll_per_m2_ck {
644 compatible = "ti,divider-clock";
645 clocks = <&dpll_per_ck>;
648 ti,index-starts-at-one;
651 dpll_per_m2x2_ck: dpll_per_m2x2_ck {
653 compatible = "ti,divider-clock";
654 clocks = <&dpll_per_x2_ck>;
657 ti,index-starts-at-one;
660 dpll_per_m3x2_ck: dpll_per_m3x2_ck {
662 compatible = "ti,divider-clock";
663 clocks = <&dpll_per_x2_ck>;
666 ti,index-starts-at-one;
669 dpll_unipro1_ck: dpll_unipro1_ck {
671 compatible = "ti,omap4-dpll-clock";
672 clocks = <&sys_clkin>, <&sys_clkin>;
673 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
676 dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
678 compatible = "fixed-factor-clock";
679 clocks = <&dpll_unipro1_ck>;
684 dpll_unipro1_m2_ck: dpll_unipro1_m2_ck {
686 compatible = "ti,divider-clock";
687 clocks = <&dpll_unipro1_ck>;
690 ti,index-starts-at-one;
693 dpll_unipro2_ck: dpll_unipro2_ck {
695 compatible = "ti,omap4-dpll-clock";
696 clocks = <&sys_clkin>, <&sys_clkin>;
697 reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
700 dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
702 compatible = "fixed-factor-clock";
703 clocks = <&dpll_unipro2_ck>;
708 dpll_unipro2_m2_ck: dpll_unipro2_m2_ck {
710 compatible = "ti,divider-clock";
711 clocks = <&dpll_unipro2_ck>;
714 ti,index-starts-at-one;
717 dpll_usb_ck: dpll_usb_ck {
719 compatible = "ti,omap4-dpll-j-type-clock";
720 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
721 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
724 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
726 compatible = "fixed-factor-clock";
727 clocks = <&dpll_usb_ck>;
732 dpll_usb_m2_ck: dpll_usb_m2_ck {
734 compatible = "ti,divider-clock";
735 clocks = <&dpll_usb_ck>;
738 ti,index-starts-at-one;
741 func_128m_clk: func_128m_clk {
743 compatible = "fixed-factor-clock";
744 clocks = <&dpll_per_h11x2_ck>;
749 func_12m_fclk: func_12m_fclk {
751 compatible = "fixed-factor-clock";
752 clocks = <&dpll_per_m2x2_ck>;
757 func_24m_clk: func_24m_clk {
759 compatible = "fixed-factor-clock";
760 clocks = <&dpll_per_m2_ck>;
765 func_48m_fclk: func_48m_fclk {
767 compatible = "fixed-factor-clock";
768 clocks = <&dpll_per_m2x2_ck>;
773 func_96m_fclk: func_96m_fclk {
775 compatible = "fixed-factor-clock";
776 clocks = <&dpll_per_m2x2_ck>;
781 l3init_60m_fclk: l3init_60m_fclk {
783 compatible = "ti,divider-clock";
784 clocks = <&dpll_usb_m2_ck>;
786 ti,dividers = <1>, <8>;
789 dss_32khz_clk: dss_32khz_clk {
791 compatible = "ti,gate-clock";
792 clocks = <&sys_32k_ck>;
797 dss_48mhz_clk: dss_48mhz_clk {
799 compatible = "ti,gate-clock";
800 clocks = <&func_48m_fclk>;
805 dss_dss_clk: dss_dss_clk {
807 compatible = "ti,gate-clock";
808 clocks = <&dpll_per_h12x2_ck>;
814 dss_sys_clk: dss_sys_clk {
816 compatible = "ti,gate-clock";
817 clocks = <&dss_syc_gfclk_div>;
822 gpio2_dbclk: gpio2_dbclk {
824 compatible = "ti,gate-clock";
825 clocks = <&sys_32k_ck>;
830 gpio3_dbclk: gpio3_dbclk {
832 compatible = "ti,gate-clock";
833 clocks = <&sys_32k_ck>;
838 gpio4_dbclk: gpio4_dbclk {
840 compatible = "ti,gate-clock";
841 clocks = <&sys_32k_ck>;
846 gpio5_dbclk: gpio5_dbclk {
848 compatible = "ti,gate-clock";
849 clocks = <&sys_32k_ck>;
854 gpio6_dbclk: gpio6_dbclk {
856 compatible = "ti,gate-clock";
857 clocks = <&sys_32k_ck>;
862 gpio7_dbclk: gpio7_dbclk {
864 compatible = "ti,gate-clock";
865 clocks = <&sys_32k_ck>;
870 gpio8_dbclk: gpio8_dbclk {
872 compatible = "ti,gate-clock";
873 clocks = <&sys_32k_ck>;
878 iss_ctrlclk: iss_ctrlclk {
880 compatible = "ti,gate-clock";
881 clocks = <&func_96m_fclk>;
886 lli_txphy_clk: lli_txphy_clk {
888 compatible = "ti,gate-clock";
889 clocks = <&dpll_unipro1_clkdcoldo>;
894 lli_txphy_ls_clk: lli_txphy_ls_clk {
896 compatible = "ti,gate-clock";
897 clocks = <&dpll_unipro1_m2_ck>;
902 mmc1_32khz_clk: mmc1_32khz_clk {
904 compatible = "ti,gate-clock";
905 clocks = <&sys_32k_ck>;
910 sata_ref_clk: sata_ref_clk {
912 compatible = "ti,gate-clock";
913 clocks = <&sys_clkin>;
918 usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
920 compatible = "ti,gate-clock";
921 clocks = <&dpll_usb_m2_ck>;
926 usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
928 compatible = "ti,gate-clock";
929 clocks = <&dpll_usb_m2_ck>;
934 usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk {
936 compatible = "ti,gate-clock";
937 clocks = <&dpll_usb_m2_ck>;
942 usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
944 compatible = "ti,gate-clock";
945 clocks = <&l3init_60m_fclk>;
950 usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
952 compatible = "ti,gate-clock";
953 clocks = <&l3init_60m_fclk>;
958 usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk {
960 compatible = "ti,gate-clock";
961 clocks = <&l3init_60m_fclk>;
966 utmi_p1_gfclk: utmi_p1_gfclk {
968 compatible = "ti,mux-clock";
969 clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
974 usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
976 compatible = "ti,gate-clock";
977 clocks = <&utmi_p1_gfclk>;
982 utmi_p2_gfclk: utmi_p2_gfclk {
984 compatible = "ti,mux-clock";
985 clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
990 usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
992 compatible = "ti,gate-clock";
993 clocks = <&utmi_p2_gfclk>;
998 usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
1000 compatible = "ti,gate-clock";
1001 clocks = <&l3init_60m_fclk>;
1002 ti,bit-shift = <10>;
1006 usb_otg_ss_refclk960m: usb_otg_ss_refclk960m {
1008 compatible = "ti,gate-clock";
1009 clocks = <&dpll_usb_clkdcoldo>;
1014 usb_phy_cm_clk32k: usb_phy_cm_clk32k {
1016 compatible = "ti,gate-clock";
1017 clocks = <&sys_32k_ck>;
1022 usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
1024 compatible = "ti,gate-clock";
1025 clocks = <&l3init_60m_fclk>;
1030 usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
1032 compatible = "ti,gate-clock";
1033 clocks = <&l3init_60m_fclk>;
1038 usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
1040 compatible = "ti,gate-clock";
1041 clocks = <&l3init_60m_fclk>;
1042 ti,bit-shift = <10>;
1046 fdif_fclk: fdif_fclk {
1048 compatible = "ti,divider-clock";
1049 clocks = <&dpll_per_h11x2_ck>;
1050 ti,bit-shift = <24>;
1055 gpu_core_gclk_mux: gpu_core_gclk_mux {
1057 compatible = "ti,mux-clock";
1058 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
1059 ti,bit-shift = <24>;
1063 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
1065 compatible = "ti,mux-clock";
1066 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
1067 ti,bit-shift = <25>;
1071 hsi_fclk: hsi_fclk {
1073 compatible = "ti,divider-clock";
1074 clocks = <&dpll_per_m2x2_ck>;
1075 ti,bit-shift = <24>;
1080 mmc1_fclk_mux: mmc1_fclk_mux {
1082 compatible = "ti,mux-clock";
1083 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1084 ti,bit-shift = <24>;
1088 mmc1_fclk: mmc1_fclk {
1090 compatible = "ti,divider-clock";
1091 clocks = <&mmc1_fclk_mux>;
1092 ti,bit-shift = <25>;
1097 mmc2_fclk_mux: mmc2_fclk_mux {
1099 compatible = "ti,mux-clock";
1100 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1101 ti,bit-shift = <24>;
1105 mmc2_fclk: mmc2_fclk {
1107 compatible = "ti,divider-clock";
1108 clocks = <&mmc2_fclk_mux>;
1109 ti,bit-shift = <25>;
1114 timer10_gfclk_mux: timer10_gfclk_mux {
1116 compatible = "ti,mux-clock";
1117 clocks = <&sys_clkin>, <&sys_32k_ck>;
1118 ti,bit-shift = <24>;
1122 timer11_gfclk_mux: timer11_gfclk_mux {
1124 compatible = "ti,mux-clock";
1125 clocks = <&sys_clkin>, <&sys_32k_ck>;
1126 ti,bit-shift = <24>;
1130 timer2_gfclk_mux: timer2_gfclk_mux {
1132 compatible = "ti,mux-clock";
1133 clocks = <&sys_clkin>, <&sys_32k_ck>;
1134 ti,bit-shift = <24>;
1138 timer3_gfclk_mux: timer3_gfclk_mux {
1140 compatible = "ti,mux-clock";
1141 clocks = <&sys_clkin>, <&sys_32k_ck>;
1142 ti,bit-shift = <24>;
1146 timer4_gfclk_mux: timer4_gfclk_mux {
1148 compatible = "ti,mux-clock";
1149 clocks = <&sys_clkin>, <&sys_32k_ck>;
1150 ti,bit-shift = <24>;
1154 timer9_gfclk_mux: timer9_gfclk_mux {
1156 compatible = "ti,mux-clock";
1157 clocks = <&sys_clkin>, <&sys_32k_ck>;
1158 ti,bit-shift = <24>;
1163 &cm_core_clockdomains {
1164 l3init_clkdm: l3init_clkdm {
1165 compatible = "ti,clockdomain";
1166 clocks = <&dpll_usb_ck>;
1171 auxclk0_src_gate_ck: auxclk0_src_gate_ck {
1173 compatible = "ti,composite-no-wait-gate-clock";
1174 clocks = <&dpll_core_m3x2_ck>;
1179 auxclk0_src_mux_ck: auxclk0_src_mux_ck {
1181 compatible = "ti,composite-mux-clock";
1182 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1187 auxclk0_src_ck: auxclk0_src_ck {
1189 compatible = "ti,composite-clock";
1190 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
1193 auxclk0_ck: auxclk0_ck {
1195 compatible = "ti,divider-clock";
1196 clocks = <&auxclk0_src_ck>;
1197 ti,bit-shift = <16>;
1202 auxclk1_src_gate_ck: auxclk1_src_gate_ck {
1204 compatible = "ti,composite-no-wait-gate-clock";
1205 clocks = <&dpll_core_m3x2_ck>;
1210 auxclk1_src_mux_ck: auxclk1_src_mux_ck {
1212 compatible = "ti,composite-mux-clock";
1213 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1218 auxclk1_src_ck: auxclk1_src_ck {
1220 compatible = "ti,composite-clock";
1221 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
1224 auxclk1_ck: auxclk1_ck {
1226 compatible = "ti,divider-clock";
1227 clocks = <&auxclk1_src_ck>;
1228 ti,bit-shift = <16>;
1233 auxclk2_src_gate_ck: auxclk2_src_gate_ck {
1235 compatible = "ti,composite-no-wait-gate-clock";
1236 clocks = <&dpll_core_m3x2_ck>;
1241 auxclk2_src_mux_ck: auxclk2_src_mux_ck {
1243 compatible = "ti,composite-mux-clock";
1244 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1249 auxclk2_src_ck: auxclk2_src_ck {
1251 compatible = "ti,composite-clock";
1252 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
1255 auxclk2_ck: auxclk2_ck {
1257 compatible = "ti,divider-clock";
1258 clocks = <&auxclk2_src_ck>;
1259 ti,bit-shift = <16>;
1264 auxclk3_src_gate_ck: auxclk3_src_gate_ck {
1266 compatible = "ti,composite-no-wait-gate-clock";
1267 clocks = <&dpll_core_m3x2_ck>;
1272 auxclk3_src_mux_ck: auxclk3_src_mux_ck {
1274 compatible = "ti,composite-mux-clock";
1275 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1280 auxclk3_src_ck: auxclk3_src_ck {
1282 compatible = "ti,composite-clock";
1283 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
1286 auxclk3_ck: auxclk3_ck {
1288 compatible = "ti,divider-clock";
1289 clocks = <&auxclk3_src_ck>;
1290 ti,bit-shift = <16>;
1295 auxclk4_src_gate_ck: auxclk4_src_gate_ck {
1297 compatible = "ti,composite-no-wait-gate-clock";
1298 clocks = <&dpll_core_m3x2_ck>;
1303 auxclk4_src_mux_ck: auxclk4_src_mux_ck {
1305 compatible = "ti,composite-mux-clock";
1306 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1311 auxclk4_src_ck: auxclk4_src_ck {
1313 compatible = "ti,composite-clock";
1314 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
1317 auxclk4_ck: auxclk4_ck {
1319 compatible = "ti,divider-clock";
1320 clocks = <&auxclk4_src_ck>;
1321 ti,bit-shift = <16>;
1326 auxclkreq0_ck: auxclkreq0_ck {
1328 compatible = "ti,mux-clock";
1329 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1334 auxclkreq1_ck: auxclkreq1_ck {
1336 compatible = "ti,mux-clock";
1337 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1342 auxclkreq2_ck: auxclkreq2_ck {
1344 compatible = "ti,mux-clock";
1345 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1350 auxclkreq3_ck: auxclkreq3_ck {
1352 compatible = "ti,mux-clock";
1353 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;