arch/arm/boot/dts/qcom-apq8084.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4
   5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
   6
   7 / {
   8         model = "Qualcomm APQ 8084";
   9         compatible = "qcom,apq8084";
  10         interrupt-parent = <&intc>;
  11
  12         cpus {
  13                 #address-cells = <1>;
  14                 #size-cells = <0>;
  15
  16                 cpu@0 {
  17                         device_type = "cpu";
  18                         compatible = "qcom,krait";
  19                         reg = <0>;
  20                         enable-method = "qcom,kpss-acc-v2";
  21                         next-level-cache = <&L2>;
  22                         qcom,acc = <&acc0>;
  23                 };
  24
  25                 cpu@1 {
  26                         device_type = "cpu";
  27                         compatible = "qcom,krait";
  28                         reg = <1>;
  29                         enable-method = "qcom,kpss-acc-v2";
  30                         next-level-cache = <&L2>;
  31                         qcom,acc = <&acc1>;
  32                 };
  33
  34                 cpu@2 {
  35                         device_type = "cpu";
  36                         compatible = "qcom,krait";
  37                         reg = <2>;
  38                         enable-method = "qcom,kpss-acc-v2";
  39                         next-level-cache = <&L2>;
  40                         qcom,acc = <&acc2>;
  41                 };
  42
  43                 cpu@3 {
  44                         device_type = "cpu";
  45                         compatible = "qcom,krait";
  46                         reg = <3>;
  47                         enable-method = "qcom,kpss-acc-v2";
  48                         next-level-cache = <&L2>;
  49                         qcom,acc = <&acc3>;
  50                 };
  51
  52                 L2: l2-cache {
  53                         compatible = "qcom,arch-cache";
  54                         cache-level = <2>;
  55                         qcom,saw = <&saw_l2>;
  56                 };
  57         };
  58
  59         cpu-pmu {
  60                 compatible = "qcom,krait-pmu";
  61                 interrupts = <1 7 0xf04>;
  62         };
  63
  64         timer {
  65                 compatible = "arm,armv7-timer";
  66                 interrupts = <1 2 0xf08>,
  67                              <1 3 0xf08>,
  68                              <1 4 0xf08>,
  69                              <1 1 0xf08>;
  70                 clock-frequency = <19200000>;
  71         };
  72
  73         soc: soc {
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 ranges;
  77                 compatible = "simple-bus";
  78
  79                 intc: interrupt-controller@f9000000 {
  80                         compatible = "qcom,msm-qgic2";
  81                         interrupt-controller;
  82                         #interrupt-cells = <3>;
  83                         reg = <0xf9000000 0x1000>,
  84                               <0xf9002000 0x1000>;
  85                 };
  86
  87                 timer@f9020000 {
  88                         #address-cells = <1>;
  89                         #size-cells = <1>;
  90                         ranges;
  91                         compatible = "arm,armv7-timer-mem";
  92                         reg = <0xf9020000 0x1000>;
  93                         clock-frequency = <19200000>;
  94
  95                         frame@f9021000 {
  96                                 frame-number = <0>;
  97                                 interrupts = <0 8 0x4>,
  98                                              <0 7 0x4>;
  99                                 reg = <0xf9021000 0x1000>,
 100                                       <0xf9022000 0x1000>;
 101                         };
 102
 103                         frame@f9023000 {
 104                                 frame-number = <1>;
 105                                 interrupts = <0 9 0x4>;
 106                                 reg = <0xf9023000 0x1000>;
 107                                 status = "disabled";
 108                         };
 109
 110                         frame@f9024000 {
 111                                 frame-number = <2>;
 112                                 interrupts = <0 10 0x4>;
 113                                 reg = <0xf9024000 0x1000>;
 114                                 status = "disabled";
 115                         };
 116
 117                         frame@f9025000 {
 118                                 frame-number = <3>;
 119                                 interrupts = <0 11 0x4>;
 120                                 reg = <0xf9025000 0x1000>;
 121                                 status = "disabled";
 122                         };
 123
 124                         frame@f9026000 {
 125                                 frame-number = <4>;
 126                                 interrupts = <0 12 0x4>;
 127                                 reg = <0xf9026000 0x1000>;
 128                                 status = "disabled";
 129                         };
 130
 131                         frame@f9027000 {
 132                                 frame-number = <5>;
 133                                 interrupts = <0 13 0x4>;
 134                                 reg = <0xf9027000 0x1000>;
 135                                 status = "disabled";
 136                         };
 137
 138                         frame@f9028000 {
 139                                 frame-number = <6>;
 140                                 interrupts = <0 14 0x4>;
 141                                 reg = <0xf9028000 0x1000>;
 142                                 status = "disabled";
 143                         };
 144                 };
 145
 146                 saw_l2: regulator@f9012000 {
 147                         compatible = "qcom,saw2";
 148                         reg = <0xf9012000 0x1000>;
 149                         regulator;
 150                 };
 151
 152                 acc0: clock-controller@f9088000 {
 153                         compatible = "qcom,kpss-acc-v2";
 154                         reg = <0xf9088000 0x1000>,
 155                               <0xf9008000 0x1000>;
 156                 };
 157
 158                 acc1: clock-controller@f9098000 {
 159                         compatible = "qcom,kpss-acc-v2";
 160                         reg = <0xf9098000 0x1000>,
 161                               <0xf9008000 0x1000>;
 162                 };
 163
 164                 acc2: clock-controller@f90a8000 {
 165                         compatible = "qcom,kpss-acc-v2";
 166                         reg = <0xf90a8000 0x1000>,
 167                               <0xf9008000 0x1000>;
 168                 };
 169
 170                 acc3: clock-controller@f90b8000 {
 171                         compatible = "qcom,kpss-acc-v2";
 172                         reg = <0xf90b8000 0x1000>,
 173                               <0xf9008000 0x1000>;
 174                 };
 175
 176                 restart@fc4ab000 {
 177                         compatible = "qcom,pshold";
 178                         reg = <0xfc4ab000 0x4>;
 179                 };
 180
 181                 gcc: clock-controller@fc400000 {
 182                         compatible = "qcom,gcc-apq8084";
 183                         #clock-cells = <1>;
 184                         #reset-cells = <1>;
 185                         reg = <0xfc400000 0x4000>;
 186                 };
 187
 188         };
 189 };