3 #include "skeleton.dtsi"
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm APQ 8084";
10 compatible = "qcom,apq8084";
11 interrupt-parent = <&intc>;
19 compatible = "qcom,krait";
21 enable-method = "qcom,kpss-acc-v2";
22 next-level-cache = <&L2>;
28 compatible = "qcom,krait";
30 enable-method = "qcom,kpss-acc-v2";
31 next-level-cache = <&L2>;
37 compatible = "qcom,krait";
39 enable-method = "qcom,kpss-acc-v2";
40 next-level-cache = <&L2>;
46 compatible = "qcom,krait";
48 enable-method = "qcom,kpss-acc-v2";
49 next-level-cache = <&L2>;
54 compatible = "qcom,arch-cache";
61 compatible = "qcom,krait-pmu";
62 interrupts = <1 7 0xf04>;
66 compatible = "arm,armv7-timer";
67 interrupts = <1 2 0xf08>,
71 clock-frequency = <19200000>;
78 compatible = "simple-bus";
80 intc: interrupt-controller@f9000000 {
81 compatible = "qcom,msm-qgic2";
83 #interrupt-cells = <3>;
84 reg = <0xf9000000 0x1000>,
92 compatible = "arm,armv7-timer-mem";
93 reg = <0xf9020000 0x1000>;
94 clock-frequency = <19200000>;
98 interrupts = <0 8 0x4>,
100 reg = <0xf9021000 0x1000>,
106 interrupts = <0 9 0x4>;
107 reg = <0xf9023000 0x1000>;
113 interrupts = <0 10 0x4>;
114 reg = <0xf9024000 0x1000>;
120 interrupts = <0 11 0x4>;
121 reg = <0xf9025000 0x1000>;
127 interrupts = <0 12 0x4>;
128 reg = <0xf9026000 0x1000>;
134 interrupts = <0 13 0x4>;
135 reg = <0xf9027000 0x1000>;
141 interrupts = <0 14 0x4>;
142 reg = <0xf9028000 0x1000>;
147 saw_l2: regulator@f9012000 {
148 compatible = "qcom,saw2";
149 reg = <0xf9012000 0x1000>;
153 acc0: clock-controller@f9088000 {
154 compatible = "qcom,kpss-acc-v2";
155 reg = <0xf9088000 0x1000>,
159 acc1: clock-controller@f9098000 {
160 compatible = "qcom,kpss-acc-v2";
161 reg = <0xf9098000 0x1000>,
165 acc2: clock-controller@f90a8000 {
166 compatible = "qcom,kpss-acc-v2";
167 reg = <0xf90a8000 0x1000>,
171 acc3: clock-controller@f90b8000 {
172 compatible = "qcom,kpss-acc-v2";
173 reg = <0xf90b8000 0x1000>,
178 compatible = "qcom,pshold";
179 reg = <0xfc4ab000 0x4>;
182 gcc: clock-controller@fc400000 {
183 compatible = "qcom,gcc-apq8084";
186 reg = <0xfc400000 0x4000>;
189 tlmm: pinctrl@fd510000 {
190 compatible = "qcom,apq8084-pinctrl";
191 reg = <0xfd510000 0x4000>;
194 interrupt-controller;
195 #interrupt-cells = <2>;
196 interrupts = <0 208 0>;
200 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
201 reg = <0xf995e000 0x1000>;
202 interrupts = <0 114 0x0>;
203 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
204 clock-names = "core", "iface";
209 compatible = "qcom,sdhci-msm-v4";
210 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
211 reg-names = "hc_mem", "core_mem";
212 interrupts = <0 123 0>, <0 138 0>;
213 interrupt-names = "hc_irq", "pwr_irq";
214 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
215 clock-names = "core", "iface";
220 compatible = "qcom,sdhci-msm-v4";
221 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
222 reg-names = "hc_mem", "core_mem";
223 interrupts = <0 125 0>, <0 221 0>;
224 interrupt-names = "hc_irq", "pwr_irq";
225 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
226 clock-names = "core", "iface";