3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/soc/qcom,gsbi.h>
8 model = "Qualcomm IPQ8064";
9 compatible = "qcom,ipq8064";
10 interrupt-parent = <&intc>;
17 compatible = "qcom,krait";
18 enable-method = "qcom,kpss-acc-v1";
21 next-level-cache = <&L2>;
27 compatible = "qcom,krait";
28 enable-method = "qcom,kpss-acc-v1";
31 next-level-cache = <&L2>;
43 compatible = "qcom,krait-pmu";
44 interrupts = <1 10 0x304>;
53 reg = <0x40000000 0x1000000>;
58 reg = <0x41000000 0x200000>;
67 compatible = "simple-bus";
69 qcom_pinmux: pinmux@800000 {
70 compatible = "qcom,ipq8064-pinctrl";
71 reg = <0x800000 0x4000>;
76 #interrupt-cells = <2>;
77 interrupts = <0 32 0x4>;
80 intc: interrupt-controller@2000000 {
81 compatible = "qcom,msm-qgic2";
83 #interrupt-cells = <3>;
84 reg = <0x02000000 0x1000>,
89 compatible = "qcom,kpss-timer", "qcom,msm-timer";
90 interrupts = <1 1 0x301>,
93 reg = <0x0200a000 0x100>;
94 clock-frequency = <25000000>,
96 cpu-offset = <0x80000>;
99 acc0: clock-controller@2088000 {
100 compatible = "qcom,kpss-acc-v1";
101 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
104 acc1: clock-controller@2098000 {
105 compatible = "qcom,kpss-acc-v1";
106 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
109 saw0: regulator@2089000 {
110 compatible = "qcom,saw2";
111 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
115 saw1: regulator@2099000 {
116 compatible = "qcom,saw2";
117 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
121 gsbi2: gsbi@12480000 {
122 compatible = "qcom,gsbi-v1.0.0";
123 reg = <0x12480000 0x100>;
124 clocks = <&gcc GSBI2_H_CLK>;
125 clock-names = "iface";
126 #address-cells = <1>;
132 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
133 reg = <0x12490000 0x1000>,
135 interrupts = <0 195 0x0>;
136 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
137 clock-names = "core", "iface";
142 compatible = "qcom,i2c-qup-v1.1.1";
143 reg = <0x124a0000 0x1000>;
144 interrupts = <0 196 0>;
146 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
147 clock-names = "core", "iface";
150 #address-cells = <1>;
156 gsbi4: gsbi@16300000 {
157 compatible = "qcom,gsbi-v1.0.0";
158 reg = <0x16300000 0x100>;
159 clocks = <&gcc GSBI4_H_CLK>;
160 clock-names = "iface";
161 #address-cells = <1>;
167 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
168 reg = <0x16340000 0x1000>,
170 interrupts = <0 152 0x0>;
171 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
172 clock-names = "core", "iface";
177 compatible = "qcom,i2c-qup-v1.1.1";
178 reg = <0x16380000 0x1000>;
179 interrupts = <0 153 0>;
181 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
182 clock-names = "core", "iface";
185 #address-cells = <1>;
190 gsbi5: gsbi@1a200000 {
191 compatible = "qcom,gsbi-v1.0.0";
192 reg = <0x1a200000 0x100>;
193 clocks = <&gcc GSBI5_H_CLK>;
194 clock-names = "iface";
195 #address-cells = <1>;
201 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
202 reg = <0x1a240000 0x1000>,
204 interrupts = <0 154 0x0>;
205 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
206 clock-names = "core", "iface";
211 compatible = "qcom,i2c-qup-v1.1.1";
212 reg = <0x1a280000 0x1000>;
213 interrupts = <0 155 0>;
215 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
216 clock-names = "core", "iface";
219 #address-cells = <1>;
224 compatible = "qcom,spi-qup-v1.1.1";
225 reg = <0x1a280000 0x1000>;
226 interrupts = <0 155 0>;
228 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
229 clock-names = "core", "iface";
232 #address-cells = <1>;
237 sata_phy: sata-phy@1b400000 {
238 compatible = "qcom,ipq806x-sata-phy";
239 reg = <0x1b400000 0x200>;
241 clocks = <&gcc SATA_PHY_CFG_CLK>;
249 compatible = "qcom,ipq806x-ahci", "generic-ahci";
250 reg = <0x29000000 0x180>;
252 interrupts = <0 209 0x0>;
254 clocks = <&gcc SFAB_SATA_S_H_CLK>,
257 <&gcc SATA_RXOOB_CLK>,
258 <&gcc SATA_PMALIVE_CLK>;
259 clock-names = "slave_face", "iface", "core",
262 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
263 assigned-clock-rates = <100000000>, <100000000>;
266 phy-names = "sata-phy";
271 compatible = "qcom,ssbi";
272 reg = <0x00500000 0x1000>;
273 qcom,controller-type = "pmic-arbiter";
276 gcc: clock-controller@900000 {
277 compatible = "qcom,gcc-ipq8064";
278 reg = <0x00900000 0x4000>;