Merge tag 'v4.3-rc1' into spi-fix-doc
[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / qcom-ipq8064.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
6 #include <dt-bindings/soc/qcom,gsbi.h>
7
8 / {
9         model = "Qualcomm IPQ8064";
10         compatible = "qcom,ipq8064";
11         interrupt-parent = <&intc>;
12
13         cpus {
14                 #address-cells = <1>;
15                 #size-cells = <0>;
16
17                 cpu@0 {
18                         compatible = "qcom,krait";
19                         enable-method = "qcom,kpss-acc-v1";
20                         device_type = "cpu";
21                         reg = <0>;
22                         next-level-cache = <&L2>;
23                         qcom,acc = <&acc0>;
24                         qcom,saw = <&saw0>;
25                 };
26
27                 cpu@1 {
28                         compatible = "qcom,krait";
29                         enable-method = "qcom,kpss-acc-v1";
30                         device_type = "cpu";
31                         reg = <1>;
32                         next-level-cache = <&L2>;
33                         qcom,acc = <&acc1>;
34                         qcom,saw = <&saw1>;
35                 };
36
37                 L2: l2-cache {
38                         compatible = "cache";
39                         cache-level = <2>;
40                 };
41         };
42
43         cpu-pmu {
44                 compatible = "qcom,krait-pmu";
45                 interrupts = <1 10 0x304>;
46         };
47
48         reserved-memory {
49                 #address-cells = <1>;
50                 #size-cells = <1>;
51                 ranges;
52
53                 nss@40000000 {
54                         reg = <0x40000000 0x1000000>;
55                         no-map;
56                 };
57
58                 smem@41000000 {
59                         reg = <0x41000000 0x200000>;
60                         no-map;
61                 };
62         };
63
64         clocks {
65                 sleep_clk: sleep_clk {
66                         compatible = "fixed-clock";
67                         clock-frequency = <32768>;
68                         #clock-cells = <0>;
69                 };
70         };
71
72         soc: soc {
73                 #address-cells = <1>;
74                 #size-cells = <1>;
75                 ranges;
76                 compatible = "simple-bus";
77
78                 lpass@28100000 {
79                         compatible = "qcom,lpass-cpu";
80                         status = "disabled";
81                         clocks = <&lcc AHBIX_CLK>,
82                                         <&lcc MI2S_OSR_CLK>,
83                                         <&lcc MI2S_BIT_CLK>;
84                         clock-names = "ahbix-clk",
85                                         "mi2s-osr-clk",
86                                         "mi2s-bit-clk";
87                         interrupts = <0 85 1>;
88                         interrupt-names = "lpass-irq-lpaif";
89                         reg = <0x28100000 0x10000>;
90                         reg-names = "lpass-lpaif";
91                 };
92
93                 qcom_pinmux: pinmux@800000 {
94                         compatible = "qcom,ipq8064-pinctrl";
95                         reg = <0x800000 0x4000>;
96
97                         gpio-controller;
98                         #gpio-cells = <2>;
99                         interrupt-controller;
100                         #interrupt-cells = <2>;
101                         interrupts = <0 16 0x4>;
102                 };
103
104                 intc: interrupt-controller@2000000 {
105                         compatible = "qcom,msm-qgic2";
106                         interrupt-controller;
107                         #interrupt-cells = <3>;
108                         reg = <0x02000000 0x1000>,
109                               <0x02002000 0x1000>;
110                 };
111
112                 timer@200a000 {
113                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
114                         interrupts = <1 1 0x301>,
115                                      <1 2 0x301>,
116                                      <1 3 0x301>,
117                                      <1 4 0x301>,
118                                      <1 5 0x301>;
119                         reg = <0x0200a000 0x100>;
120                         clock-frequency = <25000000>,
121                                           <32768>;
122                         clocks = <&sleep_clk>;
123                         clock-names = "sleep";
124                         cpu-offset = <0x80000>;
125                 };
126
127                 acc0: clock-controller@2088000 {
128                         compatible = "qcom,kpss-acc-v1";
129                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
130                 };
131
132                 acc1: clock-controller@2098000 {
133                         compatible = "qcom,kpss-acc-v1";
134                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
135                 };
136
137                 saw0: regulator@2089000 {
138                         compatible = "qcom,saw2";
139                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
140                         regulator;
141                 };
142
143                 saw1: regulator@2099000 {
144                         compatible = "qcom,saw2";
145                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
146                         regulator;
147                 };
148
149                 gsbi2: gsbi@12480000 {
150                         compatible = "qcom,gsbi-v1.0.0";
151                         cell-index = <2>;
152                         reg = <0x12480000 0x100>;
153                         clocks = <&gcc GSBI2_H_CLK>;
154                         clock-names = "iface";
155                         #address-cells = <1>;
156                         #size-cells = <1>;
157                         ranges;
158                         status = "disabled";
159
160                         syscon-tcsr = <&tcsr>;
161
162                         serial@12490000 {
163                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
164                                 reg = <0x12490000 0x1000>,
165                                       <0x12480000 0x1000>;
166                                 interrupts = <0 195 0x0>;
167                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
168                                 clock-names = "core", "iface";
169                                 status = "disabled";
170                         };
171
172                         i2c@124a0000 {
173                                 compatible = "qcom,i2c-qup-v1.1.1";
174                                 reg = <0x124a0000 0x1000>;
175                                 interrupts = <0 196 0>;
176
177                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
178                                 clock-names = "core", "iface";
179                                 status = "disabled";
180
181                                 #address-cells = <1>;
182                                 #size-cells = <0>;
183                         };
184
185                 };
186
187                 gsbi4: gsbi@16300000 {
188                         compatible = "qcom,gsbi-v1.0.0";
189                         cell-index = <4>;
190                         reg = <0x16300000 0x100>;
191                         clocks = <&gcc GSBI4_H_CLK>;
192                         clock-names = "iface";
193                         #address-cells = <1>;
194                         #size-cells = <1>;
195                         ranges;
196                         status = "disabled";
197
198                         syscon-tcsr = <&tcsr>;
199
200                         gsbi4_serial: serial@16340000 {
201                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
202                                 reg = <0x16340000 0x1000>,
203                                       <0x16300000 0x1000>;
204                                 interrupts = <0 152 0x0>;
205                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
206                                 clock-names = "core", "iface";
207                                 status = "disabled";
208                         };
209
210                         i2c@16380000 {
211                                 compatible = "qcom,i2c-qup-v1.1.1";
212                                 reg = <0x16380000 0x1000>;
213                                 interrupts = <0 153 0>;
214
215                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
216                                 clock-names = "core", "iface";
217                                 status = "disabled";
218
219                                 #address-cells = <1>;
220                                 #size-cells = <0>;
221                         };
222                 };
223
224                 gsbi5: gsbi@1a200000 {
225                         compatible = "qcom,gsbi-v1.0.0";
226                         cell-index = <5>;
227                         reg = <0x1a200000 0x100>;
228                         clocks = <&gcc GSBI5_H_CLK>;
229                         clock-names = "iface";
230                         #address-cells = <1>;
231                         #size-cells = <1>;
232                         ranges;
233                         status = "disabled";
234
235                         syscon-tcsr = <&tcsr>;
236
237                         serial@1a240000 {
238                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
239                                 reg = <0x1a240000 0x1000>,
240                                       <0x1a200000 0x1000>;
241                                 interrupts = <0 154 0x0>;
242                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
243                                 clock-names = "core", "iface";
244                                 status = "disabled";
245                         };
246
247                         i2c@1a280000 {
248                                 compatible = "qcom,i2c-qup-v1.1.1";
249                                 reg = <0x1a280000 0x1000>;
250                                 interrupts = <0 155 0>;
251
252                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
253                                 clock-names = "core", "iface";
254                                 status = "disabled";
255
256                                 #address-cells = <1>;
257                                 #size-cells = <0>;
258                         };
259
260                         spi@1a280000 {
261                                 compatible = "qcom,spi-qup-v1.1.1";
262                                 reg = <0x1a280000 0x1000>;
263                                 interrupts = <0 155 0>;
264
265                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
266                                 clock-names = "core", "iface";
267                                 status = "disabled";
268
269                                 #address-cells = <1>;
270                                 #size-cells = <0>;
271                         };
272                 };
273
274                 sata_phy: sata-phy@1b400000 {
275                         compatible = "qcom,ipq806x-sata-phy";
276                         reg = <0x1b400000 0x200>;
277
278                         clocks = <&gcc SATA_PHY_CFG_CLK>;
279                         clock-names = "cfg";
280
281                         #phy-cells = <0>;
282                         status = "disabled";
283                 };
284
285                 sata@29000000 {
286                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
287                         reg = <0x29000000 0x180>;
288
289                         interrupts = <0 209 0x0>;
290
291                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
292                                  <&gcc SATA_H_CLK>,
293                                  <&gcc SATA_A_CLK>,
294                                  <&gcc SATA_RXOOB_CLK>,
295                                  <&gcc SATA_PMALIVE_CLK>;
296                         clock-names = "slave_face", "iface", "core",
297                                         "rxoob", "pmalive";
298
299                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
300                         assigned-clock-rates = <100000000>, <100000000>;
301
302                         phys = <&sata_phy>;
303                         phy-names = "sata-phy";
304                         status = "disabled";
305                 };
306
307                 qcom,ssbi@500000 {
308                         compatible = "qcom,ssbi";
309                         reg = <0x00500000 0x1000>;
310                         qcom,controller-type = "pmic-arbiter";
311                 };
312
313                 gcc: clock-controller@900000 {
314                         compatible = "qcom,gcc-ipq8064";
315                         reg = <0x00900000 0x4000>;
316                         #clock-cells = <1>;
317                         #reset-cells = <1>;
318                 };
319
320                 tcsr: syscon@1a400000 {
321                         compatible = "qcom,tcsr-ipq8064", "syscon";
322                         reg = <0x1a400000 0x100>;
323                 };
324
325                 lcc: clock-controller@28000000 {
326                         compatible = "qcom,lcc-ipq8064";
327                         reg = <0x28000000 0x1000>;
328                         #clock-cells = <1>;
329                         #reset-cells = <1>;
330                 };
331
332         };
333 };