3 /include/ "skeleton.dtsi"
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
10 model = "Qualcomm MSM8660";
11 compatible = "qcom,msm8660";
12 interrupt-parent = <&intc>;
19 compatible = "qcom,scorpion";
20 enable-method = "qcom,gcc-msm8660";
23 next-level-cache = <&L2>;
27 compatible = "qcom,scorpion";
28 enable-method = "qcom,gcc-msm8660";
31 next-level-cache = <&L2>;
44 compatible = "simple-bus";
46 intc: interrupt-controller@2080000 {
47 compatible = "qcom,msm-8660-qgic";
49 #interrupt-cells = <3>;
50 reg = < 0x02080000 0x1000 >,
51 < 0x02081000 0x1000 >;
55 compatible = "qcom,scss-timer", "qcom,msm-timer";
56 interrupts = <1 0 0x301>,
59 reg = <0x02000000 0x100>;
60 clock-frequency = <27000000>,
62 cpu-offset = <0x40000>;
65 msmgpio: gpio@800000 {
66 compatible = "qcom,msm-gpio";
67 reg = <0x00800000 0x4000>;
71 interrupts = <0 16 0x4>;
73 #interrupt-cells = <2>;
76 gcc: clock-controller@900000 {
77 compatible = "qcom,gcc-msm8660";
80 reg = <0x900000 0x4000>;
83 gsbi12: gsbi@19c00000 {
84 compatible = "qcom,gsbi-v1.0.0";
86 reg = <0x19c00000 0x100>;
87 clocks = <&gcc GSBI12_H_CLK>;
88 clock-names = "iface";
93 syscon-tcsr = <&tcsr>;
96 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
97 reg = <0x19c40000 0x1000>,
99 interrupts = <0 195 0x0>;
100 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
101 clock-names = "core", "iface";
107 compatible = "qcom,ssbi";
108 reg = <0x500000 0x1000>;
109 qcom,controller-type = "pmic-arbiter";
112 compatible = "qcom,pm8058";
113 interrupt-parent = <&msmgpio>;
115 #interrupt-cells = <2>;
116 interrupt-controller;
117 #address-cells = <1>;
121 compatible = "qcom,pm8058-pwrkey";
123 interrupt-parent = <&pmicintc>;
124 interrupts = <50 1>, <51 1>;
130 compatible = "qcom,pm8058-keypad";
132 interrupt-parent = <&pmicintc>;
133 interrupts = <74 1>, <75 1>;
140 compatible = "qcom,pm8058-rtc";
141 interrupt-parent = <&pmicintc>;
148 compatible = "qcom,pm8058-vib";
154 /* Temporary fixed regulator */
155 vsdcc_fixed: vsdcc-regulator {
156 compatible = "regulator-fixed";
157 regulator-name = "SDCC Power";
158 regulator-min-microvolt = <2700000>;
159 regulator-max-microvolt = <2700000>;
164 compatible = "arm,amba-bus";
165 #address-cells = <1>;
168 sdcc1: sdcc@12400000 {
170 compatible = "arm,pl18x", "arm,primecell";
171 arm,primecell-periphid = <0x00051180>;
172 reg = <0x12400000 0x8000>;
173 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
174 interrupt-names = "cmd_irq";
175 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
176 clock-names = "mclk", "apb_pclk";
178 max-frequency = <48000000>;
182 vmmc-supply = <&vsdcc_fixed>;
185 sdcc3: sdcc@12180000 {
186 compatible = "arm,pl18x", "arm,primecell";
187 arm,primecell-periphid = <0x00051180>;
189 reg = <0x12180000 0x8000>;
190 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
191 interrupt-names = "cmd_irq";
192 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
193 clock-names = "mclk", "apb_pclk";
197 max-frequency = <48000000>;
199 vmmc-supply = <&vsdcc_fixed>;
203 tcsr: syscon@1a400000 {
204 compatible = "qcom,tcsr-msm8660", "syscon";
205 reg = <0x1a400000 0x100>;