3 /include/ "skeleton.dtsi"
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
10 model = "Qualcomm MSM8960";
11 compatible = "qcom,msm8960";
12 interrupt-parent = <&intc>;
17 interrupts = <1 14 0x304>;
20 compatible = "qcom,krait";
21 enable-method = "qcom,kpss-acc-v1";
24 next-level-cache = <&L2>;
30 compatible = "qcom,krait";
31 enable-method = "qcom,kpss-acc-v1";
34 next-level-cache = <&L2>;
46 compatible = "qcom,krait-pmu";
47 interrupts = <1 10 0x304>;
55 compatible = "simple-bus";
57 intc: interrupt-controller@2000000 {
58 compatible = "qcom,msm-qgic2";
60 #interrupt-cells = <3>;
61 reg = <0x02000000 0x1000>,
66 compatible = "qcom,kpss-timer", "qcom,msm-timer";
67 interrupts = <1 1 0x301>,
70 reg = <0x0200a000 0x100>;
71 clock-frequency = <27000000>,
73 cpu-offset = <0x80000>;
76 msmgpio: gpio@800000 {
77 compatible = "qcom,msm-gpio";
81 interrupts = <0 16 0x4>;
83 #interrupt-cells = <2>;
84 reg = <0x800000 0x4000>;
87 gcc: clock-controller@900000 {
88 compatible = "qcom,gcc-msm8960";
91 reg = <0x900000 0x4000>;
94 clock-controller@4000000 {
95 compatible = "qcom,mmcc-msm8960";
96 reg = <0x4000000 0x1000>;
101 acc0: clock-controller@2088000 {
102 compatible = "qcom,kpss-acc-v1";
103 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
106 acc1: clock-controller@2098000 {
107 compatible = "qcom,kpss-acc-v1";
108 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
111 saw0: regulator@2089000 {
112 compatible = "qcom,saw2";
113 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
117 saw1: regulator@2099000 {
118 compatible = "qcom,saw2";
119 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
123 gsbi5: gsbi@16400000 {
124 compatible = "qcom,gsbi-v1.0.0";
125 reg = <0x16400000 0x100>;
126 clocks = <&gcc GSBI5_H_CLK>;
127 clock-names = "iface";
128 #address-cells = <1>;
133 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
134 reg = <0x16440000 0x1000>,
136 interrupts = <0 154 0x0>;
137 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
138 clock-names = "core", "iface";
144 compatible = "qcom,ssbi";
145 reg = <0x500000 0x1000>;
146 qcom,controller-type = "pmic-arbiter";
149 compatible = "qcom,pm8921";
150 interrupt-parent = <&msmgpio>;
151 interrupts = <104 8>;
152 #interrupt-cells = <2>;
153 interrupt-controller;
154 #address-cells = <1>;
158 compatible = "qcom,pm8921-pwrkey";
160 interrupt-parent = <&pmicintc>;
161 interrupts = <50 1>, <51 1>;
167 compatible = "qcom,pm8921-keypad";
169 interrupt-parent = <&pmicintc>;
170 interrupts = <74 1>, <75 1>;
177 compatible = "qcom,pm8921-rtc";
178 interrupt-parent = <&pmicintc>;
187 compatible = "qcom,prng";
188 reg = <0x1a500000 0x200>;
189 clocks = <&gcc PRNG_CLK>;
190 clock-names = "core";
193 /* Temporary fixed regulator */
194 vsdcc_fixed: vsdcc-regulator {
195 compatible = "regulator-fixed";
196 regulator-name = "SDCC Power";
197 regulator-min-microvolt = <2700000>;
198 regulator-max-microvolt = <2700000>;
203 compatible = "arm,amba-bus";
204 #address-cells = <1>;
207 sdcc1: sdcc@12400000 {
209 compatible = "arm,pl18x", "arm,primecell";
210 arm,primecell-periphid = <0x00051180>;
211 reg = <0x12400000 0x8000>;
212 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
213 interrupt-names = "cmd_irq";
214 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
215 clock-names = "mclk", "apb_pclk";
217 max-frequency = <96000000>;
221 vmmc-supply = <&vsdcc_fixed>;
224 sdcc3: sdcc@12180000 {
225 compatible = "arm,pl18x", "arm,primecell";
226 arm,primecell-periphid = <0x00051180>;
228 reg = <0x12180000 0x8000>;
229 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
230 interrupt-names = "cmd_irq";
231 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
232 clock-names = "mclk", "apb_pclk";
236 max-frequency = <192000000>;
238 vmmc-supply = <&vsdcc_fixed>;