2 * Device Tree Source for the r7s72100 SoC
4 * Copyright (C) 2013-14 Renesas Solutions Corp.
5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r7s72100-clock.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "renesas,r7s72100";
17 interrupt-parent = <&gic>;
39 extal_clk: extal_clk {
41 compatible = "fixed-clock";
42 /* If clk present, value must be set by board */
43 clock-frequency = <0>;
44 clock-output-names = "extal";
47 usb_x1_clk: usb_x1_clk {
49 compatible = "fixed-clock";
50 /* If clk present, value must be set by board */
51 clock-frequency = <0>;
52 clock-output-names = "usb_x1";
55 /* Fixed factor clocks */
58 compatible = "fixed-factor-clock";
59 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
62 clock-output-names = "b";
66 compatible = "fixed-factor-clock";
67 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
70 clock-output-names = "p1";
74 compatible = "fixed-factor-clock";
75 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
78 clock-output-names = "p0";
81 /* Special CPG clocks */
82 cpg_clocks: cpg_clocks@fcfe0000 {
84 compatible = "renesas,r7s72100-cpg-clocks",
85 "renesas,rz-cpg-clocks";
86 reg = <0xfcfe0000 0x18>;
87 clocks = <&extal_clk>, <&usb_x1_clk>;
88 clock-output-names = "pll", "i", "g";
92 mstp3_clks: mstp3_clks@fcfe0420 {
94 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
97 clock-indices = <R7S72100_CLK_MTU2>;
98 clock-output-names = "mtu2";
101 mstp4_clks: mstp4_clks@fcfe0424 {
103 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
104 reg = <0xfcfe0424 4>;
105 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
106 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
108 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
109 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
111 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
114 mstp9_clks: mstp9_clks@fcfe0438 {
116 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
117 reg = <0xfcfe0438 4>;
118 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
120 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
122 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
125 mstp10_clks: mstp10_clks@fcfe043c {
127 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
128 reg = <0xfcfe043c 4>;
129 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
132 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
135 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
140 #address-cells = <1>;
145 compatible = "arm,cortex-a9";
147 clock-frequency = <400000000>;
151 scif0: serial@e8007000 {
152 compatible = "renesas,scif-r7s72100", "renesas,scif";
153 reg = <0xe8007000 64>;
154 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>,
155 <0 191 IRQ_TYPE_LEVEL_HIGH>,
156 <0 192 IRQ_TYPE_LEVEL_HIGH>,
157 <0 189 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
159 clock-names = "sci_ick";
163 scif1: serial@e8007800 {
164 compatible = "renesas,scif-r7s72100", "renesas,scif";
165 reg = <0xe8007800 64>;
166 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>,
167 <0 195 IRQ_TYPE_LEVEL_HIGH>,
168 <0 196 IRQ_TYPE_LEVEL_HIGH>,
169 <0 193 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
171 clock-names = "sci_ick";
175 scif2: serial@e8008000 {
176 compatible = "renesas,scif-r7s72100", "renesas,scif";
177 reg = <0xe8008000 64>;
178 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
179 <0 199 IRQ_TYPE_LEVEL_HIGH>,
180 <0 200 IRQ_TYPE_LEVEL_HIGH>,
181 <0 197 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
183 clock-names = "sci_ick";
187 scif3: serial@e8008800 {
188 compatible = "renesas,scif-r7s72100", "renesas,scif";
189 reg = <0xe8008800 64>;
190 interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>,
191 <0 203 IRQ_TYPE_LEVEL_HIGH>,
192 <0 204 IRQ_TYPE_LEVEL_HIGH>,
193 <0 201 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
195 clock-names = "sci_ick";
199 scif4: serial@e8009000 {
200 compatible = "renesas,scif-r7s72100", "renesas,scif";
201 reg = <0xe8009000 64>;
202 interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>,
203 <0 207 IRQ_TYPE_LEVEL_HIGH>,
204 <0 208 IRQ_TYPE_LEVEL_HIGH>,
205 <0 205 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
207 clock-names = "sci_ick";
211 scif5: serial@e8009800 {
212 compatible = "renesas,scif-r7s72100", "renesas,scif";
213 reg = <0xe8009800 64>;
214 interrupts = <0 210 IRQ_TYPE_LEVEL_HIGH>,
215 <0 211 IRQ_TYPE_LEVEL_HIGH>,
216 <0 212 IRQ_TYPE_LEVEL_HIGH>,
217 <0 209 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
219 clock-names = "sci_ick";
223 scif6: serial@e800a000 {
224 compatible = "renesas,scif-r7s72100", "renesas,scif";
225 reg = <0xe800a000 64>;
226 interrupts = <0 214 IRQ_TYPE_LEVEL_HIGH>,
227 <0 215 IRQ_TYPE_LEVEL_HIGH>,
228 <0 216 IRQ_TYPE_LEVEL_HIGH>,
229 <0 213 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
231 clock-names = "sci_ick";
235 scif7: serial@e800a800 {
236 compatible = "renesas,scif-r7s72100", "renesas,scif";
237 reg = <0xe800a800 64>;
238 interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>,
239 <0 219 IRQ_TYPE_LEVEL_HIGH>,
240 <0 220 IRQ_TYPE_LEVEL_HIGH>,
241 <0 217 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
243 clock-names = "sci_ick";
248 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
249 reg = <0xe800c800 0x24>;
250 interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>,
251 <0 239 IRQ_TYPE_LEVEL_HIGH>,
252 <0 240 IRQ_TYPE_LEVEL_HIGH>;
253 interrupt-names = "error", "rx", "tx";
254 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
256 #address-cells = <1>;
262 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
263 reg = <0xe800d000 0x24>;
264 interrupts = <0 241 IRQ_TYPE_LEVEL_HIGH>,
265 <0 242 IRQ_TYPE_LEVEL_HIGH>,
266 <0 243 IRQ_TYPE_LEVEL_HIGH>;
267 interrupt-names = "error", "rx", "tx";
268 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
270 #address-cells = <1>;
276 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
277 reg = <0xe800d800 0x24>;
278 interrupts = <0 244 IRQ_TYPE_LEVEL_HIGH>,
279 <0 245 IRQ_TYPE_LEVEL_HIGH>,
280 <0 246 IRQ_TYPE_LEVEL_HIGH>;
281 interrupt-names = "error", "rx", "tx";
282 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
284 #address-cells = <1>;
290 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
291 reg = <0xe800e000 0x24>;
292 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>,
293 <0 248 IRQ_TYPE_LEVEL_HIGH>,
294 <0 249 IRQ_TYPE_LEVEL_HIGH>;
295 interrupt-names = "error", "rx", "tx";
296 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
298 #address-cells = <1>;
304 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
305 reg = <0xe800e800 0x24>;
306 interrupts = <0 250 IRQ_TYPE_LEVEL_HIGH>,
307 <0 251 IRQ_TYPE_LEVEL_HIGH>,
308 <0 252 IRQ_TYPE_LEVEL_HIGH>;
309 interrupt-names = "error", "rx", "tx";
310 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
312 #address-cells = <1>;
317 gic: interrupt-controller@e8201000 {
318 compatible = "arm,cortex-a9-gic";
319 #interrupt-cells = <3>;
320 #address-cells = <0>;
321 interrupt-controller;
322 reg = <0xe8201000 0x1000>,
327 #address-cells = <1>;
329 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
330 reg = <0xfcfee000 0x44>;
331 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
332 <0 158 IRQ_TYPE_EDGE_RISING>,
333 <0 159 IRQ_TYPE_EDGE_RISING>,
334 <0 160 IRQ_TYPE_LEVEL_HIGH>,
335 <0 161 IRQ_TYPE_LEVEL_HIGH>,
336 <0 162 IRQ_TYPE_LEVEL_HIGH>,
337 <0 163 IRQ_TYPE_LEVEL_HIGH>,
338 <0 164 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
340 clock-frequency = <100000>;
345 #address-cells = <1>;
347 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
348 reg = <0xfcfee400 0x44>;
349 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
350 <0 166 IRQ_TYPE_EDGE_RISING>,
351 <0 167 IRQ_TYPE_EDGE_RISING>,
352 <0 168 IRQ_TYPE_LEVEL_HIGH>,
353 <0 169 IRQ_TYPE_LEVEL_HIGH>,
354 <0 170 IRQ_TYPE_LEVEL_HIGH>,
355 <0 171 IRQ_TYPE_LEVEL_HIGH>,
356 <0 172 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
358 clock-frequency = <100000>;
363 #address-cells = <1>;
365 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
366 reg = <0xfcfee800 0x44>;
367 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
368 <0 174 IRQ_TYPE_EDGE_RISING>,
369 <0 175 IRQ_TYPE_EDGE_RISING>,
370 <0 176 IRQ_TYPE_LEVEL_HIGH>,
371 <0 177 IRQ_TYPE_LEVEL_HIGH>,
372 <0 178 IRQ_TYPE_LEVEL_HIGH>,
373 <0 179 IRQ_TYPE_LEVEL_HIGH>,
374 <0 180 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
376 clock-frequency = <100000>;
381 #address-cells = <1>;
383 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
384 reg = <0xfcfeec00 0x44>;
385 interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
386 <0 182 IRQ_TYPE_EDGE_RISING>,
387 <0 183 IRQ_TYPE_EDGE_RISING>,
388 <0 184 IRQ_TYPE_LEVEL_HIGH>,
389 <0 185 IRQ_TYPE_LEVEL_HIGH>,
390 <0 186 IRQ_TYPE_LEVEL_HIGH>,
391 <0 187 IRQ_TYPE_LEVEL_HIGH>,
392 <0 188 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
394 clock-frequency = <100000>;
398 mtu2: timer@fcff0000 {
399 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
400 reg = <0xfcff0000 0x400>;
401 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "tgi0a";
403 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;