2 * Device Tree Source for the r8a7740 SoC
4 * Copyright (C) 2012 Renesas Solutions Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 /include/ "skeleton.dtsi"
13 #include <dt-bindings/clock/r8a7740-clock.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r8a7740";
18 interrupt-parent = <&gic>;
24 compatible = "arm,cortex-a9";
27 clock-frequency = <800000000>;
31 gic: interrupt-controller@c2800000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
35 reg = <0xc2800000 0x1000>,
40 compatible = "arm,cortex-a9-pmu";
41 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
44 cmt1: timer@e6138000 {
45 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
46 reg = <0xe6138000 0x170>;
47 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
51 renesas,channels-mask = <0x3f>;
56 /* irqpin0: IRQ0 - IRQ7 */
57 irqpin0: irqpin@e6900000 {
58 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
59 #interrupt-cells = <2>;
66 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
67 0 149 IRQ_TYPE_LEVEL_HIGH
68 0 149 IRQ_TYPE_LEVEL_HIGH
69 0 149 IRQ_TYPE_LEVEL_HIGH
70 0 149 IRQ_TYPE_LEVEL_HIGH
71 0 149 IRQ_TYPE_LEVEL_HIGH
72 0 149 IRQ_TYPE_LEVEL_HIGH
73 0 149 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
77 /* irqpin1: IRQ8 - IRQ15 */
78 irqpin1: irqpin@e6900004 {
79 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
80 #interrupt-cells = <2>;
87 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
88 0 149 IRQ_TYPE_LEVEL_HIGH
89 0 149 IRQ_TYPE_LEVEL_HIGH
90 0 149 IRQ_TYPE_LEVEL_HIGH
91 0 149 IRQ_TYPE_LEVEL_HIGH
92 0 149 IRQ_TYPE_LEVEL_HIGH
93 0 149 IRQ_TYPE_LEVEL_HIGH
94 0 149 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
98 /* irqpin2: IRQ16 - IRQ23 */
99 irqpin2: irqpin@e6900008 {
100 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
101 #interrupt-cells = <2>;
102 interrupt-controller;
103 reg = <0xe6900008 4>,
108 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
109 0 149 IRQ_TYPE_LEVEL_HIGH
110 0 149 IRQ_TYPE_LEVEL_HIGH
111 0 149 IRQ_TYPE_LEVEL_HIGH
112 0 149 IRQ_TYPE_LEVEL_HIGH
113 0 149 IRQ_TYPE_LEVEL_HIGH
114 0 149 IRQ_TYPE_LEVEL_HIGH
115 0 149 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
119 /* irqpin3: IRQ24 - IRQ31 */
120 irqpin3: irqpin@e690000c {
121 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
122 #interrupt-cells = <2>;
123 interrupt-controller;
124 reg = <0xe690000c 4>,
129 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
130 0 149 IRQ_TYPE_LEVEL_HIGH
131 0 149 IRQ_TYPE_LEVEL_HIGH
132 0 149 IRQ_TYPE_LEVEL_HIGH
133 0 149 IRQ_TYPE_LEVEL_HIGH
134 0 149 IRQ_TYPE_LEVEL_HIGH
135 0 149 IRQ_TYPE_LEVEL_HIGH
136 0 149 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
140 ether: ethernet@e9a00000 {
141 compatible = "renesas,gether-r8a7740";
142 reg = <0xe9a00000 0x800>,
144 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
147 #address-cells = <1>;
153 #address-cells = <1>;
155 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
156 reg = <0xfff20000 0x425>;
157 interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH
158 0 202 IRQ_TYPE_LEVEL_HIGH
159 0 203 IRQ_TYPE_LEVEL_HIGH
160 0 204 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
166 #address-cells = <1>;
168 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
169 reg = <0xe6c20000 0x425>;
170 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH
171 0 71 IRQ_TYPE_LEVEL_HIGH
172 0 72 IRQ_TYPE_LEVEL_HIGH
173 0 73 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
178 scifa0: serial@e6c40000 {
179 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
180 reg = <0xe6c40000 0x100>;
181 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
183 clock-names = "sci_ick";
187 scifa1: serial@e6c50000 {
188 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
189 reg = <0xe6c50000 0x100>;
190 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
192 clock-names = "sci_ick";
196 scifa2: serial@e6c60000 {
197 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
198 reg = <0xe6c60000 0x100>;
199 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
201 clock-names = "sci_ick";
205 scifa3: serial@e6c70000 {
206 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
207 reg = <0xe6c70000 0x100>;
208 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
210 clock-names = "sci_ick";
214 scifa4: serial@e6c80000 {
215 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
216 reg = <0xe6c80000 0x100>;
217 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
219 clock-names = "sci_ick";
223 scifa5: serial@e6cb0000 {
224 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
225 reg = <0xe6cb0000 0x100>;
226 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
228 clock-names = "sci_ick";
232 scifa6: serial@e6cc0000 {
233 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
234 reg = <0xe6cc0000 0x100>;
235 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
237 clock-names = "sci_ick";
241 scifa7: serial@e6cd0000 {
242 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
243 reg = <0xe6cd0000 0x100>;
244 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
246 clock-names = "sci_ick";
250 scifb8: serial@e6c30000 {
251 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
252 reg = <0xe6c30000 0x100>;
253 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
255 clock-names = "sci_ick";
260 compatible = "renesas,pfc-r8a7740";
261 reg = <0xe6050000 0x8000>,
265 interrupts-extended =
266 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
267 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
268 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
269 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
270 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
271 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
272 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
273 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
277 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
278 reg = <0xe6600000 0x100>;
279 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
284 mmcif0: mmc@e6bd0000 {
285 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
286 reg = <0xe6bd0000 0x100>;
287 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
288 0 57 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
294 compatible = "renesas,sdhi-r8a7740";
295 reg = <0xe6850000 0x100>;
296 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
297 0 118 IRQ_TYPE_LEVEL_HIGH
298 0 119 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
306 compatible = "renesas,sdhi-r8a7740";
307 reg = <0xe6860000 0x100>;
308 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
309 0 122 IRQ_TYPE_LEVEL_HIGH
310 0 123 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
318 compatible = "renesas,sdhi-r8a7740";
319 reg = <0xe6870000 0x100>;
320 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
321 0 126 IRQ_TYPE_LEVEL_HIGH
322 0 127 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
329 sh_fsi2: sound@fe1f0000 {
330 #sound-dai-cells = <1>;
331 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
332 reg = <0xfe1f0000 0x400>;
333 interrupts = <0 9 0x4>;
334 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
338 tmu0: timer@fff80000 {
339 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
340 reg = <0xfff80000 0x2c>;
341 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
342 <0 199 IRQ_TYPE_LEVEL_HIGH>,
343 <0 200 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
347 #renesas,channels = <3>;
352 tmu1: timer@fff90000 {
353 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
354 reg = <0xfff90000 0x2c>;
355 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>,
356 <0 171 IRQ_TYPE_LEVEL_HIGH>,
357 <0 172 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
361 #renesas,channels = <3>;
367 #address-cells = <1>;
371 /* External root clock */
372 extalr_clk: extalr_clk {
373 compatible = "fixed-clock";
375 clock-frequency = <32768>;
376 clock-output-names = "extalr";
378 extal1_clk: extal1_clk {
379 compatible = "fixed-clock";
381 clock-frequency = <0>;
382 clock-output-names = "extal1";
384 extal2_clk: extal2_clk {
385 compatible = "fixed-clock";
387 clock-frequency = <0>;
388 clock-output-names = "extal2";
391 compatible = "fixed-clock";
393 clock-frequency = <27000000>;
394 clock-output-names = "dv";
396 fsiack_clk: fsiack_clk {
397 compatible = "fixed-clock";
399 clock-frequency = <0>;
400 clock-output-names = "fsiack";
402 fsibck_clk: fsibck_clk {
403 compatible = "fixed-clock";
405 clock-frequency = <0>;
406 clock-output-names = "fsibck";
409 /* Special CPG clocks */
410 cpg_clocks: cpg_clocks@e6150000 {
411 compatible = "renesas,r8a7740-cpg-clocks";
412 reg = <0xe6150000 0x10000>;
413 clocks = <&extal1_clk>, <&extalr_clk>;
415 clock-output-names = "system", "pllc0", "pllc1",
418 "i", "zg", "b", "m1", "hp",
419 "hpp", "usbp", "s", "zb", "m3",
423 /* Variable factor clocks (DIV6) */
424 sub_clk: sub_clk@e6150080 {
425 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
426 reg = <0xe6150080 4>;
427 clocks = <&pllc1_div2_clk>;
429 clock-output-names = "sub";
432 /* Fixed factor clocks */
433 pllc1_div2_clk: pllc1_div2_clk {
434 compatible = "fixed-factor-clock";
435 clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
439 clock-output-names = "pllc1_div2";
441 extal1_div2_clk: extal1_div2_clk {
442 compatible = "fixed-factor-clock";
443 clocks = <&extal1_clk>;
447 clock-output-names = "extal1_div2";
451 subck_clks: subck_clks@e6150080 {
452 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
453 reg = <0xe6150080 4>;
454 clocks = <&sub_clk>, <&sub_clk>;
456 renesas,clock-indices = <
457 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
462 mstp1_clks: mstp1_clks@e6150134 {
463 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
464 reg = <0xe6150134 4>, <0xe6150038 4>;
465 clocks = <&cpg_clocks R8A7740_CLK_S>,
466 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
467 <&cpg_clocks R8A7740_CLK_B>,
468 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
469 <&cpg_clocks R8A7740_CLK_B>;
471 renesas,clock-indices = <
472 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
473 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
477 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
480 mstp2_clks: mstp2_clks@e6150138 {
481 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
482 reg = <0xe6150138 4>, <0xe6150040 4>;
483 clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
484 <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
485 <&cpg_clocks R8A7740_CLK_HP>,
486 <&cpg_clocks R8A7740_CLK_HP>,
487 <&cpg_clocks R8A7740_CLK_HP>,
488 <&sub_clk>, <&sub_clk>, <&sub_clk>,
489 <&sub_clk>, <&sub_clk>, <&sub_clk>,
492 renesas,clock-indices = <
493 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
495 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
496 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
497 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
498 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
499 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
504 "scifa7", "dmac1", "dmac2", "dmac3",
505 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
506 "scifa2", "scifa3", "scifa4";
508 mstp3_clks: mstp3_clks@e615013c {
509 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
510 reg = <0xe615013c 4>, <0xe6150048 4>;
511 clocks = <&cpg_clocks R8A7740_CLK_R>,
512 <&cpg_clocks R8A7740_CLK_HP>,
514 <&cpg_clocks R8A7740_CLK_HP>,
515 <&cpg_clocks R8A7740_CLK_HP>,
516 <&cpg_clocks R8A7740_CLK_HP>,
517 <&cpg_clocks R8A7740_CLK_HP>,
518 <&cpg_clocks R8A7740_CLK_HP>,
519 <&cpg_clocks R8A7740_CLK_HP>;
521 renesas,clock-indices = <
522 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
523 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
524 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
527 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
528 "mmc", "gether", "tpu0";
530 mstp4_clks: mstp4_clks@e6150140 {
531 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
532 reg = <0xe6150140 4>, <0xe615004c 4>;
533 clocks = <&cpg_clocks R8A7740_CLK_HP>,
534 <&cpg_clocks R8A7740_CLK_HP>,
535 <&cpg_clocks R8A7740_CLK_HP>,
536 <&cpg_clocks R8A7740_CLK_HP>;
538 renesas,clock-indices = <
539 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
540 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
543 "usbhost", "sdhi2", "usbfunc", "usphy";