2 * Device Tree Source for Renesas r8a7779
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 /include/ "skeleton.dtsi"
14 #include <dt-bindings/clock/r8a7779-clock.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
18 compatible = "renesas,r8a7779";
19 interrupt-parent = <&gic>;
27 compatible = "arm,cortex-a9";
29 clock-frequency = <1000000000>;
33 compatible = "arm,cortex-a9";
35 clock-frequency = <1000000000>;
39 compatible = "arm,cortex-a9";
41 clock-frequency = <1000000000>;
45 compatible = "arm,cortex-a9";
47 clock-frequency = <1000000000>;
57 gic: interrupt-controller@f0001000 {
58 compatible = "arm,cortex-a9-gic";
59 #interrupt-cells = <3>;
61 reg = <0xf0001000 0x1000>,
65 gpio0: gpio@ffc40000 {
66 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
67 reg = <0xffc40000 0x2c>;
68 interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
71 gpio-ranges = <&pfc 0 0 32>;
72 #interrupt-cells = <2>;
76 gpio1: gpio@ffc41000 {
77 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
78 reg = <0xffc41000 0x2c>;
79 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
82 gpio-ranges = <&pfc 0 32 32>;
83 #interrupt-cells = <2>;
87 gpio2: gpio@ffc42000 {
88 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
89 reg = <0xffc42000 0x2c>;
90 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
93 gpio-ranges = <&pfc 0 64 32>;
94 #interrupt-cells = <2>;
98 gpio3: gpio@ffc43000 {
99 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
100 reg = <0xffc43000 0x2c>;
101 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
104 gpio-ranges = <&pfc 0 96 32>;
105 #interrupt-cells = <2>;
106 interrupt-controller;
109 gpio4: gpio@ffc44000 {
110 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
111 reg = <0xffc44000 0x2c>;
112 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
115 gpio-ranges = <&pfc 0 128 32>;
116 #interrupt-cells = <2>;
117 interrupt-controller;
120 gpio5: gpio@ffc45000 {
121 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
122 reg = <0xffc45000 0x2c>;
123 interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
126 gpio-ranges = <&pfc 0 160 32>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
131 gpio6: gpio@ffc46000 {
132 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
133 reg = <0xffc46000 0x2c>;
134 interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
137 gpio-ranges = <&pfc 0 192 9>;
138 #interrupt-cells = <2>;
139 interrupt-controller;
142 irqpin0: irqpin@fe780010 {
143 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
144 #interrupt-cells = <2>;
146 interrupt-controller;
147 reg = <0xfe78001c 4>,
152 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
153 0 28 IRQ_TYPE_LEVEL_HIGH
154 0 29 IRQ_TYPE_LEVEL_HIGH
155 0 30 IRQ_TYPE_LEVEL_HIGH>;
156 sense-bitfield-width = <2>;
160 #address-cells = <1>;
162 compatible = "renesas,i2c-r8a7779";
163 reg = <0xffc70000 0x1000>;
164 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
170 #address-cells = <1>;
172 compatible = "renesas,i2c-r8a7779";
173 reg = <0xffc71000 0x1000>;
174 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
180 #address-cells = <1>;
182 compatible = "renesas,i2c-r8a7779";
183 reg = <0xffc72000 0x1000>;
184 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
190 #address-cells = <1>;
192 compatible = "renesas,i2c-r8a7779";
193 reg = <0xffc73000 0x1000>;
194 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
199 scif0: serial@ffe40000 {
200 compatible = "renesas,scif-r8a7779", "renesas,scif";
201 reg = <0xffe40000 0x100>;
202 interrupt-parent = <&gic>;
203 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&cpg_clocks R8A7779_CLK_P>;
205 clock-names = "sci_ick";
209 scif1: serial@ffe41000 {
210 compatible = "renesas,scif-r8a7779", "renesas,scif";
211 reg = <0xffe41000 0x100>;
212 interrupt-parent = <&gic>;
213 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&cpg_clocks R8A7779_CLK_P>;
215 clock-names = "sci_ick";
219 scif2: serial@ffe42000 {
220 compatible = "renesas,scif-r8a7779", "renesas,scif";
221 reg = <0xffe42000 0x100>;
222 interrupt-parent = <&gic>;
223 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cpg_clocks R8A7779_CLK_P>;
225 clock-names = "sci_ick";
229 scif3: serial@ffe43000 {
230 compatible = "renesas,scif-r8a7779", "renesas,scif";
231 reg = <0xffe43000 0x100>;
232 interrupt-parent = <&gic>;
233 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cpg_clocks R8A7779_CLK_P>;
235 clock-names = "sci_ick";
239 scif4: serial@ffe44000 {
240 compatible = "renesas,scif-r8a7779", "renesas,scif";
241 reg = <0xffe44000 0x100>;
242 interrupt-parent = <&gic>;
243 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&cpg_clocks R8A7779_CLK_P>;
245 clock-names = "sci_ick";
249 scif5: serial@ffe45000 {
250 compatible = "renesas,scif-r8a7779", "renesas,scif";
251 reg = <0xffe45000 0x100>;
252 interrupt-parent = <&gic>;
253 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&cpg_clocks R8A7779_CLK_P>;
255 clock-names = "sci_ick";
260 compatible = "renesas,pfc-r8a7779";
261 reg = <0xfffc0000 0x23c>;
265 compatible = "renesas,rcar-thermal";
266 reg = <0xffc48000 0x38>;
269 sata: sata@fc600000 {
270 compatible = "renesas,rcar-sata";
271 reg = <0xfc600000 0x2000>;
272 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
277 compatible = "renesas,sdhi-r8a7779";
278 reg = <0xffe4c000 0x100>;
279 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
287 compatible = "renesas,sdhi-r8a7779";
288 reg = <0xffe4d000 0x100>;
289 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
297 compatible = "renesas,sdhi-r8a7779";
298 reg = <0xffe4e000 0x100>;
299 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
307 compatible = "renesas,sdhi-r8a7779";
308 reg = <0xffe4f000 0x100>;
309 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
316 hspi0: spi@fffc7000 {
317 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
318 reg = <0xfffc7000 0x18>;
319 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
322 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
326 hspi1: spi@fffc8000 {
327 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
328 reg = <0xfffc8000 0x18>;
329 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
330 #address-cells = <1>;
332 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
336 hspi2: spi@fffc6000 {
337 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
338 reg = <0xfffc6000 0x18>;
339 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
340 #address-cells = <1>;
342 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
347 #address-cells = <1>;
351 /* External root clock */
352 extal_clk: extal_clk {
353 compatible = "fixed-clock";
355 /* This value must be overriden by the board. */
356 clock-frequency = <0>;
357 clock-output-names = "extal";
360 /* Special CPG clocks */
361 cpg_clocks: clocks@ffc80000 {
362 compatible = "renesas,r8a7779-cpg-clocks";
363 reg = <0xffc80000 0x30>;
364 clocks = <&extal_clk>;
366 clock-output-names = "plla", "z", "zs", "s",
367 "s1", "p", "b", "out";
370 /* Fixed factor clocks */
372 compatible = "fixed-factor-clock";
373 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
377 clock-output-names = "i";
380 compatible = "fixed-factor-clock";
381 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
385 clock-output-names = "s3";
388 compatible = "fixed-factor-clock";
389 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
393 clock-output-names = "s4";
396 compatible = "fixed-factor-clock";
397 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
401 clock-output-names = "g";
405 mstp0_clks: clocks@ffc80030 {
406 compatible = "renesas,r8a7779-mstp-clocks",
407 "renesas,cpg-mstp-clocks";
408 reg = <0xffc80030 4>;
409 clocks = <&cpg_clocks R8A7779_CLK_S>,
410 <&cpg_clocks R8A7779_CLK_P>,
411 <&cpg_clocks R8A7779_CLK_P>,
412 <&cpg_clocks R8A7779_CLK_P>,
413 <&cpg_clocks R8A7779_CLK_S>,
414 <&cpg_clocks R8A7779_CLK_S>,
415 <&cpg_clocks R8A7779_CLK_S1>,
416 <&cpg_clocks R8A7779_CLK_S1>,
417 <&cpg_clocks R8A7779_CLK_S1>,
418 <&cpg_clocks R8A7779_CLK_S1>,
419 <&cpg_clocks R8A7779_CLK_S1>,
420 <&cpg_clocks R8A7779_CLK_S1>,
421 <&cpg_clocks R8A7779_CLK_P>,
422 <&cpg_clocks R8A7779_CLK_P>,
423 <&cpg_clocks R8A7779_CLK_P>,
424 <&cpg_clocks R8A7779_CLK_P>;
426 renesas,clock-indices = <
427 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
428 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
429 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
430 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
431 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
432 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
433 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
434 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
437 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
438 "hscif0", "scif5", "scif4", "scif3", "scif2",
439 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
442 mstp1_clks: clocks@ffc80034 {
443 compatible = "renesas,r8a7779-mstp-clocks",
444 "renesas,cpg-mstp-clocks";
445 reg = <0xffc80034 4>, <0xffc80044 4>;
446 clocks = <&cpg_clocks R8A7779_CLK_P>,
447 <&cpg_clocks R8A7779_CLK_P>,
448 <&cpg_clocks R8A7779_CLK_S>,
449 <&cpg_clocks R8A7779_CLK_S>,
450 <&cpg_clocks R8A7779_CLK_S>,
451 <&cpg_clocks R8A7779_CLK_S>,
452 <&cpg_clocks R8A7779_CLK_P>,
453 <&cpg_clocks R8A7779_CLK_P>,
454 <&cpg_clocks R8A7779_CLK_P>,
455 <&cpg_clocks R8A7779_CLK_S>;
457 renesas,clock-indices = <
458 R8A7779_CLK_USB01 R8A7779_CLK_USB2
459 R8A7779_CLK_DU R8A7779_CLK_VIN2
460 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
461 R8A7779_CLK_ETHER R8A7779_CLK_SATA
462 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
471 mstp3_clks: clocks@ffc8003c {
472 compatible = "renesas,r8a7779-mstp-clocks",
473 "renesas,cpg-mstp-clocks";
474 reg = <0xffc8003c 4>;
475 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
476 <&s4_clk>, <&s4_clk>;
478 renesas,clock-indices = <
479 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
480 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
481 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
484 "sdhi3", "sdhi2", "sdhi1", "sdhi0",