2 * Device Tree Source for the r8a7790 SoC
4 * Copyright (C) 2013-2014 Renesas Solutions Corp.
5 * Copyright (C) 2014 Cogent Embedded Inc.
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a7790-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r8a7790";
18 interrupt-parent = <&gic>;
48 compatible = "arm,cortex-a15";
50 clock-frequency = <1300000000>;
51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7790_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1400000 1000000>,
66 compatible = "arm,cortex-a15";
68 clock-frequency = <1300000000>;
73 compatible = "arm,cortex-a15";
75 clock-frequency = <1300000000>;
80 compatible = "arm,cortex-a15";
82 clock-frequency = <1300000000>;
87 compatible = "arm,cortex-a7";
89 clock-frequency = <780000000>;
94 compatible = "arm,cortex-a7";
96 clock-frequency = <780000000>;
101 compatible = "arm,cortex-a7";
103 clock-frequency = <780000000>;
108 compatible = "arm,cortex-a7";
110 clock-frequency = <780000000>;
114 gic: interrupt-controller@f1001000 {
115 compatible = "arm,cortex-a15-gic";
116 #interrupt-cells = <3>;
117 #address-cells = <0>;
118 interrupt-controller;
119 reg = <0 0xf1001000 0 0x1000>,
120 <0 0xf1002000 0 0x1000>,
121 <0 0xf1004000 0 0x2000>,
122 <0 0xf1006000 0 0x2000>;
123 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
126 gpio0: gpio@e6050000 {
127 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
128 reg = <0 0xe6050000 0 0x50>;
129 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
132 gpio-ranges = <&pfc 0 0 32>;
133 #interrupt-cells = <2>;
134 interrupt-controller;
135 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
138 gpio1: gpio@e6051000 {
139 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
140 reg = <0 0xe6051000 0 0x50>;
141 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
144 gpio-ranges = <&pfc 0 32 32>;
145 #interrupt-cells = <2>;
146 interrupt-controller;
147 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
150 gpio2: gpio@e6052000 {
151 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
152 reg = <0 0xe6052000 0 0x50>;
153 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
156 gpio-ranges = <&pfc 0 64 32>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
159 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
162 gpio3: gpio@e6053000 {
163 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
164 reg = <0 0xe6053000 0 0x50>;
165 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
168 gpio-ranges = <&pfc 0 96 32>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
171 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
174 gpio4: gpio@e6054000 {
175 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
176 reg = <0 0xe6054000 0 0x50>;
177 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
180 gpio-ranges = <&pfc 0 128 32>;
181 #interrupt-cells = <2>;
182 interrupt-controller;
183 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
186 gpio5: gpio@e6055000 {
187 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
188 reg = <0 0xe6055000 0 0x50>;
189 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
192 gpio-ranges = <&pfc 0 160 32>;
193 #interrupt-cells = <2>;
194 interrupt-controller;
195 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
199 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
200 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
201 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
206 compatible = "arm,armv7-timer";
207 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
208 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
209 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
210 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
213 cmt0: timer@ffca0000 {
214 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
215 reg = <0 0xffca0000 0 0x1004>;
216 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
217 <0 143 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
221 renesas,channels-mask = <0x60>;
226 cmt1: timer@e6130000 {
227 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
228 reg = <0 0xe6130000 0 0x1004>;
229 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
230 <0 121 IRQ_TYPE_LEVEL_HIGH>,
231 <0 122 IRQ_TYPE_LEVEL_HIGH>,
232 <0 123 IRQ_TYPE_LEVEL_HIGH>,
233 <0 124 IRQ_TYPE_LEVEL_HIGH>,
234 <0 125 IRQ_TYPE_LEVEL_HIGH>,
235 <0 126 IRQ_TYPE_LEVEL_HIGH>,
236 <0 127 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
240 renesas,channels-mask = <0xff>;
245 irqc0: interrupt-controller@e61c0000 {
246 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
247 #interrupt-cells = <2>;
248 interrupt-controller;
249 reg = <0 0xe61c0000 0 0x200>;
250 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
251 <0 1 IRQ_TYPE_LEVEL_HIGH>,
252 <0 2 IRQ_TYPE_LEVEL_HIGH>,
253 <0 3 IRQ_TYPE_LEVEL_HIGH>;
256 dmac0: dma-controller@e6700000 {
257 compatible = "renesas,rcar-dmac";
258 reg = <0 0xe6700000 0 0x20000>;
259 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
260 0 200 IRQ_TYPE_LEVEL_HIGH
261 0 201 IRQ_TYPE_LEVEL_HIGH
262 0 202 IRQ_TYPE_LEVEL_HIGH
263 0 203 IRQ_TYPE_LEVEL_HIGH
264 0 204 IRQ_TYPE_LEVEL_HIGH
265 0 205 IRQ_TYPE_LEVEL_HIGH
266 0 206 IRQ_TYPE_LEVEL_HIGH
267 0 207 IRQ_TYPE_LEVEL_HIGH
268 0 208 IRQ_TYPE_LEVEL_HIGH
269 0 209 IRQ_TYPE_LEVEL_HIGH
270 0 210 IRQ_TYPE_LEVEL_HIGH
271 0 211 IRQ_TYPE_LEVEL_HIGH
272 0 212 IRQ_TYPE_LEVEL_HIGH
273 0 213 IRQ_TYPE_LEVEL_HIGH
274 0 214 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-names = "error",
276 "ch0", "ch1", "ch2", "ch3",
277 "ch4", "ch5", "ch6", "ch7",
278 "ch8", "ch9", "ch10", "ch11",
279 "ch12", "ch13", "ch14";
280 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
286 dmac1: dma-controller@e6720000 {
287 compatible = "renesas,rcar-dmac";
288 reg = <0 0xe6720000 0 0x20000>;
289 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
290 0 216 IRQ_TYPE_LEVEL_HIGH
291 0 217 IRQ_TYPE_LEVEL_HIGH
292 0 218 IRQ_TYPE_LEVEL_HIGH
293 0 219 IRQ_TYPE_LEVEL_HIGH
294 0 308 IRQ_TYPE_LEVEL_HIGH
295 0 309 IRQ_TYPE_LEVEL_HIGH
296 0 310 IRQ_TYPE_LEVEL_HIGH
297 0 311 IRQ_TYPE_LEVEL_HIGH
298 0 312 IRQ_TYPE_LEVEL_HIGH
299 0 313 IRQ_TYPE_LEVEL_HIGH
300 0 314 IRQ_TYPE_LEVEL_HIGH
301 0 315 IRQ_TYPE_LEVEL_HIGH
302 0 316 IRQ_TYPE_LEVEL_HIGH
303 0 317 IRQ_TYPE_LEVEL_HIGH
304 0 318 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-names = "error",
306 "ch0", "ch1", "ch2", "ch3",
307 "ch4", "ch5", "ch6", "ch7",
308 "ch8", "ch9", "ch10", "ch11",
309 "ch12", "ch13", "ch14";
310 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
316 #address-cells = <1>;
318 compatible = "renesas,i2c-r8a7790";
319 reg = <0 0xe6508000 0 0x40>;
320 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
326 #address-cells = <1>;
328 compatible = "renesas,i2c-r8a7790";
329 reg = <0 0xe6518000 0 0x40>;
330 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
336 #address-cells = <1>;
338 compatible = "renesas,i2c-r8a7790";
339 reg = <0 0xe6530000 0 0x40>;
340 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
346 #address-cells = <1>;
348 compatible = "renesas,i2c-r8a7790";
349 reg = <0 0xe6540000 0 0x40>;
350 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
356 #address-cells = <1>;
358 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
359 reg = <0 0xe6500000 0 0x425>;
360 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
366 #address-cells = <1>;
368 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
369 reg = <0 0xe6510000 0 0x425>;
370 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
376 #address-cells = <1>;
378 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
379 reg = <0 0xe6520000 0 0x425>;
380 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
386 #address-cells = <1>;
388 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
389 reg = <0 0xe60b0000 0 0x425>;
390 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
395 mmcif0: mmcif@ee200000 {
396 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
397 reg = <0 0xee200000 0 0x80>;
398 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
404 mmcif1: mmc@ee220000 {
405 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
406 reg = <0 0xee220000 0 0x80>;
407 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
414 compatible = "renesas,pfc-r8a7790";
415 reg = <0 0xe6060000 0 0x250>;
419 compatible = "renesas,sdhi-r8a7790";
420 reg = <0 0xee100000 0 0x200>;
421 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
428 compatible = "renesas,sdhi-r8a7790";
429 reg = <0 0xee120000 0 0x200>;
430 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
437 compatible = "renesas,sdhi-r8a7790";
438 reg = <0 0xee140000 0 0x100>;
439 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
446 compatible = "renesas,sdhi-r8a7790";
447 reg = <0 0xee160000 0 0x100>;
448 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
454 scifa0: serial@e6c40000 {
455 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
456 reg = <0 0xe6c40000 0 64>;
457 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
459 clock-names = "sci_ick";
463 scifa1: serial@e6c50000 {
464 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
465 reg = <0 0xe6c50000 0 64>;
466 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
468 clock-names = "sci_ick";
472 scifa2: serial@e6c60000 {
473 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
474 reg = <0 0xe6c60000 0 64>;
475 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
477 clock-names = "sci_ick";
481 scifb0: serial@e6c20000 {
482 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
483 reg = <0 0xe6c20000 0 64>;
484 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
486 clock-names = "sci_ick";
490 scifb1: serial@e6c30000 {
491 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
492 reg = <0 0xe6c30000 0 64>;
493 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
495 clock-names = "sci_ick";
499 scifb2: serial@e6ce0000 {
500 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
501 reg = <0 0xe6ce0000 0 64>;
502 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
504 clock-names = "sci_ick";
508 scif0: serial@e6e60000 {
509 compatible = "renesas,scif-r8a7790", "renesas,scif";
510 reg = <0 0xe6e60000 0 64>;
511 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
513 clock-names = "sci_ick";
517 scif1: serial@e6e68000 {
518 compatible = "renesas,scif-r8a7790", "renesas,scif";
519 reg = <0 0xe6e68000 0 64>;
520 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
522 clock-names = "sci_ick";
526 hscif0: serial@e62c0000 {
527 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
528 reg = <0 0xe62c0000 0 96>;
529 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
531 clock-names = "sci_ick";
535 hscif1: serial@e62c8000 {
536 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
537 reg = <0 0xe62c8000 0 96>;
538 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
540 clock-names = "sci_ick";
544 ether: ethernet@ee700000 {
545 compatible = "renesas,ether-r8a7790";
546 reg = <0 0xee700000 0 0x400>;
547 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
550 #address-cells = <1>;
555 sata0: sata@ee300000 {
556 compatible = "renesas,sata-r8a7790";
557 reg = <0 0xee300000 0 0x2000>;
558 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
563 sata1: sata@ee500000 {
564 compatible = "renesas,sata-r8a7790";
565 reg = <0 0xee500000 0 0x2000>;
566 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
571 usbphy: usb-phy@e6590100 {
572 compatible = "renesas,usb-phy-r8a7790";
573 reg = <0 0xe6590100 0 0x100>;
574 #address-cells = <1>;
576 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
577 clock-names = "usbhs";
580 usb0: usb-channel@0 {
584 usb2: usb-channel@2 {
590 vin0: video@e6ef0000 {
591 compatible = "renesas,vin-r8a7790";
592 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
593 reg = <0 0xe6ef0000 0 0x1000>;
594 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
598 vin1: video@e6ef1000 {
599 compatible = "renesas,vin-r8a7790";
600 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
601 reg = <0 0xe6ef1000 0 0x1000>;
602 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
606 vin2: video@e6ef2000 {
607 compatible = "renesas,vin-r8a7790";
608 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
609 reg = <0 0xe6ef2000 0 0x1000>;
610 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
614 vin3: video@e6ef3000 {
615 compatible = "renesas,vin-r8a7790";
616 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
617 reg = <0 0xe6ef3000 0 0x1000>;
618 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
623 compatible = "renesas,vsp1";
624 reg = <0 0xfe920000 0 0x8000>;
625 interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
635 compatible = "renesas,vsp1";
636 reg = <0 0xfe928000 0 0x8000>;
637 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
648 compatible = "renesas,vsp1";
649 reg = <0 0xfe930000 0 0x8000>;
650 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
661 compatible = "renesas,vsp1";
662 reg = <0 0xfe938000 0 0x8000>;
663 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
673 du: display@feb00000 {
674 compatible = "renesas,du-r8a7790";
675 reg = <0 0xfeb00000 0 0x70000>,
676 <0 0xfeb90000 0 0x1c>,
677 <0 0xfeb94000 0 0x1c>;
678 reg-names = "du", "lvds.0", "lvds.1";
679 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
680 <0 268 IRQ_TYPE_LEVEL_HIGH>,
681 <0 269 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
683 <&mstp7_clks R8A7790_CLK_DU1>,
684 <&mstp7_clks R8A7790_CLK_DU2>,
685 <&mstp7_clks R8A7790_CLK_LVDS0>,
686 <&mstp7_clks R8A7790_CLK_LVDS1>;
687 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
691 #address-cells = <1>;
696 du_out_rgb: endpoint {
701 du_out_lvds0: endpoint {
706 du_out_lvds1: endpoint {
713 #address-cells = <2>;
717 /* External root clock */
718 extal_clk: extal_clk {
719 compatible = "fixed-clock";
721 /* This value must be overriden by the board. */
722 clock-frequency = <0>;
723 clock-output-names = "extal";
726 /* External PCIe clock - can be overridden by the board */
727 pcie_bus_clk: pcie_bus_clk {
728 compatible = "fixed-clock";
730 clock-frequency = <100000000>;
731 clock-output-names = "pcie_bus";
736 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
737 * default. Boards that provide audio clocks should override them.
739 audio_clk_a: audio_clk_a {
740 compatible = "fixed-clock";
742 clock-frequency = <0>;
743 clock-output-names = "audio_clk_a";
745 audio_clk_b: audio_clk_b {
746 compatible = "fixed-clock";
748 clock-frequency = <0>;
749 clock-output-names = "audio_clk_b";
751 audio_clk_c: audio_clk_c {
752 compatible = "fixed-clock";
754 clock-frequency = <0>;
755 clock-output-names = "audio_clk_c";
758 /* Special CPG clocks */
759 cpg_clocks: cpg_clocks@e6150000 {
760 compatible = "renesas,r8a7790-cpg-clocks",
761 "renesas,rcar-gen2-cpg-clocks";
762 reg = <0 0xe6150000 0 0x1000>;
763 clocks = <&extal_clk>;
765 clock-output-names = "main", "pll0", "pll1", "pll3",
766 "lb", "qspi", "sdh", "sd0", "sd1",
770 /* Variable factor clocks */
771 sd2_clk: sd2_clk@e6150078 {
772 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
773 reg = <0 0xe6150078 0 4>;
774 clocks = <&pll1_div2_clk>;
776 clock-output-names = "sd2";
778 sd3_clk: sd3_clk@e615007c {
779 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
780 reg = <0 0xe615007c 0 4>;
781 clocks = <&pll1_div2_clk>;
783 clock-output-names = "sd3";
785 mmc0_clk: mmc0_clk@e6150240 {
786 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
787 reg = <0 0xe6150240 0 4>;
788 clocks = <&pll1_div2_clk>;
790 clock-output-names = "mmc0";
792 mmc1_clk: mmc1_clk@e6150244 {
793 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
794 reg = <0 0xe6150244 0 4>;
795 clocks = <&pll1_div2_clk>;
797 clock-output-names = "mmc1";
799 ssp_clk: ssp_clk@e6150248 {
800 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
801 reg = <0 0xe6150248 0 4>;
802 clocks = <&pll1_div2_clk>;
804 clock-output-names = "ssp";
806 ssprs_clk: ssprs_clk@e615024c {
807 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
808 reg = <0 0xe615024c 0 4>;
809 clocks = <&pll1_div2_clk>;
811 clock-output-names = "ssprs";
814 /* Fixed factor clocks */
815 pll1_div2_clk: pll1_div2_clk {
816 compatible = "fixed-factor-clock";
817 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
821 clock-output-names = "pll1_div2";
824 compatible = "fixed-factor-clock";
825 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
829 clock-output-names = "z2";
832 compatible = "fixed-factor-clock";
833 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
837 clock-output-names = "zg";
840 compatible = "fixed-factor-clock";
841 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
845 clock-output-names = "zx";
848 compatible = "fixed-factor-clock";
849 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
853 clock-output-names = "zs";
856 compatible = "fixed-factor-clock";
857 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
861 clock-output-names = "hp";
864 compatible = "fixed-factor-clock";
865 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
869 clock-output-names = "i";
872 compatible = "fixed-factor-clock";
873 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
877 clock-output-names = "b";
880 compatible = "fixed-factor-clock";
881 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
885 clock-output-names = "p";
888 compatible = "fixed-factor-clock";
889 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
893 clock-output-names = "cl";
896 compatible = "fixed-factor-clock";
897 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
901 clock-output-names = "m2";
904 compatible = "fixed-factor-clock";
905 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
909 clock-output-names = "imp";
912 compatible = "fixed-factor-clock";
913 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
915 clock-div = <(48 * 1024)>;
917 clock-output-names = "rclk";
919 oscclk_clk: oscclk_clk {
920 compatible = "fixed-factor-clock";
921 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
923 clock-div = <(12 * 1024)>;
925 clock-output-names = "oscclk";
928 compatible = "fixed-factor-clock";
929 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
933 clock-output-names = "zb3";
935 zb3d2_clk: zb3d2_clk {
936 compatible = "fixed-factor-clock";
937 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
941 clock-output-names = "zb3d2";
944 compatible = "fixed-factor-clock";
945 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
949 clock-output-names = "ddr";
952 compatible = "fixed-factor-clock";
953 clocks = <&pll1_div2_clk>;
957 clock-output-names = "mp";
960 compatible = "fixed-factor-clock";
961 clocks = <&extal_clk>;
965 clock-output-names = "cp";
969 mstp0_clks: mstp0_clks@e6150130 {
970 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
971 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
974 renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
975 clock-output-names = "msiof0";
977 mstp1_clks: mstp1_clks@e6150134 {
978 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
979 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
980 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
981 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
982 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
983 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
985 renesas,clock-indices = <
986 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
987 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
988 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
989 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
990 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
991 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
992 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
995 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
996 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
997 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
998 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1000 mstp2_clks: mstp2_clks@e6150138 {
1001 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1002 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1003 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1004 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1007 renesas,clock-indices = <
1008 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1009 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1010 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1011 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1013 clock-output-names =
1014 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1015 "scifb1", "msiof1", "msiof3", "scifb2",
1016 "sys-dmac1", "sys-dmac0";
1018 mstp3_clks: mstp3_clks@e615013c {
1019 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1020 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1021 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1022 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1023 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
1025 renesas,clock-indices = <
1026 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1027 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1028 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1030 clock-output-names =
1031 "iic2", "tpu0", "mmcif1", "sdhi3",
1032 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1033 "iic0", "pciec", "iic1", "ssusb", "cmt1";
1035 mstp5_clks: mstp5_clks@e6150144 {
1036 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1037 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1038 clocks = <&extal_clk>, <&p_clk>;
1040 renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
1041 clock-output-names = "thermal", "pwm";
1043 mstp7_clks: mstp7_clks@e615014c {
1044 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1045 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1046 clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1047 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1050 renesas,clock-indices = <
1051 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1052 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1053 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1054 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1056 clock-output-names =
1057 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1058 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1060 mstp8_clks: mstp8_clks@e6150990 {
1061 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1062 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1063 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
1064 <&zs_clk>, <&zs_clk>;
1066 renesas,clock-indices = <
1067 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
1068 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
1071 clock-output-names =
1072 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
1074 mstp9_clks: mstp9_clks@e6150994 {
1075 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1076 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1077 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1078 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1079 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1080 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1082 renesas,clock-indices = <
1083 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1084 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1085 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1086 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1088 clock-output-names =
1089 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1090 "rcan1", "rcan0", "qspi_mod", "iic3",
1091 "i2c3", "i2c2", "i2c1", "i2c0";
1093 mstp10_clks: mstp10_clks@e6150998 {
1094 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1095 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1097 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1098 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1100 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1101 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1102 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1103 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1104 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1105 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1110 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1111 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1113 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1114 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1115 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1117 clock-output-names =
1119 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1120 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1122 "scu-dvc1", "scu-dvc0",
1123 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1124 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1128 qspi: spi@e6b10000 {
1129 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1130 reg = <0 0xe6b10000 0 0x2c>;
1131 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1132 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1133 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1134 dma-names = "tx", "rx";
1136 #address-cells = <1>;
1138 status = "disabled";
1141 msiof0: spi@e6e20000 {
1142 compatible = "renesas,msiof-r8a7790";
1143 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
1144 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1146 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1147 dma-names = "tx", "rx";
1148 #address-cells = <1>;
1150 status = "disabled";
1153 msiof1: spi@e6e10000 {
1154 compatible = "renesas,msiof-r8a7790";
1155 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
1156 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1157 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1158 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1159 dma-names = "tx", "rx";
1160 #address-cells = <1>;
1162 status = "disabled";
1165 msiof2: spi@e6e00000 {
1166 compatible = "renesas,msiof-r8a7790";
1167 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
1168 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1169 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1170 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1171 dma-names = "tx", "rx";
1172 #address-cells = <1>;
1174 status = "disabled";
1177 msiof3: spi@e6c90000 {
1178 compatible = "renesas,msiof-r8a7790";
1179 reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
1180 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
1181 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1182 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1183 dma-names = "tx", "rx";
1184 #address-cells = <1>;
1186 status = "disabled";
1189 xhci: usb@ee000000 {
1190 compatible = "renesas,xhci-r8a7790";
1191 reg = <0 0xee000000 0 0xc00>;
1192 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1196 status = "disabled";
1199 pci0: pci@ee090000 {
1200 compatible = "renesas,pci-r8a7790";
1201 device_type = "pci";
1202 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1203 reg = <0 0xee090000 0 0xc00>,
1204 <0 0xee080000 0 0x1100>;
1205 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1206 status = "disabled";
1209 #address-cells = <3>;
1211 #interrupt-cells = <1>;
1212 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1213 interrupt-map-mask = <0xff00 0 0 0x7>;
1214 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1215 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1216 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1219 reg = <0x800 0 0 0 0>;
1220 device_type = "pci";
1226 reg = <0x1000 0 0 0 0>;
1227 device_type = "pci";
1233 pci1: pci@ee0b0000 {
1234 compatible = "renesas,pci-r8a7790";
1235 device_type = "pci";
1236 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1237 reg = <0 0xee0b0000 0 0xc00>,
1238 <0 0xee0a0000 0 0x1100>;
1239 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
1240 status = "disabled";
1243 #address-cells = <3>;
1245 #interrupt-cells = <1>;
1246 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1247 interrupt-map-mask = <0xff00 0 0 0x7>;
1248 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1249 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1250 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
1253 pci2: pci@ee0d0000 {
1254 compatible = "renesas,pci-r8a7790";
1255 device_type = "pci";
1256 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1257 reg = <0 0xee0d0000 0 0xc00>,
1258 <0 0xee0c0000 0 0x1100>;
1259 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1260 status = "disabled";
1263 #address-cells = <3>;
1265 #interrupt-cells = <1>;
1266 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1267 interrupt-map-mask = <0xff00 0 0 0x7>;
1268 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1269 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1270 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1273 reg = <0x800 0 0 0 0>;
1274 device_type = "pci";
1280 reg = <0x1000 0 0 0 0>;
1281 device_type = "pci";
1287 pciec: pcie@fe000000 {
1288 compatible = "renesas,pcie-r8a7790";
1289 reg = <0 0xfe000000 0 0x80000>;
1290 #address-cells = <3>;
1292 bus-range = <0x00 0xff>;
1293 device_type = "pci";
1294 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1295 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1296 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1297 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1298 /* Map all possible DDR as inbound ranges */
1299 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1300 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1301 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1302 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1303 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1304 #interrupt-cells = <1>;
1305 interrupt-map-mask = <0 0 0 0>;
1306 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1307 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1308 clock-names = "pcie", "pcie_bus";
1309 status = "disabled";
1312 rcar_sound: rcar_sound@0xec500000 {
1313 #sound-dai-cells = <1>;
1314 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1315 reg = <0 0xec500000 0 0x1000>, /* SCU */
1316 <0 0xec5a0000 0 0x100>, /* ADG */
1317 <0 0xec540000 0 0x1000>, /* SSIU */
1318 <0 0xec541000 0 0x1280>; /* SSI */
1319 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1320 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1321 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1322 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1323 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1324 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1325 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1326 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1327 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1328 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1329 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1330 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1331 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1332 clock-names = "ssi-all",
1333 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1334 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1335 "src.9", "src.8", "src.7", "src.6", "src.5",
1336 "src.4", "src.3", "src.2", "src.1", "src.0",
1338 "clk_a", "clk_b", "clk_c", "clk_i";
1340 status = "disabled";
1361 ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1362 ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1363 ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1364 ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1365 ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1366 ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1367 ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1368 ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1369 ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1370 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };