2 * Device Tree Source for the r8a7790 SoC
4 * Copyright (C) 2013-2014 Renesas Solutions Corp.
5 * Copyright (C) 2014 Cogent Embedded Inc.
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a7790-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r8a7790";
18 interrupt-parent = <&gic>;
48 compatible = "arm,cortex-a15";
50 clock-frequency = <1300000000>;
51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7790_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1400000 1000000>,
66 compatible = "arm,cortex-a15";
68 clock-frequency = <1300000000>;
73 compatible = "arm,cortex-a15";
75 clock-frequency = <1300000000>;
80 compatible = "arm,cortex-a15";
82 clock-frequency = <1300000000>;
87 compatible = "arm,cortex-a7";
89 clock-frequency = <780000000>;
94 compatible = "arm,cortex-a7";
96 clock-frequency = <780000000>;
101 compatible = "arm,cortex-a7";
103 clock-frequency = <780000000>;
108 compatible = "arm,cortex-a7";
110 clock-frequency = <780000000>;
114 gic: interrupt-controller@f1001000 {
115 compatible = "arm,cortex-a15-gic";
116 #interrupt-cells = <3>;
117 #address-cells = <0>;
118 interrupt-controller;
119 reg = <0 0xf1001000 0 0x1000>,
120 <0 0xf1002000 0 0x1000>,
121 <0 0xf1004000 0 0x2000>,
122 <0 0xf1006000 0 0x2000>;
123 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
126 gpio0: gpio@e6050000 {
127 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
128 reg = <0 0xe6050000 0 0x50>;
129 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
132 gpio-ranges = <&pfc 0 0 32>;
133 #interrupt-cells = <2>;
134 interrupt-controller;
135 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
138 gpio1: gpio@e6051000 {
139 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
140 reg = <0 0xe6051000 0 0x50>;
141 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
144 gpio-ranges = <&pfc 0 32 32>;
145 #interrupt-cells = <2>;
146 interrupt-controller;
147 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
150 gpio2: gpio@e6052000 {
151 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
152 reg = <0 0xe6052000 0 0x50>;
153 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
156 gpio-ranges = <&pfc 0 64 32>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
159 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
162 gpio3: gpio@e6053000 {
163 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
164 reg = <0 0xe6053000 0 0x50>;
165 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
168 gpio-ranges = <&pfc 0 96 32>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
171 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
174 gpio4: gpio@e6054000 {
175 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
176 reg = <0 0xe6054000 0 0x50>;
177 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
180 gpio-ranges = <&pfc 0 128 32>;
181 #interrupt-cells = <2>;
182 interrupt-controller;
183 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
186 gpio5: gpio@e6055000 {
187 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
188 reg = <0 0xe6055000 0 0x50>;
189 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
192 gpio-ranges = <&pfc 0 160 32>;
193 #interrupt-cells = <2>;
194 interrupt-controller;
195 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
199 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
200 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
201 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
206 compatible = "arm,armv7-timer";
207 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
208 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
209 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
210 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
213 cmt0: timer@ffca0000 {
214 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
215 reg = <0 0xffca0000 0 0x1004>;
216 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
217 <0 143 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
221 renesas,channels-mask = <0x60>;
226 cmt1: timer@e6130000 {
227 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
228 reg = <0 0xe6130000 0 0x1004>;
229 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
230 <0 121 IRQ_TYPE_LEVEL_HIGH>,
231 <0 122 IRQ_TYPE_LEVEL_HIGH>,
232 <0 123 IRQ_TYPE_LEVEL_HIGH>,
233 <0 124 IRQ_TYPE_LEVEL_HIGH>,
234 <0 125 IRQ_TYPE_LEVEL_HIGH>,
235 <0 126 IRQ_TYPE_LEVEL_HIGH>,
236 <0 127 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
240 renesas,channels-mask = <0xff>;
245 irqc0: interrupt-controller@e61c0000 {
246 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
247 #interrupt-cells = <2>;
248 interrupt-controller;
249 reg = <0 0xe61c0000 0 0x200>;
250 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
251 <0 1 IRQ_TYPE_LEVEL_HIGH>,
252 <0 2 IRQ_TYPE_LEVEL_HIGH>,
253 <0 3 IRQ_TYPE_LEVEL_HIGH>;
256 dmac0: dma-controller@e6700000 {
257 compatible = "renesas,rcar-dmac";
258 reg = <0 0xe6700000 0 0x20000>;
259 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
260 0 200 IRQ_TYPE_LEVEL_HIGH
261 0 201 IRQ_TYPE_LEVEL_HIGH
262 0 202 IRQ_TYPE_LEVEL_HIGH
263 0 203 IRQ_TYPE_LEVEL_HIGH
264 0 204 IRQ_TYPE_LEVEL_HIGH
265 0 205 IRQ_TYPE_LEVEL_HIGH
266 0 206 IRQ_TYPE_LEVEL_HIGH
267 0 207 IRQ_TYPE_LEVEL_HIGH
268 0 208 IRQ_TYPE_LEVEL_HIGH
269 0 209 IRQ_TYPE_LEVEL_HIGH
270 0 210 IRQ_TYPE_LEVEL_HIGH
271 0 211 IRQ_TYPE_LEVEL_HIGH
272 0 212 IRQ_TYPE_LEVEL_HIGH
273 0 213 IRQ_TYPE_LEVEL_HIGH
274 0 214 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-names = "error",
276 "ch0", "ch1", "ch2", "ch3",
277 "ch4", "ch5", "ch6", "ch7",
278 "ch8", "ch9", "ch10", "ch11",
279 "ch12", "ch13", "ch14";
280 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
286 dmac1: dma-controller@e6720000 {
287 compatible = "renesas,rcar-dmac";
288 reg = <0 0xe6720000 0 0x20000>;
289 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
290 0 216 IRQ_TYPE_LEVEL_HIGH
291 0 217 IRQ_TYPE_LEVEL_HIGH
292 0 218 IRQ_TYPE_LEVEL_HIGH
293 0 219 IRQ_TYPE_LEVEL_HIGH
294 0 308 IRQ_TYPE_LEVEL_HIGH
295 0 309 IRQ_TYPE_LEVEL_HIGH
296 0 310 IRQ_TYPE_LEVEL_HIGH
297 0 311 IRQ_TYPE_LEVEL_HIGH
298 0 312 IRQ_TYPE_LEVEL_HIGH
299 0 313 IRQ_TYPE_LEVEL_HIGH
300 0 314 IRQ_TYPE_LEVEL_HIGH
301 0 315 IRQ_TYPE_LEVEL_HIGH
302 0 316 IRQ_TYPE_LEVEL_HIGH
303 0 317 IRQ_TYPE_LEVEL_HIGH
304 0 318 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-names = "error",
306 "ch0", "ch1", "ch2", "ch3",
307 "ch4", "ch5", "ch6", "ch7",
308 "ch8", "ch9", "ch10", "ch11",
309 "ch12", "ch13", "ch14";
310 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
316 audma0: dma-controller@ec700000 {
317 compatible = "renesas,rcar-dmac";
318 reg = <0 0xec700000 0 0x10000>;
319 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
320 0 320 IRQ_TYPE_LEVEL_HIGH
321 0 321 IRQ_TYPE_LEVEL_HIGH
322 0 322 IRQ_TYPE_LEVEL_HIGH
323 0 323 IRQ_TYPE_LEVEL_HIGH
324 0 324 IRQ_TYPE_LEVEL_HIGH
325 0 325 IRQ_TYPE_LEVEL_HIGH
326 0 326 IRQ_TYPE_LEVEL_HIGH
327 0 327 IRQ_TYPE_LEVEL_HIGH
328 0 328 IRQ_TYPE_LEVEL_HIGH
329 0 329 IRQ_TYPE_LEVEL_HIGH
330 0 330 IRQ_TYPE_LEVEL_HIGH
331 0 331 IRQ_TYPE_LEVEL_HIGH
332 0 332 IRQ_TYPE_LEVEL_HIGH>;
333 interrupt-names = "error",
334 "ch0", "ch1", "ch2", "ch3",
335 "ch4", "ch5", "ch6", "ch7",
336 "ch8", "ch9", "ch10", "ch11",
338 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
344 audma1: dma-controller@ec720000 {
345 compatible = "renesas,rcar-dmac";
346 reg = <0 0xec720000 0 0x10000>;
347 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
348 0 333 IRQ_TYPE_LEVEL_HIGH
349 0 334 IRQ_TYPE_LEVEL_HIGH
350 0 335 IRQ_TYPE_LEVEL_HIGH
351 0 336 IRQ_TYPE_LEVEL_HIGH
352 0 337 IRQ_TYPE_LEVEL_HIGH
353 0 338 IRQ_TYPE_LEVEL_HIGH
354 0 339 IRQ_TYPE_LEVEL_HIGH
355 0 340 IRQ_TYPE_LEVEL_HIGH
356 0 341 IRQ_TYPE_LEVEL_HIGH
357 0 342 IRQ_TYPE_LEVEL_HIGH
358 0 343 IRQ_TYPE_LEVEL_HIGH
359 0 344 IRQ_TYPE_LEVEL_HIGH
360 0 345 IRQ_TYPE_LEVEL_HIGH>;
361 interrupt-names = "error",
362 "ch0", "ch1", "ch2", "ch3",
363 "ch4", "ch5", "ch6", "ch7",
364 "ch8", "ch9", "ch10", "ch11",
366 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
372 audmapp: dma-controller@ec740000 {
373 compatible = "renesas,rcar-audmapp";
376 reg = <0 0xec740000 0 0x200>;
380 #address-cells = <1>;
382 compatible = "renesas,i2c-r8a7790";
383 reg = <0 0xe6508000 0 0x40>;
384 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
390 #address-cells = <1>;
392 compatible = "renesas,i2c-r8a7790";
393 reg = <0 0xe6518000 0 0x40>;
394 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
400 #address-cells = <1>;
402 compatible = "renesas,i2c-r8a7790";
403 reg = <0 0xe6530000 0 0x40>;
404 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
410 #address-cells = <1>;
412 compatible = "renesas,i2c-r8a7790";
413 reg = <0 0xe6540000 0 0x40>;
414 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
420 #address-cells = <1>;
422 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
423 reg = <0 0xe6500000 0 0x425>;
424 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
426 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
427 dma-names = "tx", "rx";
432 #address-cells = <1>;
434 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
435 reg = <0 0xe6510000 0 0x425>;
436 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
438 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
439 dma-names = "tx", "rx";
444 #address-cells = <1>;
446 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
447 reg = <0 0xe6520000 0 0x425>;
448 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
450 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
451 dma-names = "tx", "rx";
456 #address-cells = <1>;
458 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
459 reg = <0 0xe60b0000 0 0x425>;
460 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
462 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
463 dma-names = "tx", "rx";
467 mmcif0: mmc@ee200000 {
468 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
469 reg = <0 0xee200000 0 0x80>;
470 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
472 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
473 dma-names = "tx", "rx";
478 mmcif1: mmc@ee220000 {
479 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
480 reg = <0 0xee220000 0 0x80>;
481 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
483 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
484 dma-names = "tx", "rx";
490 compatible = "renesas,pfc-r8a7790";
491 reg = <0 0xe6060000 0 0x250>;
495 compatible = "renesas,sdhi-r8a7790";
496 reg = <0 0xee100000 0 0x200>;
497 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
503 compatible = "renesas,sdhi-r8a7790";
504 reg = <0 0xee120000 0 0x200>;
505 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
511 compatible = "renesas,sdhi-r8a7790";
512 reg = <0 0xee140000 0 0x100>;
513 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
519 compatible = "renesas,sdhi-r8a7790";
520 reg = <0 0xee160000 0 0x100>;
521 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
526 scifa0: serial@e6c40000 {
527 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
528 reg = <0 0xe6c40000 0 64>;
529 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
531 clock-names = "sci_ick";
535 scifa1: serial@e6c50000 {
536 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
537 reg = <0 0xe6c50000 0 64>;
538 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
540 clock-names = "sci_ick";
544 scifa2: serial@e6c60000 {
545 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
546 reg = <0 0xe6c60000 0 64>;
547 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
549 clock-names = "sci_ick";
553 scifb0: serial@e6c20000 {
554 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
555 reg = <0 0xe6c20000 0 64>;
556 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
558 clock-names = "sci_ick";
562 scifb1: serial@e6c30000 {
563 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
564 reg = <0 0xe6c30000 0 64>;
565 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
567 clock-names = "sci_ick";
571 scifb2: serial@e6ce0000 {
572 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
573 reg = <0 0xe6ce0000 0 64>;
574 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
576 clock-names = "sci_ick";
580 scif0: serial@e6e60000 {
581 compatible = "renesas,scif-r8a7790", "renesas,scif";
582 reg = <0 0xe6e60000 0 64>;
583 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
585 clock-names = "sci_ick";
589 scif1: serial@e6e68000 {
590 compatible = "renesas,scif-r8a7790", "renesas,scif";
591 reg = <0 0xe6e68000 0 64>;
592 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
594 clock-names = "sci_ick";
598 hscif0: serial@e62c0000 {
599 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
600 reg = <0 0xe62c0000 0 96>;
601 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
603 clock-names = "sci_ick";
607 hscif1: serial@e62c8000 {
608 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
609 reg = <0 0xe62c8000 0 96>;
610 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
612 clock-names = "sci_ick";
616 ether: ethernet@ee700000 {
617 compatible = "renesas,ether-r8a7790";
618 reg = <0 0xee700000 0 0x400>;
619 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
622 #address-cells = <1>;
627 sata0: sata@ee300000 {
628 compatible = "renesas,sata-r8a7790";
629 reg = <0 0xee300000 0 0x2000>;
630 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
635 sata1: sata@ee500000 {
636 compatible = "renesas,sata-r8a7790";
637 reg = <0 0xee500000 0 0x2000>;
638 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
643 hsusb: usb@e6590000 {
644 compatible = "renesas,usbhs-r8a7790";
645 reg = <0 0xe6590000 0 0x100>;
646 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
648 renesas,buswait = <4>;
654 usbphy: usb-phy@e6590100 {
655 compatible = "renesas,usb-phy-r8a7790";
656 reg = <0 0xe6590100 0 0x100>;
657 #address-cells = <1>;
659 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
660 clock-names = "usbhs";
663 usb0: usb-channel@0 {
667 usb2: usb-channel@2 {
673 vin0: video@e6ef0000 {
674 compatible = "renesas,vin-r8a7790";
675 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
676 reg = <0 0xe6ef0000 0 0x1000>;
677 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
681 vin1: video@e6ef1000 {
682 compatible = "renesas,vin-r8a7790";
683 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
684 reg = <0 0xe6ef1000 0 0x1000>;
685 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
689 vin2: video@e6ef2000 {
690 compatible = "renesas,vin-r8a7790";
691 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
692 reg = <0 0xe6ef2000 0 0x1000>;
693 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
697 vin3: video@e6ef3000 {
698 compatible = "renesas,vin-r8a7790";
699 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
700 reg = <0 0xe6ef3000 0 0x1000>;
701 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
706 compatible = "renesas,vsp1";
707 reg = <0 0xfe920000 0 0x8000>;
708 interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
718 compatible = "renesas,vsp1";
719 reg = <0 0xfe928000 0 0x8000>;
720 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
731 compatible = "renesas,vsp1";
732 reg = <0 0xfe930000 0 0x8000>;
733 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
744 compatible = "renesas,vsp1";
745 reg = <0 0xfe938000 0 0x8000>;
746 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
756 du: display@feb00000 {
757 compatible = "renesas,du-r8a7790";
758 reg = <0 0xfeb00000 0 0x70000>,
759 <0 0xfeb90000 0 0x1c>,
760 <0 0xfeb94000 0 0x1c>;
761 reg-names = "du", "lvds.0", "lvds.1";
762 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
763 <0 268 IRQ_TYPE_LEVEL_HIGH>,
764 <0 269 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
766 <&mstp7_clks R8A7790_CLK_DU1>,
767 <&mstp7_clks R8A7790_CLK_DU2>,
768 <&mstp7_clks R8A7790_CLK_LVDS0>,
769 <&mstp7_clks R8A7790_CLK_LVDS1>;
770 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
774 #address-cells = <1>;
779 du_out_rgb: endpoint {
784 du_out_lvds0: endpoint {
789 du_out_lvds1: endpoint {
796 #address-cells = <2>;
800 /* External root clock */
801 extal_clk: extal_clk {
802 compatible = "fixed-clock";
804 /* This value must be overriden by the board. */
805 clock-frequency = <0>;
806 clock-output-names = "extal";
809 /* External PCIe clock - can be overridden by the board */
810 pcie_bus_clk: pcie_bus_clk {
811 compatible = "fixed-clock";
813 clock-frequency = <100000000>;
814 clock-output-names = "pcie_bus";
819 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
820 * default. Boards that provide audio clocks should override them.
822 audio_clk_a: audio_clk_a {
823 compatible = "fixed-clock";
825 clock-frequency = <0>;
826 clock-output-names = "audio_clk_a";
828 audio_clk_b: audio_clk_b {
829 compatible = "fixed-clock";
831 clock-frequency = <0>;
832 clock-output-names = "audio_clk_b";
834 audio_clk_c: audio_clk_c {
835 compatible = "fixed-clock";
837 clock-frequency = <0>;
838 clock-output-names = "audio_clk_c";
841 /* Special CPG clocks */
842 cpg_clocks: cpg_clocks@e6150000 {
843 compatible = "renesas,r8a7790-cpg-clocks",
844 "renesas,rcar-gen2-cpg-clocks";
845 reg = <0 0xe6150000 0 0x1000>;
846 clocks = <&extal_clk>;
848 clock-output-names = "main", "pll0", "pll1", "pll3",
849 "lb", "qspi", "sdh", "sd0", "sd1",
853 /* Variable factor clocks */
854 sd2_clk: sd2_clk@e6150078 {
855 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
856 reg = <0 0xe6150078 0 4>;
857 clocks = <&pll1_div2_clk>;
859 clock-output-names = "sd2";
861 sd3_clk: sd3_clk@e615026c {
862 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
863 reg = <0 0xe615026c 0 4>;
864 clocks = <&pll1_div2_clk>;
866 clock-output-names = "sd3";
868 mmc0_clk: mmc0_clk@e6150240 {
869 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
870 reg = <0 0xe6150240 0 4>;
871 clocks = <&pll1_div2_clk>;
873 clock-output-names = "mmc0";
875 mmc1_clk: mmc1_clk@e6150244 {
876 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
877 reg = <0 0xe6150244 0 4>;
878 clocks = <&pll1_div2_clk>;
880 clock-output-names = "mmc1";
882 ssp_clk: ssp_clk@e6150248 {
883 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
884 reg = <0 0xe6150248 0 4>;
885 clocks = <&pll1_div2_clk>;
887 clock-output-names = "ssp";
889 ssprs_clk: ssprs_clk@e615024c {
890 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
891 reg = <0 0xe615024c 0 4>;
892 clocks = <&pll1_div2_clk>;
894 clock-output-names = "ssprs";
897 /* Fixed factor clocks */
898 pll1_div2_clk: pll1_div2_clk {
899 compatible = "fixed-factor-clock";
900 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
904 clock-output-names = "pll1_div2";
907 compatible = "fixed-factor-clock";
908 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
912 clock-output-names = "z2";
915 compatible = "fixed-factor-clock";
916 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
920 clock-output-names = "zg";
923 compatible = "fixed-factor-clock";
924 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
928 clock-output-names = "zx";
931 compatible = "fixed-factor-clock";
932 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
936 clock-output-names = "zs";
939 compatible = "fixed-factor-clock";
940 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
944 clock-output-names = "hp";
947 compatible = "fixed-factor-clock";
948 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
952 clock-output-names = "i";
955 compatible = "fixed-factor-clock";
956 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
960 clock-output-names = "b";
963 compatible = "fixed-factor-clock";
964 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
968 clock-output-names = "p";
971 compatible = "fixed-factor-clock";
972 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
976 clock-output-names = "cl";
979 compatible = "fixed-factor-clock";
980 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
984 clock-output-names = "m2";
987 compatible = "fixed-factor-clock";
988 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
992 clock-output-names = "imp";
995 compatible = "fixed-factor-clock";
996 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
998 clock-div = <(48 * 1024)>;
1000 clock-output-names = "rclk";
1002 oscclk_clk: oscclk_clk {
1003 compatible = "fixed-factor-clock";
1004 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1006 clock-div = <(12 * 1024)>;
1008 clock-output-names = "oscclk";
1011 compatible = "fixed-factor-clock";
1012 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1016 clock-output-names = "zb3";
1018 zb3d2_clk: zb3d2_clk {
1019 compatible = "fixed-factor-clock";
1020 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1024 clock-output-names = "zb3d2";
1027 compatible = "fixed-factor-clock";
1028 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1032 clock-output-names = "ddr";
1035 compatible = "fixed-factor-clock";
1036 clocks = <&pll1_div2_clk>;
1040 clock-output-names = "mp";
1043 compatible = "fixed-factor-clock";
1044 clocks = <&extal_clk>;
1048 clock-output-names = "cp";
1052 mstp0_clks: mstp0_clks@e6150130 {
1053 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1054 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1057 renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
1058 clock-output-names = "msiof0";
1060 mstp1_clks: mstp1_clks@e6150134 {
1061 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1062 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1063 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1064 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1065 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1066 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1068 renesas,clock-indices = <
1069 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1070 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1071 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1072 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1073 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1074 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1075 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1077 clock-output-names =
1078 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1079 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1080 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1081 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1083 mstp2_clks: mstp2_clks@e6150138 {
1084 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1085 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1086 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1087 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1090 renesas,clock-indices = <
1091 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1092 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1093 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1094 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1096 clock-output-names =
1097 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1098 "scifb1", "msiof1", "msiof3", "scifb2",
1099 "sys-dmac1", "sys-dmac0";
1101 mstp3_clks: mstp3_clks@e615013c {
1102 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1103 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1104 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1105 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1106 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1107 <&hp_clk>, <&hp_clk>;
1109 renesas,clock-indices = <
1110 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1111 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1112 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1113 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1115 clock-output-names =
1116 "iic2", "tpu0", "mmcif1", "sdhi3",
1117 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1118 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1119 "usbdmac0", "usbdmac1";
1121 mstp5_clks: mstp5_clks@e6150144 {
1122 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1123 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1124 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
1126 renesas,clock-indices = <R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1127 R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
1128 clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
1130 mstp7_clks: mstp7_clks@e615014c {
1131 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1132 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1133 clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1134 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1137 renesas,clock-indices = <
1138 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1139 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1140 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1141 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1143 clock-output-names =
1144 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1145 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1147 mstp8_clks: mstp8_clks@e6150990 {
1148 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1149 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1150 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
1151 <&zs_clk>, <&zs_clk>;
1153 renesas,clock-indices = <
1154 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
1155 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
1158 clock-output-names =
1159 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
1161 mstp9_clks: mstp9_clks@e6150994 {
1162 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1163 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1164 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1165 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1166 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1167 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1169 renesas,clock-indices = <
1170 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1171 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1172 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1173 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1175 clock-output-names =
1176 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1177 "rcan1", "rcan0", "qspi_mod", "iic3",
1178 "i2c3", "i2c2", "i2c1", "i2c0";
1180 mstp10_clks: mstp10_clks@e6150998 {
1181 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1182 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1184 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1185 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1187 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1188 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1189 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1190 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1191 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1192 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1197 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1198 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1200 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1201 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1202 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1204 clock-output-names =
1206 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1207 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1209 "scu-dvc1", "scu-dvc0",
1210 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1211 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1215 qspi: spi@e6b10000 {
1216 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1217 reg = <0 0xe6b10000 0 0x2c>;
1218 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1220 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1221 dma-names = "tx", "rx";
1223 #address-cells = <1>;
1225 status = "disabled";
1228 msiof0: spi@e6e20000 {
1229 compatible = "renesas,msiof-r8a7790";
1230 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
1231 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1232 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1233 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1234 dma-names = "tx", "rx";
1235 #address-cells = <1>;
1237 status = "disabled";
1240 msiof1: spi@e6e10000 {
1241 compatible = "renesas,msiof-r8a7790";
1242 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
1243 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1244 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1245 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1246 dma-names = "tx", "rx";
1247 #address-cells = <1>;
1249 status = "disabled";
1252 msiof2: spi@e6e00000 {
1253 compatible = "renesas,msiof-r8a7790";
1254 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
1255 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1257 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1258 dma-names = "tx", "rx";
1259 #address-cells = <1>;
1261 status = "disabled";
1264 msiof3: spi@e6c90000 {
1265 compatible = "renesas,msiof-r8a7790";
1266 reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
1267 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
1268 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1269 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1270 dma-names = "tx", "rx";
1271 #address-cells = <1>;
1273 status = "disabled";
1276 xhci: usb@ee000000 {
1277 compatible = "renesas,xhci-r8a7790";
1278 reg = <0 0xee000000 0 0xc00>;
1279 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1280 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1283 status = "disabled";
1286 pci0: pci@ee090000 {
1287 compatible = "renesas,pci-r8a7790";
1288 device_type = "pci";
1289 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1290 reg = <0 0xee090000 0 0xc00>,
1291 <0 0xee080000 0 0x1100>;
1292 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1293 status = "disabled";
1296 #address-cells = <3>;
1298 #interrupt-cells = <1>;
1299 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1300 interrupt-map-mask = <0xff00 0 0 0x7>;
1301 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1302 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1303 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1306 reg = <0x800 0 0 0 0>;
1307 device_type = "pci";
1313 reg = <0x1000 0 0 0 0>;
1314 device_type = "pci";
1320 pci1: pci@ee0b0000 {
1321 compatible = "renesas,pci-r8a7790";
1322 device_type = "pci";
1323 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1324 reg = <0 0xee0b0000 0 0xc00>,
1325 <0 0xee0a0000 0 0x1100>;
1326 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
1327 status = "disabled";
1330 #address-cells = <3>;
1332 #interrupt-cells = <1>;
1333 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1334 interrupt-map-mask = <0xff00 0 0 0x7>;
1335 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1336 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1337 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
1340 pci2: pci@ee0d0000 {
1341 compatible = "renesas,pci-r8a7790";
1342 device_type = "pci";
1343 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1344 reg = <0 0xee0d0000 0 0xc00>,
1345 <0 0xee0c0000 0 0x1100>;
1346 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1347 status = "disabled";
1350 #address-cells = <3>;
1352 #interrupt-cells = <1>;
1353 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1354 interrupt-map-mask = <0xff00 0 0 0x7>;
1355 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1356 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1357 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1360 reg = <0x800 0 0 0 0>;
1361 device_type = "pci";
1367 reg = <0x1000 0 0 0 0>;
1368 device_type = "pci";
1374 pciec: pcie@fe000000 {
1375 compatible = "renesas,pcie-r8a7790";
1376 reg = <0 0xfe000000 0 0x80000>;
1377 #address-cells = <3>;
1379 bus-range = <0x00 0xff>;
1380 device_type = "pci";
1381 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1382 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1383 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1384 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1385 /* Map all possible DDR as inbound ranges */
1386 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1387 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1388 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1389 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1390 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1391 #interrupt-cells = <1>;
1392 interrupt-map-mask = <0 0 0 0>;
1393 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1394 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1395 clock-names = "pcie", "pcie_bus";
1396 status = "disabled";
1399 rcar_sound: rcar_sound@ec500000 {
1400 #sound-dai-cells = <1>;
1401 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1402 reg = <0 0xec500000 0 0x1000>, /* SCU */
1403 <0 0xec5a0000 0 0x100>, /* ADG */
1404 <0 0xec540000 0 0x1000>, /* SSIU */
1405 <0 0xec541000 0 0x1280>; /* SSI */
1406 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1407 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1408 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1409 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1410 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1411 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1412 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1413 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1414 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1415 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1416 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1417 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1418 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1419 clock-names = "ssi-all",
1420 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1421 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1422 "src.9", "src.8", "src.7", "src.6", "src.5",
1423 "src.4", "src.3", "src.2", "src.1", "src.0",
1425 "clk_a", "clk_b", "clk_c", "clk_i";
1427 status = "disabled";
1448 ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1449 ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1450 ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1451 ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1452 ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1453 ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1454 ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1455 ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1456 ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1457 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };