arch/arm/boot/dts/r8a7793.dtsi

   1 /*
   2  * Device Tree Source for the r8a7793 SoC
   3  *
   4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7793-clock.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14
  15 / {
  16         compatible = "renesas,r8a7793";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a15";
  28                         reg = <0>;
  29                         clock-frequency = <1500000000>;
  30                         voltage-tolerance = <1>; /* 1% */
  31                         clocks = <&cpg_clocks R8A7793_CLK_Z>;
  32                         clock-latency = <300000>; /* 300 us */
  33
  34                         /* kHz - uV - OPPs unknown yet */
  35                         operating-points = <1500000 1000000>,
  36                                            <1312500 1000000>,
  37                                            <1125000 1000000>,
  38                                            < 937500 1000000>,
  39                                            < 750000 1000000>,
  40                                            < 375000 1000000>;
  41                 };
  42         };
  43
  44         gic: interrupt-controller@f1001000 {
  45                 compatible = "arm,gic-400";
  46                 #interrupt-cells = <3>;
  47                 #address-cells = <0>;
  48                 interrupt-controller;
  49                 reg = <0 0xf1001000 0 0x1000>,
  50                         <0 0xf1002000 0 0x1000>,
  51                         <0 0xf1004000 0 0x2000>,
  52                         <0 0xf1006000 0 0x2000>;
  53                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  54         };
  55
  56         timer {
  57                 compatible = "arm,armv7-timer";
  58                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  59                              <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  60                              <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  61                              <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  62         };
  63
  64         cmt0: timer@ffca0000 {
  65                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
  66                 reg = <0 0xffca0000 0 0x1004>;
  67                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
  68                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
  69                 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
  70                 clock-names = "fck";
  71
  72                 renesas,channels-mask = <0x60>;
  73
  74                 status = "disabled";
  75         };
  76
  77         cmt1: timer@e6130000 {
  78                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
  79                 reg = <0 0xe6130000 0 0x1004>;
  80                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
  81                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
  82                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
  83                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
  84                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
  85                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
  86                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
  87                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
  88                 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
  89                 clock-names = "fck";
  90
  91                 renesas,channels-mask = <0xff>;
  92
  93                 status = "disabled";
  94         };
  95
  96         irqc0: interrupt-controller@e61c0000 {
  97                 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
  98                 #interrupt-cells = <2>;
  99                 interrupt-controller;
 100                 reg = <0 0xe61c0000 0 0x200>;
 101                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 102                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 103                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 104                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 105                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 106                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 107                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 108                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 109                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 110                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 111                 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
 112         };
 113
 114         scif0: serial@e6e60000 {
 115                 compatible = "renesas,scif-r8a7793", "renesas,scif";
 116                 reg = <0 0xe6e60000 0 64>;
 117                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 118                 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
 119                 clock-names = "sci_ick";
 120                 status = "disabled";
 121         };
 122
 123         scif1: serial@e6e68000 {
 124                 compatible = "renesas,scif-r8a7793", "renesas,scif";
 125                 reg = <0 0xe6e68000 0 64>;
 126                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 127                 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
 128                 clock-names = "sci_ick";
 129                 status = "disabled";
 130         };
 131
 132         ether: ethernet@ee700000 {
 133                 compatible = "renesas,ether-r8a7793";
 134                 reg = <0 0xee700000 0 0x400>;
 135                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 136                 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
 137                 phy-mode = "rmii";
 138                 #address-cells = <1>;
 139                 #size-cells = <0>;
 140                 status = "disabled";
 141         };
 142
 143         clocks {
 144                 #address-cells = <2>;
 145                 #size-cells = <2>;
 146                 ranges;
 147
 148                 /* External root clock */
 149                 extal_clk: extal_clk {
 150                         compatible = "fixed-clock";
 151                         #clock-cells = <0>;
 152                         /* This value must be overridden by the board. */
 153                         clock-frequency = <0>;
 154                         clock-output-names = "extal";
 155                 };
 156
 157                 /* Special CPG clocks */
 158                 cpg_clocks: cpg_clocks@e6150000 {
 159                         compatible = "renesas,r8a7793-cpg-clocks",
 160                                      "renesas,rcar-gen2-cpg-clocks";
 161                         reg = <0 0xe6150000 0 0x1000>;
 162                         clocks = <&extal_clk>;
 163                         #clock-cells = <1>;
 164                         clock-output-names = "main", "pll0", "pll1", "pll3",
 165                                              "lb", "qspi", "sdh", "sd0", "z",
 166                                              "rcan", "adsp";
 167                 };
 168
 169                 /* Variable factor clocks */
 170                 sd2_clk: sd2_clk@e6150078 {
 171                         compatible = "renesas,r8a7793-div6-clock",
 172                                      "renesas,cpg-div6-clock";
 173                         reg = <0 0xe6150078 0 4>;
 174                         clocks = <&pll1_div2_clk>;
 175                         #clock-cells = <0>;
 176                         clock-output-names = "sd2";
 177                 };
 178                 sd3_clk: sd3_clk@e615026c {
 179                         compatible = "renesas,r8a7793-div6-clock",
 180                                      "renesas,cpg-div6-clock";
 181                         reg = <0 0xe615026c 0 4>;
 182                         clocks = <&pll1_div2_clk>;
 183                         #clock-cells = <0>;
 184                         clock-output-names = "sd3";
 185                 };
 186                 mmc0_clk: mmc0_clk@e6150240 {
 187                         compatible = "renesas,r8a7793-div6-clock",
 188                                      "renesas,cpg-div6-clock";
 189                         reg = <0 0xe6150240 0 4>;
 190                         clocks = <&pll1_div2_clk>;
 191                         #clock-cells = <0>;
 192                         clock-output-names = "mmc0";
 193                 };
 194
 195                 /* Fixed factor clocks */
 196                 pll1_div2_clk: pll1_div2_clk {
 197                         compatible = "fixed-factor-clock";
 198                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 199                         #clock-cells = <0>;
 200                         clock-div = <2>;
 201                         clock-mult = <1>;
 202                         clock-output-names = "pll1_div2";
 203                 };
 204                 zg_clk: zg_clk {
 205                         compatible = "fixed-factor-clock";
 206                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 207                         #clock-cells = <0>;
 208                         clock-div = <5>;
 209                         clock-mult = <1>;
 210                         clock-output-names = "zg";
 211                 };
 212                 zx_clk: zx_clk {
 213                         compatible = "fixed-factor-clock";
 214                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 215                         #clock-cells = <0>;
 216                         clock-div = <3>;
 217                         clock-mult = <1>;
 218                         clock-output-names = "zx";
 219                 };
 220                 zs_clk: zs_clk {
 221                         compatible = "fixed-factor-clock";
 222                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 223                         #clock-cells = <0>;
 224                         clock-div = <6>;
 225                         clock-mult = <1>;
 226                         clock-output-names = "zs";
 227                 };
 228                 hp_clk: hp_clk {
 229                         compatible = "fixed-factor-clock";
 230                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 231                         #clock-cells = <0>;
 232                         clock-div = <12>;
 233                         clock-mult = <1>;
 234                         clock-output-names = "hp";
 235                 };
 236                 p_clk: p_clk {
 237                         compatible = "fixed-factor-clock";
 238                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 239                         #clock-cells = <0>;
 240                         clock-div = <24>;
 241                         clock-mult = <1>;
 242                         clock-output-names = "p";
 243                 };
 244                 rclk_clk: rclk_clk {
 245                         compatible = "fixed-factor-clock";
 246                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 247                         #clock-cells = <0>;
 248                         clock-div = <(48 * 1024)>;
 249                         clock-mult = <1>;
 250                         clock-output-names = "rclk";
 251                 };
 252                 mp_clk: mp_clk {
 253                         compatible = "fixed-factor-clock";
 254                         clocks = <&pll1_div2_clk>;
 255                         #clock-cells = <0>;
 256                         clock-div = <15>;
 257                         clock-mult = <1>;
 258                         clock-output-names = "mp";
 259                 };
 260                 cp_clk: cp_clk {
 261                         compatible = "fixed-factor-clock";
 262                         clocks = <&extal_clk>;
 263                         #clock-cells = <0>;
 264                         clock-div = <2>;
 265                         clock-mult = <1>;
 266                         clock-output-names = "cp";
 267                 };
 268
 269                 /* Gate clocks */
 270                 mstp1_clks: mstp1_clks@e6150134 {
 271                         compatible = "renesas,r8a7793-mstp-clocks",
 272                                      "renesas,cpg-mstp-clocks";
 273                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 274                         clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 275                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
 276                                  <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
 277                                  <&zs_clk>, <&zs_clk>, <&zs_clk>;
 278                         #clock-cells = <1>;
 279                         clock-indices = <
 280                                 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
 281                                 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
 282                                 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
 283                                 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
 284                                 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
 285                                 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
 286                                 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
 287                                 R8A7793_CLK_VSP1_S
 288                         >;
 289                         clock-output-names =
 290                                 "vcp0", "vpc0", "ssp_dev", "tmu1",
 291                                 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
 292                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 293                                 "vsp1-du0", "vsps";
 294                 };
 295                 mstp3_clks: mstp3_clks@e615013c {
 296                         compatible = "renesas,r8a7793-mstp-clocks",
 297                                      "renesas,cpg-mstp-clocks";
 298                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 299                         clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
 300                                  <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
 301                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
 302                                  <&rclk_clk>, <&hp_clk>, <&hp_clk>;
 303                         #clock-cells = <1>;
 304                         clock-indices = <
 305                                 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
 306                                 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
 307                                 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
 308                                 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
 309                                 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
 310                                 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
 311                         >;
 312                         clock-output-names =
 313                                 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
 314                                 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
 315                                 "usbdmac0", "usbdmac1";
 316                 };
 317                 mstp4_clks: mstp4_clks@e6150140 {
 318                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
 319                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
 320                         clocks = <&cp_clk>;
 321                         #clock-cells = <1>;
 322                         clock-indices = <R8A7793_CLK_IRQC>;
 323                         clock-output-names = "irqc";
 324                 };
 325                 mstp7_clks: mstp7_clks@e615014c {
 326                         compatible = "renesas,r8a7793-mstp-clocks",
 327                                      "renesas,cpg-mstp-clocks";
 328                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 329                         clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>,
 330                                  <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 331                                  <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
 332                                  <&zx_clk>, <&zx_clk>;
 333                         #clock-cells = <1>;
 334                         clock-indices = <
 335                                 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
 336                                 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
 337                                 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
 338                                 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
 339                                 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
 340                                 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
 341                                 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
 342                         >;
 343                         clock-output-names =
 344                                 "ehci", "hsusb", "hscif2", "scif5", "scif4",
 345                                 "hscif1", "hscif0", "scif3", "scif2",
 346                                 "scif1", "scif0", "du1", "du0", "lvds0";
 347                 };
 348                 mstp8_clks: mstp8_clks@e6150990 {
 349                         compatible = "renesas,r8a7793-mstp-clocks",
 350                                      "renesas,cpg-mstp-clocks";
 351                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 352                         clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
 353                                  <&p_clk>, <&zs_clk>, <&zs_clk>;
 354                         #clock-cells = <1>;
 355                         clock-indices = <
 356                                 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
 357                                 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
 358                                 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
 359                                 R8A7793_CLK_SATA0
 360                         >;
 361                         clock-output-names =
 362                                 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
 363                                 "sata1", "sata0";
 364                 };
 365         };
 366
 367 };