2 * Copyright (C) 2014 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <dt-bindings/clock/rockchip,rk3036.h>
19 compatible = "rockchip,rk-clocks";
22 ranges = <0x0 0x20000000 0x1f0>;
25 compatible = "rockchip,rk-fixed-rate-cons";
28 compatible = "rockchip,rk-fixed-clock";
29 clock-output-names = "xin24m";
30 clock-frequency = <24000000>;
35 compatible = "rockchip,rk-fixed-clock";
37 clock-output-names = "xin12m";
38 clock-frequency = <12000000>;
42 rmii_clkin: rmii_clkin {
43 compatible = "rockchip,rk-fixed-clock";
44 clock-output-names = "rmii_clkin";
45 clock-frequency = <0>;
50 compatible = "rockchip,rk-fixed-clock";
51 clock-output-names = "usb_480m";
52 clock-frequency = <480000000>;
56 i2s_clkin: i2s_clkin {
57 compatible = "rockchip,rk-fixed-clock";
58 clock-output-names = "i2s_clkin";
59 clock-frequency = <0>;
64 compatible = "rockchip,rk-fixed-clock";
65 clock-output-names = "jtag_tck";
66 clock-frequency = <0>;
71 compatible = "rockchip,rk-fixed-clock";
72 clock-output-names = "dummy";
73 clock-frequency = <0>;
77 dummy_cpll: dummy_cpll {
78 compatible = "rockchip,rk-fixed-clock";
79 clock-output-names = "dummy_cpll";
80 clock-frequency = <0>;
87 compatible = "rockchip,rk-fixed-factor-cons";
89 otgphy0_12m: otgphy0_12m {
90 compatible = "rockchip,rk-fixed-factor-clock";
91 clocks = <&clk_gates1 5>;
92 clock-output-names = "otgphy0_12m";
98 hclk_vcodec: hclk_vcodec {
99 compatible = "rockchip,rk-fixed-factor-clock";
100 clocks = <&aclk_vcodec_pre>;
101 clock-output-names = "hclk_vcodec";
110 compatible = "rockchip,rk-clock-regs";
111 #address-cells = <1>;
113 reg = <0x0000 0x01f0>;
116 /* PLL control regs */
118 compatible = "rockchip,rk-pll-cons";
119 #address-cells = <1>;
123 clk_apll: pll-clk@0000 {
124 compatible = "rockchip,rk3188-pll-clk";
126 mode-reg = <0x0040 0>;
127 status-reg = <0x0004 10>;
129 clock-output-names = "clk_apll";
130 rockchip,pll-type = <CLK_PLL_3036_APLL>;
134 clk_dpll: pll-clk@0010 {
135 compatible = "rockchip,rk3188-pll-clk";
137 mode-reg = <0x0040 4>;
138 status-reg = <0x0014 10>;
140 clock-output-names = "clk_dpll";
141 rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
145 clk_gpll: pll-clk@0030 {
146 compatible = "rockchip,rk3188-pll-clk";
148 mode-reg = <0x0040 12>;
149 status-reg = <0x0034 10>;
151 clock-output-names = "clk_gpll";
152 rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
154 #clock-init-cells = <1>;
159 /* Select control regs */
161 compatible = "rockchip,rk-sel-cons";
162 #address-cells = <1>;
166 clk_sel_con0: sel-con@0044 {
167 compatible = "rockchip,rk3188-selcon";
169 #address-cells = <1>;
172 clk_core_div: clk_core_div {
173 compatible = "rockchip,rk3188-div-con";
174 rockchip,bits = <0 5>;
175 clocks = <&clk_core>;
176 clock-output-names = "clk_core";
177 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
179 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
180 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
181 CLK_SET_RATE_NO_REPARENT)>;
184 /* reg[6:5]: reserved */
186 clk_core: clk_core_mux {
187 compatible = "rockchip,rk3188-mux-con";
188 rockchip,bits = <7 1>;
189 clocks = <&clk_apll>, <&clk_gates0 6>;
190 clock-output-names = "clk_core";
192 #clock-init-cells = <1>;
195 aclk_cpu_pre_div: aclk_cpu_pre_div {
196 compatible = "rockchip,rk3188-div-con";
197 rockchip,bits = <8 5>;
198 clocks = <&aclk_cpu_pre>;
199 clock-output-names = "aclk_cpu_pre";
200 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
202 rockchip,clkops-idx =
203 <CLKOPS_RATE_MUX_DIV>;
204 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
207 /* reg[13]: reserved */
209 aclk_cpu_pre: aclk_cpu_pre_mux {
210 compatible = "rockchip,rk3188-mux-con";
211 rockchip,bits = <14 2>;
212 clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>;
213 clock-output-names = "aclk_cpu_pre";
215 #clock-init-cells = <1>;
220 clk_sel_con1: sel-con@0048 {
221 compatible = "rockchip,rk3188-selcon";
223 #address-cells = <1>;
226 pclk_dbg_div: pclk_dbg_div {
227 compatible = "rockchip,rk3188-div-con";
228 rockchip,bits = <0 4>;
229 clocks = <&clk_core>;
230 clock-output-names = "pclk_dbg";
231 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
233 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
236 aclk_core_pre: aclk_core_pre_div {
237 compatible = "rockchip,rk3188-div-con";
238 rockchip,bits = <4 3>;
239 clocks = <&clk_core>;
240 clock-output-names = "aclk_core_pre";
241 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
243 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
246 /* reg[7]: reserved */
248 hclk_cpu_pre: hclk_cpu_pre_div {
249 compatible = "rockchip,rk3188-div-con";
250 rockchip,bits = <8 2>;
251 clocks = <&aclk_cpu_pre>;
252 clock-output-names = "hclk_cpu_pre";
253 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
255 #clock-init-cells = <1>;
258 /* reg[11:10]: reserved */
260 pclk_cpu_pre: pclk_cpu_pre_div {
261 compatible = "rockchip,rk3188-div-con";
262 rockchip,bits = <12 3>;
263 clocks = <&aclk_cpu_pre>;
264 clock-output-names = "pclk_cpu_pre";
265 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
267 #clock-init-cells = <1>;
270 /* reg[15]: reserved */
273 clk_sel_con2: sel-con@004c {
274 compatible = "rockchip,rk3188-selcon";
276 #address-cells = <1>;
279 /* reg[3:0]: reserved */
281 clk_timer0: clk_timer0_mux {
282 compatible = "rockchip,rk3188-mux-con";
283 rockchip,bits = <4 1>;
284 clocks = <&xin24m>, <&aclk_peri_pre>;
285 clock-output-names = "clk_timer0";
287 #clock-init-cells = <1>;
290 clk_timer1: clk_timer1_mux {
291 compatible = "rockchip,rk3188-mux-con";
292 rockchip,bits = <5 1>;
293 clocks = <&xin24m>, <&aclk_peri_pre>;
294 clock-output-names = "clk_timer1";
296 #clock-init-cells = <1>;
299 clk_timer2: clk_timer2_mux {
300 compatible = "rockchip,rk3188-mux-con";
301 rockchip,bits = <6 1>;
302 clocks = <&xin24m>, <&aclk_peri_pre>;
303 clock-output-names = "clk_timer2";
305 #clock-init-cells = <1>;
308 clk_timer3: clk_timer3_mux {
309 compatible = "rockchip,rk3188-mux-con";
310 rockchip,bits = <7 1>;
311 clocks = <&xin24m>, <&aclk_peri_pre>;
312 clock-output-names = "clk_timer3";
314 #clock-init-cells = <1>;
317 /* reg[15:8]: reserved */
320 clk_sel_con3: sel-con@0050 {
321 compatible = "rockchip,rk3188-selcon";
323 #address-cells = <1>;
326 clk_i2s_pll_div: clk_i2s_pll_div {
327 compatible = "rockchip,rk3188-div-con";
328 rockchip,bits = <0 7>;
329 clocks = <&clk_i2s_pll>;
330 clock-output-names = "clk_i2s_pll";
331 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
333 rockchip,clkops-idx =
334 <CLKOPS_RATE_MUX_DIV>;
335 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
338 /* reg[7]: reserved */
340 clk_i2s: clk_i2s_mux {
341 compatible = "rockchip,rk3188-mux-con";
342 rockchip,bits = <8 2>;
343 clocks = <&clk_i2s_pll_div>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
344 clock-output-names = "clk_i2s";
346 rockchip,clkops-idx =
347 <CLKOPS_RATE_RK3288_I2S>;
348 rockchip,flags = <CLK_SET_RATE_PARENT>;
351 /* reg[11:10]: reserved */
353 clk_i2s_out: i2s_outclk_mux {
354 compatible = "rockchip,rk3188-mux-con";
355 rockchip,bits = <12 1>;
356 clocks = <&xin12m>, <&clk_i2s>;
357 clock-output-names = "i2s_clkout";
361 /* reg[13]: reserved */
363 clk_i2s_pll: i2s_pll_mux {
364 compatible = "rockchip,rk3188-mux-con";
365 rockchip,bits = <14 2>;
366 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
367 clock-output-names = "clk_i2s_pll";
369 #clock-init-cells = <1>;
374 clk_sel_con5: sel-con@0058 {
375 compatible = "rockchip,rk3188-selcon";
377 #address-cells = <1>;
380 spdif_div: spdif_div {
381 compatible = "rockchip,rk3188-div-con";
382 rockchip,bits = <0 7>;
383 clocks = <&clk_spdif_pll>;
384 clock-output-names = "clk_spdif_pll";
385 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
387 rockchip,clkops-idx =
388 <CLKOPS_RATE_MUX_DIV>;
389 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
392 /* reg[7]: reserved */
394 clk_spdif: spdif_mux {
395 compatible = "rockchip,rk3188-mux-con";
396 rockchip,bits = <8 2>;
397 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
398 clock-output-names = "clk_spdif";
400 rockchip,clkops-idx =
401 <CLKOPS_RATE_RK3288_I2S>;
402 rockchip,flags = <CLK_SET_RATE_PARENT>;
405 clk_spdif_pll: spdif_pll_mux {
406 compatible = "rockchip,rk3188-mux-con";
407 rockchip,bits = <10 2>;
408 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
409 clock-output-names = "clk_spdif_pll";
411 #clock-init-cells = <1>;
414 /* reg[15:12]: reserved */
417 clk_sel_con7: sel-con@0060 {
418 compatible = "rockchip,rk3188-selcon";
420 #address-cells = <1>;
424 compatible = "rockchip,rk3188-frac-con";
425 clocks = <&clk_i2s_pll>;
426 clock-output-names = "i2s_frac";
427 /* numerator denominator */
428 rockchip,bits = <0 32>;
429 rockchip,clkops-idx =
435 clk_sel_con9: sel-con@0068 {
436 compatible = "rockchip,rk3188-selcon";
438 #address-cells = <1>;
441 spdif_frac: spdif_frac {
442 compatible = "rockchip,rk3188-frac-con";
443 clocks = <&spdif_div>;
444 clock-output-names = "spdif_frac";
445 /* numerator denominator */
446 rockchip,bits = <0 32>;
447 rockchip,clkops-idx =
453 clk_sel_con10: sel-con@006c {
454 compatible = "rockchip,rk3188-selcon";
456 #address-cells = <1>;
459 aclk_peri_pre_div: aclk_peri_pre_div {
460 compatible = "rockchip,rk3188-div-con";
461 rockchip,bits = <0 5>;
462 clocks = <&aclk_peri_pre>;
463 clock-output-names = "aclk_peri_pre";
464 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
466 rockchip,clkops-idx =
467 <CLKOPS_RATE_MUX_DIV>;
468 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
471 /* reg[7:5]: reserved */
473 hclk_peri_pre: hclk_peri_pre_div {
474 compatible = "rockchip,rk3188-div-con";
475 rockchip,bits = <8 2>;
476 clocks = <&aclk_peri_pre>;
477 clock-output-names = "hclk_peri_pre";
478 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
479 rockchip,div-relations =
484 #clock-init-cells = <1>;
487 /* reg[11:10]: reserved */
489 pclk_peri_pre: pclk_peri_div {
490 compatible = "rockchip,rk3188-div-con";
491 rockchip,bits = <12 2>;
492 clocks = <&aclk_peri_pre>;
493 clock-output-names = "pclk_peri_pre";
494 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
495 rockchip,div-relations =
501 #clock-init-cells = <1>;
504 aclk_peri_pre: aclk_peri_pre_mux {
505 compatible = "rockchip,rk3188-mux-con";
506 rockchip,bits = <14 2>;
507 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
508 clock-output-names = "aclk_peri_pre";
510 #clock-init-cells = <1>;
514 clk_sel_con11: sel-con@0070 {
515 compatible = "rockchip,rk3188-selcon";
517 #address-cells = <1>;
520 clk_sdmmc0_div: clk_sdmmc0_div {
521 compatible = "rockchip,rk3188-div-con";
522 rockchip,bits = <0 6>;
523 clocks = <&clk_sdmmc0>;
524 clock-output-names = "clk_sdmmc0";
525 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
527 rockchip,clkops-idx =
528 <CLKOPS_RATE_MUX_EVENDIV>;
531 /* reg[7]: reserved */
533 clk_sdio_div: clk_sdio_div {
534 compatible = "rockchip,rk3188-div-con";
535 rockchip,bits = <8 7>;
536 clocks = <&clk_sdio>;
537 clock-output-names = "clk_sdio";
538 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
540 rockchip,clkops-idx =
541 <CLKOPS_RATE_MUX_EVENDIV>;
544 /* reg[15]: reserved */
548 clk_sel_con12: sel-con@0074 {
549 compatible = "rockchip,rk3188-selcon";
551 #address-cells = <1>;
554 clk_emmc_div: clk_emmc_div {
555 compatible = "rockchip,rk3188-div-con";
556 rockchip,bits = <0 7>;
557 clocks = <&clk_emmc>;
558 clock-output-names = "clk_emmc";
559 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
561 rockchip,clkops-idx =
562 <CLKOPS_RATE_MUX_EVENDIV>;
565 /* reg[7]: reserved */
567 clk_sdmmc0: clk_sdmmc0_mux {
568 compatible = "rockchip,rk3188-mux-con";
569 rockchip,bits = <8 2>;
570 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
571 clock-output-names = "clk_sdmmc0";
575 clk_sdio: clk_sdio_mux {
576 compatible = "rockchip,rk3188-mux-con";
577 rockchip,bits = <10 2>;
578 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
579 clock-output-names = "clk_sdio";
583 clk_emmc: clk_emmc_mux {
584 compatible = "rockchip,rk3188-mux-con";
585 rockchip,bits = <12 2>;
586 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
587 clock-output-names = "clk_emmc";
591 /* reg[15:14]: reserved */
594 clk_sel_con13: sel-con@0078 {
595 compatible = "rockchip,rk3188-selcon";
597 #address-cells = <1>;
600 clk_uart0_div: clk_uart0_div {
601 compatible = "rockchip,rk3188-div-con";
602 rockchip,bits = <0 7>;
603 clocks = <&clk_uart_pll>;
604 clock-output-names = "clk_uart0_div";
605 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
609 /* reg[7]: reserved */
611 clk_uart0: clk_uart0_mux {
612 compatible = "rockchip,rk3188-mux-con";
613 rockchip,bits = <8 2>;
614 clocks = <&clk_uart0_div>, <&uart0_frac>, <&xin24m>;
615 clock-output-names = "clk_uart0";
617 rockchip,clkops-idx =
618 <CLKOPS_RATE_RK3288_I2S>;
619 rockchip,flags = <CLK_SET_RATE_PARENT>;
622 clk_uart_pll: clk_uart_pll_mux {
623 compatible = "rockchip,rk3188-mux-con";
624 rockchip,bits = <10 2>;
625 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&usb_480m>;
626 clock-output-names = "clk_uart_pll";
628 #clock-init-cells = <1>;
631 /* reg[15:12]: reserved */
635 clk_sel_con14: sel-con@007c {
636 compatible = "rockchip,rk3188-selcon";
638 #address-cells = <1>;
641 clk_uart1_div: clk_uart1_div {
642 compatible = "rockchip,rk3188-div-con";
643 rockchip,bits = <0 7>;
644 clocks = <&clk_uart_pll>;
645 clock-output-names = "clk_uart1_div";
646 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
650 /* reg[7]: reserved */
652 clk_uart1: clk_uart1_mux {
653 compatible = "rockchip,rk3188-mux-con";
654 rockchip,bits = <8 2>;
655 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
656 clock-output-names = "clk_uart1";
658 rockchip,clkops-idx =
659 <CLKOPS_RATE_RK3288_I2S>;
660 rockchip,flags = <CLK_SET_RATE_PARENT>;
663 /* reg[15:10]: reserved */
666 clk_sel_con15: sel-con@0080 {
667 compatible = "rockchip,rk3188-selcon";
669 #address-cells = <1>;
672 clk_uart2_div: clk_uart2_div {
673 compatible = "rockchip,rk3188-div-con";
674 rockchip,bits = <0 7>;
675 clocks = <&clk_uart_pll>;
676 clock-output-names = "clk_uart2_div";
677 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
681 /* reg[7]: reserved */
683 clk_uart2: clk_uart2_mux {
684 compatible = "rockchip,rk3188-mux-con";
685 rockchip,bits = <8 2>;
686 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
687 clock-output-names = "clk_uart2";
689 rockchip,clkops-idx =
690 <CLKOPS_RATE_RK3288_I2S>;
691 rockchip,flags = <CLK_SET_RATE_PARENT>;
694 /* reg[15:10]: reserved */
697 clk_sel_con16: sel-con@0084 {
698 compatible = "rockchip,rk3188-selcon";
700 #address-cells = <1>;
703 clk_sfc: clk_sfc_mux {
704 compatible = "rockchip,rk3188-mux-con";
705 rockchip,bits = <0 2>;
706 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>, <&xin24m>;
707 clock-output-names = "clk_sfc";
711 clk_sfc_div: clk_sfc_div {
712 compatible = "rockchip,rk3188-div-con";
713 rockchip,bits = <2 5>;
715 clock-output-names = "clk_sfc";
716 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
718 rockchip,clkops-idx =
719 <CLKOPS_RATE_MUX_DIV>;
722 /* reg[7]: reserved */
724 clk_nandc: clk_nandc_mux {
725 compatible = "rockchip,rk3188-mux-con";
726 rockchip,bits = <8 2>;
727 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
728 clock-output-names = "clk_nandc";
732 clk_nandc_div: clk_nandc_div {
733 compatible = "rockchip,rk3188-div-con";
734 rockchip,bits = <10 5>;
735 clocks = <&clk_nandc>;
736 clock-output-names = "clk_nandc";
737 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
739 rockchip,clkops-idx =
740 <CLKOPS_RATE_MUX_DIV>;
743 /* reg[31:15]: reserved */
746 clk_sel_con17: sel-con@0088 {
747 compatible = "rockchip,rk3188-selcon";
749 #address-cells = <1>;
752 uart0_frac: uart0_frac {
753 compatible = "rockchip,rk3188-frac-con";
754 clocks = <&clk_uart0_div>;
755 clock-output-names = "uart0_frac";
756 /* numerator denominator */
757 rockchip,bits = <0 32>;
758 rockchip,clkops-idx =
764 clk_sel_con18: sel-con@008c {
765 compatible = "rockchip,rk3188-selcon";
767 #address-cells = <1>;
770 uart1_frac: uart1_frac {
771 compatible = "rockchip,rk3188-frac-con";
772 clocks = <&clk_uart1_div>;
773 clock-output-names = "uart1_frac";
774 /* numerator denominator */
775 rockchip,bits = <0 32>;
776 rockchip,clkops-idx =
782 clk_sel_con19: sel-con@0090 {
783 compatible = "rockchip,rk3188-selcon";
785 #address-cells = <1>;
788 uart2_frac: uart2_frac {
789 compatible = "rockchip,rk3188-frac-con";
790 clocks = <&clk_uart2_div>;
791 clock-output-names = "uart2_frac";
792 /* numerator denominator */
793 rockchip,bits = <0 32>;
794 rockchip,clkops-idx =
801 clk_sel_con20: sel-con@0094 {
802 compatible = "rockchip,rk3188-selcon";
804 #address-cells = <1>;
807 clk_hevc_core: clk_hevc_core_mux {
808 compatible = "rockchip,rk3188-mux-con";
809 rockchip,bits = <0 2>;
810 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
811 clock-output-names = "clk_hevc_core";
813 #clock-init-cells = <1>;
816 clk_hevc_core_div: clk_hevc_core_div {
817 compatible = "rockchip,rk3188-div-con";
818 rockchip,bits = <2 5>;
819 clocks = <&clk_hevc_core>;
820 clock-output-names = "clk_hevc_core";
821 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
823 rockchip,clkops-idx =
824 <CLKOPS_RATE_MUX_DIV>;
825 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
828 /* reg[31:7]: reserved */
832 clk_sel_con21: sel-con@0098 {
833 compatible = "rockchip,rk3188-selcon";
835 #address-cells = <1>;
838 clk_mac_pll: clk_mac_pll_mux {
839 compatible = "rockchip,rk3188-mux-con";
840 rockchip,bits = <0 2>;
841 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
842 clock-output-names = "clk_mac_pll";
844 #clock-init-cells = <1>;
847 /* reg[2]: reserved */
849 clk_mac_ref: clk_mac_ref_mux {
850 compatible = "rockchip,rk3188-mux-con";
851 rockchip,bits = <3 1>;
852 clocks = <&clk_mac_pll_div>, <&rmii_clkin>;
853 clock-output-names = "clk_mac_ref";
855 rockchip,clkops-idx =
856 <CLKOPS_RATE_MAC_REF>;
857 rockchip,flags = <CLK_SET_RATE_PARENT>;
858 #clock-init-cells = <1>;
861 clk_mac_pll_div: clk_mac_pll_div {
862 compatible = "rockchip,rk3188-div-con";
863 rockchip,bits = <4 5>;
864 clocks = <&clk_mac_pll>;
865 clock-output-names = "clk_mac_pll";
866 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
868 rockchip,clkops-idx =
869 <CLKOPS_RATE_MUX_DIV>;
870 #clock-init-cells = <1>;
873 clk_mac_ref_div: clk_mac_ref_div {
874 compatible = "rockchip,rk3188-div-con";
875 rockchip,bits = <9 5>;
876 clocks = <&clk_mac_ref>;
877 clock-output-names = "clk_mac";
878 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
880 #clock-init-cells = <1>;
883 /* reg[15:14]: reserved */
886 clk_sel_con25: sel-con@00a8 {
887 compatible = "rockchip,rk3188-selcon";
889 #address-cells = <1>;
892 clk_spi0_div: clk_spi0_div {
893 compatible = "rockchip,rk3188-div-con";
894 rockchip,bits = <0 7>;
895 clocks = <&clk_spi0>;
896 clock-output-names = "clk_spi0";
897 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
899 rockchip,clkops-idx =
900 <CLKOPS_RATE_MUX_DIV>;
903 /* reg[7]: reserved */
905 clk_spi0: clk_spi0_mux {
906 compatible = "rockchip,rk3188-mux-con";
907 rockchip,bits = <8 2>;
908 clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>;
909 clock-output-names = "clk_spi0";
913 /* reg[15:10]: reserved */
917 clk_sel_con26: sel-con@00ac {
918 compatible = "rockchip,rk3188-selcon";
920 #address-cells = <1>;
924 compatible = "rockchip,rk3188-div-con";
925 rockchip,bits = <0 2>;
927 clock-output-names = "clk_ddr";
928 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
929 rockchip,div-relations =
934 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
935 CLK_SET_RATE_NO_REPARENT)>;
936 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
939 /* reg[7:1]: reserved */
941 clk_ddr: ddr_clk_pll_mux {
942 compatible = "rockchip,rk3188-mux-con";
943 rockchip,bits = <8 1>;
944 clocks = <&clk_dpll>, <&dummy>;
945 clock-output-names = "clk_ddr";
949 /* reg[15:9]: reserved */
952 clk_sel_con28: sel-con@00b4 {
953 compatible = "rockchip,rk3188-selcon";
955 #address-cells = <1>;
958 dclk_lcdc1: dclk_lcdc1_mux {
959 compatible = "rockchip,rk3188-mux-con";
960 rockchip,bits = <0 2>;
961 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
962 clock-output-names = "dclk_lcdc1";
964 #clock-init-cells = <1>;
967 /* reg[7:2]: reserved */
969 dclk_lcdc1_div: dclk_lcdc1_div {
970 compatible = "rockchip,rk3188-div-con";
971 rockchip,bits = <8 8>;
972 clocks = <&dclk_lcdc1>;
973 clock-output-names = "dclk_lcdc1";
974 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
976 rockchip,clkops-idx =
977 <CLKOPS_RATE_MUX_DIV>;
978 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
982 clk_sel_con30: sel-con@00bc {
983 compatible = "rockchip,rk3188-selcon";
985 #address-cells = <1>;
988 clk_testout_div: clk_testout_div {
989 compatible = "rockchip,rk3188-div-con";
990 rockchip,bits = <0 5>;
992 clock-output-names = "clk_testout";
993 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
995 #clock-init-cells = <1>;
998 /* reg[7:5]: reserved */
1000 hclk_vio_pre_div: hclk_vio_pre_div {
1001 compatible = "rockchip,rk3188-div-con";
1002 rockchip,bits = <8 5>;
1003 clocks = <&hclk_vio_pre>;
1004 clock-output-names = "hclk_vio_pre";
1005 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1007 rockchip,clkops-idx =
1008 <CLKOPS_RATE_MUX_DIV>;
1009 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1012 /* reg[13]: reserved */
1014 hclk_vio_pre: hclk_vio_pre_mux {
1015 compatible = "rockchip,rk3188-mux-con";
1016 rockchip,bits = <14 2>;
1017 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1018 clock-output-names = "hclk_vio_pre";
1020 #clock-init-cells = <1>;
1025 clk_sel_con31: sel-con@00c0 {
1026 compatible = "rockchip,rk3188-selcon";
1028 #address-cells = <1>;
1031 clk_hdmi: clk_hdmi_mux {
1032 compatible = "rockchip,rk3188-mux-con";
1033 rockchip,bits = <0 1>;
1034 clocks = <&dclk_lcdc1_div>, <&dummy>;
1035 clock-output-names = "clk_hdmi";
1039 /* reg[7:1]: reserved */
1041 aclk_vio_pre_div: aclk_vio_pre_div {
1042 compatible = "rockchip,rk3188-div-con";
1043 rockchip,bits = <8 5>;
1044 clocks = <&aclk_vio_pre>;
1045 clock-output-names = "aclk_vio_pre";
1046 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1048 rockchip,clkops-idx =
1049 <CLKOPS_RATE_MUX_DIV>;
1050 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1053 /* reg[13]: reserved */
1055 aclk_vio_pre: aclk_vio_pre_mux {
1056 compatible = "rockchip,rk3188-mux-con";
1057 rockchip,bits = <14 2>;
1058 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1059 clock-output-names = "aclk_vio_pre";
1061 #clock-init-cells = <1>;
1066 clk_sel_con32: sel-con@00c4 {
1067 compatible = "rockchip,rk3188-selcon";
1069 #address-cells = <1>;
1072 /* reg[7:0]: reserved */
1074 aclk_vcodec_pre_div: aclk_vcodec_pre_div {
1075 compatible = "rockchip,rk3188-div-con";
1076 rockchip,bits = <8 5>;
1077 clocks = <&aclk_vcodec_pre>;
1078 clock-output-names = "aclk_vcodec_pre";
1079 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1081 rockchip,clkops-idx =
1082 <CLKOPS_RATE_MUX_DIV>;
1083 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1086 /* reg[13]: reserved */
1088 aclk_vcodec_pre: aclk_vcodec_pre_mux {
1089 compatible = "rockchip,rk3188-mux-con";
1090 rockchip,bits = <14 2>;
1091 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1092 clock-output-names = "aclk_vcodec_pre";
1094 #clock-init-cells = <1>;
1098 clk_sel_con34: sel-con@00cc {
1099 compatible = "rockchip,rk3188-selcon";
1101 #address-cells = <1>;
1104 clk_gpu_pre_div: clk_gpu_pre_div {
1105 compatible = "rockchip,rk3188-div-con";
1106 rockchip,bits = <0 5>;
1107 clocks = <&clk_gpu_pre>;
1108 clock-output-names = "clk_gpu_pre";
1109 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1111 rockchip,clkops-idx =
1112 <CLKOPS_RATE_MUX_DIV>;
1113 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1116 /* reg[7:5]: reserved */
1118 clk_gpu_pre: clk_gpu_pre_mux {
1119 compatible = "rockchip,rk3188-mux-con";
1120 rockchip,bits = <8 2>;
1121 clocks = <&dummy>, <&dummy>, <&clk_gpll>;
1122 clock-output-names = "clk_gpu_pre";
1124 #clock-init-cells = <1>;
1127 /* reg[15:10]: reserved */
1134 /* Gate control regs */
1136 compatible = "rockchip,rk-gate-cons";
1137 #address-cells = <1>;
1141 clk_gates0: gate-clk@00d0{
1142 compatible = "rockchip,rk3188-gate-clk";
1145 <&clk_core>, <&clk_gpll>,
1146 <&clk_dpll>, <&aclk_cpu_pre>,
1148 <&aclk_cpu_pre>, <&aclk_cpu_pre>,
1149 <&clk_gpll>, <&clk_core>,
1151 <&clk_gpll>, <&clk_i2s_pll>,
1152 <&i2s_frac>, <&hclk_vio_pre>,
1154 <&dummy>, <&clk_i2s_out>,
1155 <&clk_i2s>, <&dummy>;
1157 clock-output-names =
1158 "pclk_dbg", "reserved", /* do not use bit1 = "cpu_gpll" */
1159 "reserved", "aclk_cpu_pre",
1161 "hclk_cpu_pre", "pclk_cpu_pre",
1162 "reserved", "aclk_core_pre",
1164 "reserved", "clk_i2s_pll",
1165 "i2s_frac", "hclk_vio_pre",
1167 "clk_cryto", "clk_i2s_out",
1168 "clk_i2s", "clk_testout";
1169 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1174 clk_gates1: gate-clk@00d4{
1175 compatible = "rockchip,rk3188-gate-clk";
1178 <&clk_timer0>, <&clk_timer1>,
1179 <&dummy>, <&jtag_tck>,
1181 <&aclk_vio_pre>, <&xin12m>,
1184 <&clk_uart0_div>, <&uart0_frac>,
1185 <&clk_uart1_div>, <&uart1_frac>,
1187 <&clk_uart2_div>, <&uart2_frac>,
1190 clock-output-names =
1191 "clk_timer0", "clk_timer1",
1192 "reserved", "clk_jatg",
1194 "aclk_vio_pre", "clk_otgphy0",
1195 "clk_otgphy1", "reserved",
1197 "clk_uart0_div", "uart0_frac",
1198 "clk_uart1_div", "uart1_frac",
1200 "clk_uart2_div", "uart2_frac",
1201 "reserved", "reserved";
1203 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1207 clk_gates2: gate-clk@00d8 {
1208 compatible = "rockchip,rk3188-gate-clk";
1211 <&aclk_peri_pre>, <&aclk_peri_pre>,
1212 <&aclk_peri_pre>, <&aclk_peri_pre>,
1214 <&clk_timer2>, <&clk_timer3>,
1215 <&clk_mac_ref>, <&dummy>,
1217 <&dummy>, <&clk_spi0>,
1218 <&clk_spdif_pll>, <&clk_sdmmc0>,
1220 <&spdif_frac>, <&clk_sdio>,
1221 <&clk_emmc>, <&dummy>;
1223 clock-output-names =
1224 "aclk_peri", "aclk_peri_pre",
1225 "hclk_peri_pre", "pclk_peri_pre",
1227 "clk_timer2", "clk_timer3",
1228 "clk_mac", "reserved",
1230 "reserved", "clk_spi0",
1231 "clk_spdif_pll", "clk_sdmmc0",
1233 "spdif_frac", "clk_sdio",
1234 "clk_emmc", "reserved";
1235 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1240 clk_gates3: gate-clk@00dc {
1241 compatible = "rockchip,rk3188-gate-clk";
1245 <&dclk_lcdc1>, <&dummy>,
1247 <&dummy>, <&hclk_peri_pre>,
1250 <&pclk_cpu_pre>, <&dummy>,
1251 <&dummy>, <&aclk_vcodec_pre>,
1253 <&aclk_vcodec_pre>, <&clk_gpu_pre>,
1254 <&hclk_peri_pre>, <&dummy>;
1256 clock-output-names =
1257 "reserved", "reserved",
1258 "dclk_lcdc1", "reserved",
1260 "reserved", "g_hclk_mac",
1261 "reserved", "reserved",
1263 "g_pclk_hdmi", "reserved",
1264 "reserved", "aclk_vcodec_pre",
1266 "hclk_vcodec", "clk_gpu_pre",
1267 "g_hclk_sfc", "reserved";
1268 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1273 clk_gates4: gate-clk@00e0{
1274 compatible = "rockchip,rk3188-gate-clk";
1277 <&hclk_peri_pre>, <&pclk_peri_pre>,
1278 <&aclk_peri_pre>, <&aclk_peri_pre>,
1284 <&aclk_cpu_pre>, <&dummy>,
1286 <&aclk_cpu_pre>, <&dummy>,
1289 clock-output-names =
1290 "g_hp_axi_matrix", "g_pp_axi_matrix",
1291 "g_aclk_cpu_peri", "g_ap_axi_matrix",
1293 "reserved", "reserved",
1294 "reserved", "reserved",
1296 "reserved", "reserved",
1297 "g_aclk_strc_sys", "reserved",
1299 /* Not use these ddr gates */
1300 "g_aclk_intmem", "reserved",
1301 "reserved", "reserved";
1303 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1307 clk_gates5: gate-clk@00e4 {
1308 compatible = "rockchip,rk3188-gate-clk";
1311 <&dummy>, <&aclk_peri_pre>,
1312 <&pclk_peri_pre>, <&dummy>,
1314 <&pclk_cpu_pre>, <&dummy>,
1315 <&hclk_cpu_pre>, <&pclk_cpu_pre>,
1317 <&dummy>, <&hclk_peri_pre>,
1318 <&hclk_peri_pre>, <&hclk_peri_pre>,
1320 <&dummy>, <&hclk_peri_pre>,
1321 <&pclk_cpu_pre>, <&dummy>;
1323 clock-output-names =
1324 "reserved", "g_aclk_dmac2",
1325 "g_pclk_efuse", "reserved",
1327 "g_pclk_grf", "reserved",
1328 "g_hclk_rom", "g_pclk_ddrupctl",
1330 "reserved", "g_hclk_nandc",
1331 "g_hclk_sdmmc0", "g_hclk_sdio",
1333 "reserved", "g_hclk_otg0",
1334 "g_pclk_acodec", "reserved";
1336 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1341 clk_gates6: gate-clk@00e8 {
1342 compatible = "rockchip,rk3188-gate-clk";
1354 <&hclk_vio_pre>, <&aclk_vio_pre>,
1357 clock-output-names =
1358 "reserved", "reserved",
1359 "reserved", "reserved",
1361 "reserved", "reserved",
1362 "reserved", "reserved",
1364 "reserved", "reserved",
1365 "reserved", "reserved",
1367 "g_hclk_vio_bus", "g_aclk_vio",
1368 "reserved", "reserved";
1370 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1375 clk_gates7: gate-clk@00ec {
1376 compatible = "rockchip,rk3188-gate-clk";
1379 <&hclk_peri_pre>, <&dummy>,
1380 <&hclk_peri_pre>, <&hclk_peri_pre>,
1383 <&dummy>, <&pclk_peri_pre>,
1386 <&pclk_peri_pre>, <&dummy>,
1388 <&pclk_peri_pre>, <&dummy>,
1389 <&dummy>, <&pclk_peri_pre>;
1391 clock-output-names =
1392 "g_hclk_emmc", "reserved",
1393 "g_hclk_i2s", "g_hclk_otg1",
1395 "reserved", "reserved",
1396 "reserved", "g_pclk_timer0",
1398 "reserved", "reserved",
1399 "g_pclk_pwm", "reserved",
1401 "g_pclk_spi", "reserved",
1402 "reserved", "g_pclk_wdt";
1404 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1409 clk_gates8: gate-clk@00f0 {
1410 compatible = "rockchip,rk3188-gate-clk";
1413 <&pclk_peri_pre>, <&pclk_peri_pre>,
1414 <&pclk_peri_pre>, <&dummy>,
1416 <&pclk_peri_pre>, <&pclk_peri_pre>,
1417 <&pclk_peri_pre>, <&dummy>,
1419 <&dummy>, <&pclk_peri_pre>,
1420 <&pclk_peri_pre>, <&pclk_peri_pre>,
1425 clock-output-names =
1426 "g_pclk_uart0", "g_pclk_uart1",
1427 "g_pclk_uart2", "reserved",
1429 "g_pclk_i2c0", "g_pclk_i2c1",
1430 "g_pclk_i2c2", "reserved",
1432 "reserved", "g_pclk_gpio0",
1433 "g_pclk_gpio1", "g_pclk_gpio2",
1435 "reserved", "reserved",
1436 "reserved", "reserved";
1438 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1442 clk_gates9: gate-clk@00f4 {
1443 compatible = "rockchip,rk3188-gate-clk";
1449 <&dummy>, <&hclk_vio_pre>,
1450 <&aclk_vio_pre>, <&dummy>,
1455 <&dummy>, <&hclk_peri_pre>,
1456 <&hclk_peri_pre>, <&aclk_peri_pre>;
1458 clock-output-names =
1459 "reserved", "reserved",
1460 "reserved", "reserved",
1462 "reserved", "g_hclk_lcdc",
1463 "g_aclk_lcdc", "reserved",
1465 "reserved", "reserved",
1466 "reserved", "reserved",
1468 "reserved", "g_hclk_usb_peri",
1469 "g_hclk_pe_arbi", "g_aclk_peri_niu";
1471 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1476 clk_gates10: gate-clk@00f8 {
1477 compatible = "rockchip,rk3188-gate-clk";
1480 <&xin24m>, <&xin24m>,
1481 <&xin24m>, <&dummy>,
1483 <&clk_nandc>, <&clk_sfc>,
1484 <&clk_hevc_core>, <&dummy>,
1486 <&clk_dpll>, <&dummy>,
1492 clock-output-names =
1493 "g_clk_pvtm_core", "g_clk_pvtm_gpu",
1494 "g_pvtm_video", "reserved",
1496 "clk_nandc", "clk_sfc",
1497 "clk_hevc_core", "reserved",
1499 "reserved", "reserved",
1500 "reserved", "reserved",
1502 "reserved", "reserved",
1503 "reserved", "reserved";
1505 rockchip,suspend-clkgating-setting = <0x0 0x0>; /* pwm logic vol */