arch/arm/boot/dts/rk3036-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3036.h>
  15
  16 /{
  17
  18         clocks {
  19                 compatible = "rockchip,rk-clocks";
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22                 ranges = <0x0  0x20000000  0x1f0>;
  23
  24                 fixed_rate_cons {
  25                         compatible = "rockchip,rk-fixed-rate-cons";
  26
  27                         xin24m: xin24m {
  28                                 compatible = "rockchip,rk-fixed-clock";
  29                                 clock-output-names = "xin24m";
  30                                 clock-frequency = <24000000>;
  31                                 #clock-cells = <0>;
  32                         };
  33
  34                         xin12m: xin12m {
  35                                 compatible = "rockchip,rk-fixed-clock";
  36                                 clocks = <&xin24m>;
  37                                 clock-output-names = "xin12m";
  38                                 clock-frequency = <12000000>;
  39                                 #clock-cells = <0>;
  40                         };
  41
  42                         rmii_clkin: rmii_clkin {
  43                                 compatible = "rockchip,rk-fixed-clock";
  44                                 clock-output-names = "rmii_clkin";
  45                                 clock-frequency = <0>;
  46                                 #clock-cells = <0>;
  47                         };
  48
  49                         usb_480m: usb_480m {
  50                                 compatible = "rockchip,rk-fixed-clock";
  51                                 clock-output-names = "usb_480m";
  52                                 clock-frequency = <480000000>;
  53                                 #clock-cells = <0>;
  54                         };
  55
  56                         i2s_clkin: i2s_clkin {
  57                                 compatible = "rockchip,rk-fixed-clock";
  58                                 clock-output-names = "i2s_clkin";
  59                                 clock-frequency = <0>;
  60                                 #clock-cells = <0>;
  61                         };
  62
  63                         jtag_tck: jtag_tck {
  64                                 compatible = "rockchip,rk-fixed-clock";
  65                                 clock-output-names = "jtag_tck";
  66                                 clock-frequency = <0>;
  67                                 #clock-cells = <0>;
  68                         };
  69
  70                         dummy: dummy {
  71                                 compatible = "rockchip,rk-fixed-clock";
  72                                 clock-output-names = "dummy";
  73                                 clock-frequency = <0>;
  74                                 #clock-cells = <0>;
  75                         };
  76
  77                         dummy_cpll: dummy_cpll {
  78                                 compatible = "rockchip,rk-fixed-clock";
  79                                 clock-output-names = "dummy_cpll";
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                         };
  83
  84                 };
  85
  86                 fixed_factor_cons {
  87                         compatible = "rockchip,rk-fixed-factor-cons";
  88
  89                         otgphy0_12m: otgphy0_12m {
  90                                 compatible = "rockchip,rk-fixed-factor-clock";
  91                                 clocks = <&clk_gates1 5>;
  92                                 clock-output-names = "otgphy0_12m";
  93                                 clock-div = <1>;
  94                                 clock-mult = <20>;
  95                                 #clock-cells = <0>;
  96                         };
  97                 };
  98
  99                 clock_regs {
 100                         compatible = "rockchip,rk-clock-regs";
 101                         #address-cells = <1>;
 102                         #size-cells = <1>;
 103                         reg = <0x0000 0x01f0>;
 104                         ranges;
 105
 106                         /* PLL control regs */
 107                         pll_cons {
 108                                 compatible = "rockchip,rk-pll-cons";
 109                                 #address-cells = <1>;
 110                                 #size-cells = <1>;
 111                                 ranges ;
 112
 113                                 clk_apll: pll-clk@0000 {
 114                                         compatible = "rockchip,rk3188-pll-clk";
 115                                         reg = <0x0000 0x10>;
 116                                         mode-reg = <0x0040 0>;
 117                                         status-reg = <0x0004 10>;
 118                                         clocks = <&xin24m>;
 119                                         clock-output-names = "clk_apll";
 120                                         rockchip,pll-type = <CLK_PLL_3036_APLL>;
 121                                         #clock-cells = <0>;
 122                                 };
 123
 124                                 clk_dpll: pll-clk@0010 {
 125                                         compatible = "rockchip,rk3188-pll-clk";
 126                                         reg = <0x0010 0x10>;
 127                                         mode-reg = <0x0040 4>;
 128                                         status-reg = <0x0014 10>;
 129                                         clocks = <&xin24m>;
 130                                         clock-output-names = "clk_dpll";
 131                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 132                                         #clock-cells = <0>;
 133                                 };
 134
 135                                 clk_gpll: pll-clk@0030 {
 136                                         compatible = "rockchip,rk3188-pll-clk";
 137                                         reg = <0x0030 0x10>;
 138                                         mode-reg = <0x0040 12>;
 139                                         status-reg = <0x0034 10>;
 140                                         clocks = <&xin24m>;
 141                                         clock-output-names = "clk_gpll";
 142                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 143                                         #clock-cells = <0>;
 144                                         #clock-init-cells = <1>;
 145                                 };
 146
 147                         };
 148
 149                         /* Select control regs */
 150                         clk_sel_cons {
 151                                 compatible = "rockchip,rk-sel-cons";
 152                                 #address-cells = <1>;
 153                                 #size-cells = <1>;
 154                                 ranges;
 155
 156                                 clk_sel_con0: sel-con@0044 {
 157                                         compatible = "rockchip,rk3188-selcon";
 158                                         reg = <0x0044 0x4>;
 159                                         #address-cells = <1>;
 160                                         #size-cells = <1>;
 161
 162                                         clk_core_pre_div: clk_core_pre_div {
 163                                                 compatible = "rockchip,rk3188-div-con";
 164                                                 rockchip,bits = <0 5>;
 165                                                 clocks = <&clk_core_pre>;
 166                                                 clock-output-names = "clk_core_pre";
 167                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 168                                                 #clock-cells = <0>;
 169                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 170                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 171                                                                         CLK_SET_RATE_NO_REPARENT)>;
 172                                         };
 173
 174                                         /* reg[6:5]: reserved */
 175
 176                                         clk_core_pre: clk_core_pre_mux {
 177                                                 compatible = "rockchip,rk3188-mux-con";
 178                                                 rockchip,bits = <7 1>;
 179                                                 clocks = <&clk_apll>, <&clk_gates0 6>;
 180                                                 clock-output-names = "clk_core_pre";
 181                                                 #clock-cells = <0>;
 182                                                 #clock-init-cells = <1>;
 183                                         };
 184
 185                                         aclk_cpu_pre_div: aclk_cpu_pre_div {
 186                                                 compatible = "rockchip,rk3188-div-con";
 187                                                 rockchip,bits = <8 5>;
 188                                                 clocks = <&aclk_cpu_pre>;
 189                                                 clock-output-names = "aclk_cpu_pre";
 190                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 191                                                 #clock-cells = <0>;
 192                                                 rockchip,clkops-idx =
 193                                                         <CLKOPS_RATE_MUX_DIV>;
 194                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 195                                         };
 196
 197                                         /* reg[13]: reserved */
 198
 199                                         aclk_cpu_pre: aclk_cpu_pre_mux {
 200                                                 compatible = "rockchip,rk3188-mux-con";
 201                                                 rockchip,bits = <14 2>;
 202                                                 clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>;
 203                                                 clock-output-names = "aclk_cpu_pre";
 204                                                 #clock-cells = <0>;
 205                                                 #clock-init-cells = <1>;
 206                                         };
 207
 208                                 };
 209
 210                                 clk_sel_con1: sel-con@0048 {
 211                                         compatible = "rockchip,rk3188-selcon";
 212                                         reg = <0x0048 0x4>;
 213                                         #address-cells = <1>;
 214                                         #size-cells = <1>;
 215
 216                                         pclk_dbg_div:  pclk_dbg_div {
 217                                                 compatible = "rockchip,rk3188-div-con";
 218                                                 rockchip,bits = <0 4>;
 219                                                 clocks = <&clk_core_pre>;
 220                                                 clock-output-names = "pclk_dbg";
 221                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 222                                                 #clock-cells = <0>;
 223                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 224                                         };
 225
 226                                         aclk_core_pre: aclk_core_pre_div {
 227                                                 compatible = "rockchip,rk3188-div-con";
 228                                                 rockchip,bits = <4 3>;
 229                                                 clocks = <&clk_core_pre>;
 230                                                 clock-output-names = "aclk_core_pre";
 231                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 232                                                 #clock-cells = <0>;
 233                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 234                                         };
 235
 236                                         /* reg[7]: reserved */
 237
 238                                         hclk_cpu_pre: hclk_cpu_pre_div {
 239                                                 compatible = "rockchip,rk3188-div-con";
 240                                                 rockchip,bits = <8 2>;
 241                                                 clocks = <&aclk_cpu_pre>;
 242                                                 clock-output-names = "hclk_cpu_pre";
 243                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 244                                                 #clock-cells = <0>;
 245                                                 #clock-init-cells = <1>;
 246                                         };
 247
 248                                         /* reg[11:10]: reserved */
 249
 250                                         pclk_cpu_pre: pclk_cpu_pre_div {
 251                                                 compatible = "rockchip,rk3188-div-con";
 252                                                 rockchip,bits = <12 3>;
 253                                                 clocks = <&aclk_cpu_pre>;
 254                                                 clock-output-names = "pclk_cpu_pre";
 255                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 256                                                 #clock-cells = <0>;
 257                                                 #clock-init-cells = <1>;
 258                                         };
 259
 260                                         /* reg[15]: reserved */
 261                                 };
 262
 263                                 clk_sel_con2: sel-con@004c {
 264                                         compatible = "rockchip,rk3188-selcon";
 265                                         reg = <0x004c 0x4>;
 266                                         #address-cells = <1>;
 267                                         #size-cells = <1>;
 268
 269                                         /* reg[3:0]: reserved */
 270
 271                                         clk_timer0: clk_timer0_mux {
 272                                                 compatible = "rockchip,rk3188-mux-con";
 273                                                 rockchip,bits = <4 1>;
 274                                                 clocks = <&xin24m>, <&aclk_peri_pre>;
 275                                                 clock-output-names = "clk_timer0";
 276                                                 #clock-cells = <0>;
 277                                                 #clock-init-cells = <1>;
 278                                         };
 279
 280                                         clk_timer1: clk_timer1_mux {
 281                                                 compatible = "rockchip,rk3188-mux-con";
 282                                                 rockchip,bits = <5 1>;
 283                                                 clocks = <&xin24m>, <&aclk_peri_pre>;
 284                                                 clock-output-names = "clk_timer1";
 285                                                 #clock-cells = <0>;
 286                                                 #clock-init-cells = <1>;
 287                                         };
 288
 289                                         clk_timer2: clk_timer2_mux {
 290                                                 compatible = "rockchip,rk3188-mux-con";
 291                                                 rockchip,bits = <6 1>;
 292                                                 clocks = <&xin24m>, <&aclk_peri_pre>;
 293                                                 clock-output-names = "clk_timer2";
 294                                                 #clock-cells = <0>;
 295                                                 #clock-init-cells = <1>;
 296                                         };
 297
 298                                         clk_timer3: clk_timer3_mux {
 299                                                 compatible = "rockchip,rk3188-mux-con";
 300                                                 rockchip,bits = <7 1>;
 301                                                 clocks = <&xin24m>, <&aclk_peri_pre>;
 302                                                 clock-output-names = "clk_timer3";
 303                                                 #clock-cells = <0>;
 304                                                 #clock-init-cells = <1>;
 305                                         };
 306
 307                                         /* reg[15:8]: reserved */
 308                                 };
 309
 310                                 clk_sel_con3: sel-con@0050 {
 311                                         compatible = "rockchip,rk3188-selcon";
 312                                         reg = <0x0050 0x4>;
 313                                         #address-cells = <1>;
 314                                         #size-cells = <1>;
 315
 316                                         clk_i2s_pll_div: clk_i2s_pll_div {
 317                                                 compatible = "rockchip,rk3188-div-con";
 318                                                 rockchip,bits = <0 7>;
 319                                                 clocks = <&clk_i2s_pll>;
 320                                                 clock-output-names = "clk_i2s_pll";
 321                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 322                                                 #clock-cells = <0>;
 323                                                 rockchip,clkops-idx =
 324                                                         <CLKOPS_RATE_MUX_DIV>;
 325                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 326                                         };
 327
 328                                         /* reg[7]: reserved */
 329
 330                                         clk_i2s: clk_i2s_mux {
 331                                                 compatible = "rockchip,rk3188-mux-con";
 332                                                 rockchip,bits = <8 2>;
 333                                                 clocks = <&clk_i2s_pll_div>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
 334                                                 clock-output-names = "clk_i2s";
 335                                                 #clock-cells = <0>;
 336                                                 rockchip,clkops-idx =
 337                                                         <CLKOPS_RATE_RK3288_I2S>;
 338                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 339                                         };
 340
 341                                         /* reg[11:10]: reserved */
 342
 343                                         clk_i2s_out: i2s_outclk_mux {
 344                                                 compatible = "rockchip,rk3188-mux-con";
 345                                                 rockchip,bits = <12 1>;
 346                                                 clocks = <&xin12m>, <&clk_i2s>;
 347                                                 clock-output-names = "i2s_clkout";
 348                                                 #clock-cells = <0>;
 349                                         };
 350
 351                                         /* reg[13]: reserved */
 352
 353                                         clk_i2s_pll: i2s_pll_mux {
 354                                                 compatible = "rockchip,rk3188-mux-con";
 355                                                 rockchip,bits = <14 2>;
 356                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
 357                                                 clock-output-names = "clk_i2s_pll";
 358                                                 #clock-cells = <0>;
 359                                                 #clock-init-cells = <1>;
 360                                         };
 361
 362                                 };
 363
 364                                 clk_sel_con5: sel-con@0058 {
 365                                         compatible = "rockchip,rk3188-selcon";
 366                                         reg = <0x0058 0x4>;
 367                                         #address-cells = <1>;
 368                                         #size-cells = <1>;
 369
 370                                         spdif_div: spdif_div {
 371                                                 compatible = "rockchip,rk3188-div-con";
 372                                                 rockchip,bits = <0 7>;
 373                                                 clocks = <&clk_spdif_pll>;
 374                                                 clock-output-names = "clk_spdif_pll";
 375                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 376                                                 #clock-cells = <0>;
 377                                                 rockchip,clkops-idx =
 378                                                         <CLKOPS_RATE_MUX_DIV>;
 379                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 380                                         };
 381
 382                                         /* reg[7]: reserved */
 383
 384                                         clk_spdif: spdif_mux {
 385                                                 compatible = "rockchip,rk3188-mux-con";
 386                                                 rockchip,bits = <8 2>;
 387                                                 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
 388                                                 clock-output-names = "clk_spdif";
 389                                                 #clock-cells = <0>;
 390                                                 rockchip,clkops-idx =
 391                                                         <CLKOPS_RATE_RK3288_I2S>;
 392                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 393                                         };
 394
 395                                         clk_spdif_pll: spdif_pll_mux {
 396                                                 compatible = "rockchip,rk3188-mux-con";
 397                                                 rockchip,bits = <10 2>;
 398                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
 399                                                 clock-output-names = "clk_spdif_pll";
 400                                                 #clock-cells = <0>;
 401                                                 #clock-init-cells = <1>;
 402                                         };
 403
 404                                         /* reg[15:12]: reserved */
 405                                 };
 406
 407                                 clk_sel_con7: sel-con@0060 {
 408                                         compatible = "rockchip,rk3188-selcon";
 409                                         reg = <0x0060 0x4>;
 410                                         #address-cells = <1>;
 411                                         #size-cells = <1>;
 412
 413                                         i2s_frac: i2s_frac {
 414                                                 compatible = "rockchip,rk3188-frac-con";
 415                                                 clocks = <&clk_i2s_pll>;
 416                                                 clock-output-names = "i2s_frac";
 417                                                 /* numerator    denominator */
 418                                                 rockchip,bits = <0 32>;
 419                                                 rockchip,clkops-idx =
 420                                                         <CLKOPS_RATE_FRAC>;
 421                                                 #clock-cells = <0>;
 422                                         };
 423                                 };
 424
 425                                 clk_sel_con9: sel-con@0068 {
 426                                         compatible = "rockchip,rk3188-selcon";
 427                                         reg = <0x0068 0x4>;
 428                                         #address-cells = <1>;
 429                                         #size-cells = <1>;
 430
 431                                         spdif_frac: spdif_frac {
 432                                                 compatible = "rockchip,rk3188-frac-con";
 433                                                 clocks = <&spdif_div>;
 434                                                 clock-output-names = "spdif_frac";
 435                                                 /* numerator    denominator */
 436                                                 rockchip,bits = <0 32>;
 437                                                 rockchip,clkops-idx =
 438                                                         <CLKOPS_RATE_FRAC>;
 439                                                 #clock-cells = <0>;
 440                                         };
 441                                 };
 442
 443                                 clk_sel_con10: sel-con@006c {
 444                                         compatible = "rockchip,rk3188-selcon";
 445                                         reg = <0x006c 0x4>;
 446                                         #address-cells = <1>;
 447                                         #size-cells = <1>;
 448
 449                                         aclk_peri_pre_div: aclk_peri_pre_div {
 450                                                 compatible = "rockchip,rk3188-div-con";
 451                                                 rockchip,bits = <0 5>;
 452                                                 clocks = <&aclk_peri_pre>;
 453                                                 clock-output-names = "aclk_peri_pre";
 454                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 455                                                 #clock-cells = <0>;
 456                                                 rockchip,clkops-idx =
 457                                                         <CLKOPS_RATE_MUX_DIV>;
 458                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 459                                         };
 460
 461                                         /* reg[7:5]: reserved */
 462
 463                                         hclk_peri_pre: hclk_peri_pre_div {
 464                                                 compatible = "rockchip,rk3188-div-con";
 465                                                 rockchip,bits = <8 2>;
 466                                                 clocks = <&aclk_peri_pre>;
 467                                                 clock-output-names = "hclk_peri_pre";
 468                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 469                                                 rockchip,div-relations =
 470                                                                 <0x0 1
 471                                                                  0x1 2
 472                                                                  0x2 4>;
 473                                                 #clock-cells = <0>;
 474                                                 #clock-init-cells = <1>;
 475                                         };
 476
 477                                         /* reg[11:10]: reserved */
 478
 479                                         pclk_peri_pre: pclk_peri_div {
 480                                                 compatible = "rockchip,rk3188-div-con";
 481                                                 rockchip,bits = <12 2>;
 482                                                 clocks = <&aclk_peri_pre>;
 483                                                 clock-output-names = "pclk_peri_pre";
 484                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 485                                                 rockchip,div-relations =
 486                                                                 <0x0 1
 487                                                                  0x1 2
 488                                                                  0x2 4
 489                                                                  0x3 8>;
 490                                                 #clock-cells = <0>;
 491                                                 #clock-init-cells = <1>;
 492                                         };
 493
 494                                         aclk_peri_pre: aclk_peri_pre_mux {
 495                                                 compatible = "rockchip,rk3188-mux-con";
 496                                                 rockchip,bits = <14 2>;
 497                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
 498                                                 clock-output-names = "aclk_peri_pre";
 499                                                 #clock-cells = <0>;
 500                                                 #clock-init-cells = <1>;
 501                                         };
 502                                 };
 503
 504                                 clk_sel_con11: sel-con@0070 {
 505                                         compatible = "rockchip,rk3188-selcon";
 506                                         reg = <0x0070 0x4>;
 507                                         #address-cells = <1>;
 508                                         #size-cells = <1>;
 509
 510                                         clk_sdmmc0_div: clk_sdmmc0_div {
 511                                                 compatible = "rockchip,rk3188-div-con";
 512                                                 rockchip,bits = <0 6>;
 513                                                 clocks = <&clk_sdmmc0>;
 514                                                 clock-output-names = "clk_sdmmc0";
 515                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 516                                                 #clock-cells = <0>;
 517                                                 rockchip,clkops-idx =
 518                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 519                                         };
 520
 521                                         /* reg[7]: reserved */
 522
 523                                         clk_sdio_div: clk_sdio_div {
 524                                                 compatible = "rockchip,rk3188-div-con";
 525                                                 rockchip,bits = <8 7>;
 526                                                 clocks = <&clk_sdio>;
 527                                                 clock-output-names = "clk_sdio";
 528                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 529                                                 #clock-cells = <0>;
 530                                                 rockchip,clkops-idx =
 531                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 532                                         };
 533
 534                                         /* reg[15]: reserved */
 535
 536                                 };
 537
 538                                 clk_sel_con12: sel-con@0074 {
 539                                         compatible = "rockchip,rk3188-selcon";
 540                                         reg = <0x0074 0x4>;
 541                                         #address-cells = <1>;
 542                                         #size-cells = <1>;
 543
 544                                         clk_emmc_div: clk_emmc_div {
 545                                                 compatible = "rockchip,rk3188-div-con";
 546                                                 rockchip,bits = <0 7>;
 547                                                 clocks = <&clk_emmc>;
 548                                                 clock-output-names = "clk_emmc";
 549                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 550                                                 #clock-cells = <0>;
 551                                                 rockchip,clkops-idx =
 552                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 553                                         };
 554
 555                                         /* reg[7]: reserved */
 556
 557                                         clk_sdmmc0: clk_sdmmc0_mux {
 558                                                 compatible = "rockchip,rk3188-mux-con";
 559                                                 rockchip,bits = <8 2>;
 560                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
 561                                                 clock-output-names = "clk_sdmmc0";
 562                                                 #clock-cells = <0>;
 563                                         };
 564
 565                                         clk_sdio: clk_sdio_mux {
 566                                                 compatible = "rockchip,rk3188-mux-con";
 567                                                 rockchip,bits = <10 2>;
 568                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
 569                                                 clock-output-names = "clk_sdio";
 570                                                 #clock-cells = <0>;
 571                                         };
 572
 573                                         clk_emmc: clk_emmc_mux {
 574                                                 compatible = "rockchip,rk3188-mux-con";
 575                                                 rockchip,bits = <12 2>;
 576                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
 577                                                 clock-output-names = "clk_emmc";
 578                                                 #clock-cells = <0>;
 579                                         };
 580
 581                                         /* reg[15:14]: reserved */
 582                                 };
 583
 584                                 clk_sel_con13: sel-con@0078 {
 585                                         compatible = "rockchip,rk3188-selcon";
 586                                         reg = <0x0078 0x4>;
 587                                         #address-cells = <1>;
 588                                         #size-cells = <1>;
 589
 590                                         clk_uart0_div: clk_uart0_div {
 591                                                 compatible = "rockchip,rk3188-div-con";
 592                                                 rockchip,bits = <0 7>;
 593                                                 clocks = <&clk_uart_pll>;
 594                                                 clock-output-names = "clk_uart0_div";
 595                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 596                                                 #clock-cells = <0>;
 597                                         };
 598
 599                                         /* reg[7]: reserved */
 600
 601                                         clk_uart0: clk_uart0_mux {
 602                                                 compatible = "rockchip,rk3188-mux-con";
 603                                                 rockchip,bits = <8 2>;
 604                                                 clocks = <&clk_uart0_div>, <&uart0_frac>, <&xin24m>;
 605                                                 clock-output-names = "clk_uart0";
 606                                                 #clock-cells = <0>;
 607                                                 rockchip,clkops-idx =
 608                                                         <CLKOPS_RATE_RK3288_I2S>;
 609                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 610                                         };
 611
 612                                         clk_uart_pll: clk_uart_pll_mux {
 613                                                 compatible = "rockchip,rk3188-mux-con";
 614                                                 rockchip,bits = <10 2>;
 615                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&usb_480m>;
 616                                                 clock-output-names = "clk_uart_pll";
 617                                                 #clock-cells = <0>;
 618                                                 #clock-init-cells = <1>;
 619                                         };
 620
 621                                         /* reg[15:12]: reserved */
 622
 623                                 };
 624
 625                                 clk_sel_con14: sel-con@007c {
 626                                         compatible = "rockchip,rk3188-selcon";
 627                                         reg = <0x007c 0x4>;
 628                                         #address-cells = <1>;
 629                                         #size-cells = <1>;
 630
 631                                         clk_uart1_div: clk_uart1_div {
 632                                                 compatible = "rockchip,rk3188-div-con";
 633                                                 rockchip,bits = <0 7>;
 634                                                 clocks = <&clk_uart_pll>;
 635                                                 clock-output-names = "clk_uart1_div";
 636                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 637                                                 #clock-cells = <0>;
 638                                         };
 639
 640                                         /* reg[7]: reserved */
 641
 642                                         clk_uart1: clk_uart1_mux {
 643                                                 compatible = "rockchip,rk3188-mux-con";
 644                                                 rockchip,bits = <8 2>;
 645                                                 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
 646                                                 clock-output-names = "clk_uart1";
 647                                                 #clock-cells = <0>;
 648                                                 rockchip,clkops-idx =
 649                                                         <CLKOPS_RATE_RK3288_I2S>;
 650                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 651                                         };
 652
 653                                         /* reg[15:10]: reserved */
 654                                 };
 655
 656                                 clk_sel_con15: sel-con@0080 {
 657                                         compatible = "rockchip,rk3188-selcon";
 658                                         reg = <0x0080 0x4>;
 659                                         #address-cells = <1>;
 660                                         #size-cells = <1>;
 661
 662                                         clk_uart2_div: clk_uart2_div {
 663                                                 compatible = "rockchip,rk3188-div-con";
 664                                                 rockchip,bits = <0 7>;
 665                                                 clocks = <&clk_uart_pll>;
 666                                                 clock-output-names = "clk_uart2_div";
 667                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 668                                                 #clock-cells = <0>;
 669                                         };
 670
 671                                         /* reg[7]: reserved */
 672
 673                                         clk_uart2: clk_uart2_mux {
 674                                                 compatible = "rockchip,rk3188-mux-con";
 675                                                 rockchip,bits = <8 2>;
 676                                                 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
 677                                                 clock-output-names = "clk_uart2";
 678                                                 #clock-cells = <0>;
 679                                                 rockchip,clkops-idx =
 680                                                         <CLKOPS_RATE_RK3288_I2S>;
 681                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 682                                         };
 683
 684                                         /* reg[15:10]: reserved */
 685                                 };
 686
 687                                 clk_sel_con16: sel-con@0084 {
 688                                         compatible = "rockchip,rk3188-selcon";
 689                                         reg = <0x0084 0x4>;
 690                                         #address-cells = <1>;
 691                                         #size-cells = <1>;
 692
 693                                         clk_sfc: clk_sfc_mux {
 694                                                 compatible = "rockchip,rk3188-mux-con";
 695                                                 rockchip,bits = <0 2>;
 696                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>, <&xin24m>;
 697                                                 clock-output-names = "clk_sfc";
 698                                                 #clock-cells = <0>;
 699                                         };
 700
 701                                         clk_sfc_div: clk_sfc_div {
 702                                                 compatible = "rockchip,rk3188-div-con";
 703                                                 rockchip,bits = <2 5>;
 704                                                 clocks = <&clk_sfc>;
 705                                                 clock-output-names = "clk_sfc";
 706                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 707                                                 #clock-cells = <0>;
 708                                                 rockchip,clkops-idx =
 709                                                         <CLKOPS_RATE_MUX_DIV>;
 710                                         };
 711
 712                                         /* reg[7]: reserved */
 713
 714                                         clk_nandc: clk_nandc_mux {
 715                                                 compatible = "rockchip,rk3188-mux-con";
 716                                                 rockchip,bits = <8 2>;
 717                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
 718                                                 clock-output-names = "clk_nandc";
 719                                                 #clock-cells = <0>;
 720                                         };
 721
 722                                         clk_nandc_div: clk_nandc_div {
 723                                                 compatible = "rockchip,rk3188-div-con";
 724                                                 rockchip,bits = <10 5>;
 725                                                 clocks = <&clk_nandc>;
 726                                                 clock-output-names = "clk_nandc";
 727                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 728                                                 #clock-cells = <0>;
 729                                                 rockchip,clkops-idx =
 730                                                         <CLKOPS_RATE_MUX_DIV>;
 731                                         };
 732
 733                                         /* reg[31:15]: reserved */
 734                                 };
 735
 736                                 clk_sel_con17: sel-con@0088 {
 737                                         compatible = "rockchip,rk3188-selcon";
 738                                         reg = <0x0088 0x4>;
 739                                         #address-cells = <1>;
 740                                         #size-cells = <1>;
 741
 742                                         uart0_frac: uart0_frac {
 743                                                 compatible = "rockchip,rk3188-frac-con";
 744                                                 clocks = <&clk_uart0_div>;
 745                                                 clock-output-names = "uart0_frac";
 746                                                 /* numerator    denominator */
 747                                                 rockchip,bits = <0 32>;
 748                                                 rockchip,clkops-idx =
 749                                                         <CLKOPS_RATE_FRAC>;
 750                                                 #clock-cells = <0>;
 751                                         };
 752                                 };
 753
 754                                 clk_sel_con18: sel-con@008c {
 755                                         compatible = "rockchip,rk3188-selcon";
 756                                         reg = <0x008c 0x4>;
 757                                         #address-cells = <1>;
 758                                         #size-cells = <1>;
 759
 760                                         uart1_frac: uart1_frac {
 761                                                 compatible = "rockchip,rk3188-frac-con";
 762                                                 clocks = <&clk_uart1_div>;
 763                                                 clock-output-names = "uart1_frac";
 764                                                 /* numerator    denominator */
 765                                                 rockchip,bits = <0 32>;
 766                                                 rockchip,clkops-idx =
 767                                                         <CLKOPS_RATE_FRAC>;
 768                                                 #clock-cells = <0>;
 769                                         };
 770                                 };
 771
 772                                 clk_sel_con19: sel-con@0090 {
 773                                         compatible = "rockchip,rk3188-selcon";
 774                                         reg = <0x0090 0x4>;
 775                                         #address-cells = <1>;
 776                                         #size-cells = <1>;
 777
 778                                         uart2_frac: uart2_frac {
 779                                                 compatible = "rockchip,rk3188-frac-con";
 780                                                 clocks = <&clk_uart2_div>;
 781                                                 clock-output-names = "uart2_frac";
 782                                                 /* numerator    denominator */
 783                                                 rockchip,bits = <0 32>;
 784                                                 rockchip,clkops-idx =
 785                                                         <CLKOPS_RATE_FRAC>;
 786                                                 #clock-cells = <0>;
 787                                         };
 788
 789                                 };
 790
 791                                 clk_sel_con20: sel-con@0094 {
 792                                         compatible = "rockchip,rk3188-selcon";
 793                                         reg = <0x0094 0x4>;
 794                                         #address-cells = <1>;
 795                                         #size-cells = <1>;
 796
 797                                         clk_hevc_core: clk_hevc_core_mux {
 798                                                 compatible = "rockchip,rk3188-mux-con";
 799                                                 rockchip,bits = <0 2>;
 800                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
 801                                                 clock-output-names = "clk_hevc_core";
 802                                                 #clock-cells = <0>;
 803                                                 #clock-init-cells = <1>;
 804                                         };
 805
 806                                         clk_hevc_core_div: clk_hevc_core_div {
 807                                                 compatible = "rockchip,rk3188-div-con";
 808                                                 rockchip,bits = <2 5>;
 809                                                 clocks = <&clk_hevc_core>;
 810                                                 clock-output-names = "clk_hevc_core";
 811                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 812                                                 #clock-cells = <0>;
 813                                                 rockchip,clkops-idx =
 814                                                         <CLKOPS_RATE_MUX_DIV>;
 815                                         };
 816
 817                                         /* reg[31:7]: reserved */
 818
 819                                 };
 820
 821                                 clk_sel_con21: sel-con@0098 {
 822                                         compatible = "rockchip,rk3188-selcon";
 823                                         reg = <0x0098 0x4>;
 824                                         #address-cells = <1>;
 825                                         #size-cells = <1>;
 826
 827                                         clk_mac_pll: clk_mac_pll_mux {
 828                                                 compatible = "rockchip,rk3188-mux-con";
 829                                                 rockchip,bits = <0 2>;
 830                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
 831                                                 clock-output-names = "clk_mac_pll";
 832                                                 #clock-cells = <0>;
 833                                         };
 834
 835                                         /* reg[2]: reserved */
 836
 837                                         clk_mac_ref: clk_mac_ref_mux {
 838                                                 compatible = "rockchip,rk3188-mux-con";
 839                                                 rockchip,bits = <3 1>;
 840                                                 clocks = <&clk_mac_pll_div>, <&rmii_clkin>;
 841                                                 clock-output-names = "clk_mac_ref";
 842                                                 #clock-cells = <0>;
 843                                                 rockchip,clkops-idx =
 844                                                         <CLKOPS_RATE_MAC_REF>;
 845                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 846                                                 #clock-init-cells = <1>;
 847                                         };
 848
 849                                         clk_mac_pll_div: clk_mac_pll_div {
 850                                                 compatible = "rockchip,rk3188-div-con";
 851                                                 rockchip,bits = <4 5>;
 852                                                 clocks = <&clk_mac_pll>;
 853                                                 clock-output-names = "clk_mac_pll";
 854                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 855                                                 #clock-cells = <0>;
 856                                                 rockchip,clkops-idx =
 857                                                         <CLKOPS_RATE_MUX_DIV>;
 858                                         };
 859
 860                                         clk_mac_ref_div: clk_mac_ref_div {
 861                                                 compatible = "rockchip,rk3188-div-con";
 862                                                 rockchip,bits = <9 5>;
 863                                                 clocks = <&clk_mac_ref>;
 864                                                 clock-output-names = "clk_mac";
 865                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 866                                                 #clock-cells = <0>;
 867                                                 #clock-init-cells = <1>;
 868                                         };
 869
 870                                         /* reg[15:14]: reserved */
 871                                 };
 872
 873                                 clk_sel_con25: sel-con@00a8 {
 874                                         compatible = "rockchip,rk3188-selcon";
 875                                         reg = <0x00a8 0x4>;
 876                                         #address-cells = <1>;
 877                                         #size-cells = <1>;
 878
 879                                         clk_spi0_div: clk_spi0_div {
 880                                                 compatible = "rockchip,rk3188-div-con";
 881                                                 rockchip,bits = <0 7>;
 882                                                 clocks = <&clk_spi0>;
 883                                                 clock-output-names = "clk_spi0";
 884                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 885                                                 #clock-cells = <0>;
 886                                                 rockchip,clkops-idx =
 887                                                         <CLKOPS_RATE_MUX_DIV>;
 888                                         };
 889
 890                                         /* reg[7]: reserved */
 891
 892                                         clk_spi0: clk_spi0_mux {
 893                                                 compatible = "rockchip,rk3188-mux-con";
 894                                                 rockchip,bits = <8 2>;
 895                                                 clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>;
 896                                                 clock-output-names = "clk_spi0";
 897                                                 #clock-cells = <0>;
 898                                         };
 899
 900                                         /* reg[15:10]: reserved */
 901
 902                                 };
 903
 904                                 clk_sel_con26: sel-con@00ac {
 905                                         compatible = "rockchip,rk3188-selcon";
 906                                         reg = <0x00ac 0x4>;
 907                                         #address-cells = <1>;
 908                                         #size-cells = <1>;
 909
 910                                         ddr_div: ddr_div {
 911                                                 compatible = "rockchip,rk3188-div-con";
 912                                                 rockchip,bits = <0 2>;
 913                                                 clocks = <&clk_ddr>;
 914                                                 clock-output-names = "clk_ddr";
 915                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 916                                                 rockchip,div-relations =
 917                                                                 <0x0 1
 918                                                                  0x1 2
 919                                                                  0x3 4>;
 920                                                 #clock-cells = <0>;
 921                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 922                                                                         CLK_SET_RATE_NO_REPARENT)>;
 923                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
 924                                         };
 925
 926                                         /* reg[7:1]: reserved */
 927
 928                                         clk_ddr: ddr_clk_pll_mux {
 929                                                 compatible = "rockchip,rk3188-mux-con";
 930                                                 rockchip,bits = <8 1>;
 931                                                 clocks = <&clk_gates0 2>, <&clk_gates0 8>;
 932                                                 clock-output-names = "clk_ddr";
 933                                                 #clock-cells = <0>;
 934                                         };
 935
 936                                         /* reg[15:9]: reserved */
 937                                 };
 938
 939                                 clk_sel_con28: sel-con@00b4 {
 940                                         compatible = "rockchip,rk3188-selcon";
 941                                         reg = <0x00b4 0x4>;
 942                                         #address-cells = <1>;
 943                                         #size-cells = <1>;
 944
 945                                         dclk_lcdc1: dclk_lcdc1_mux {
 946                                                 compatible = "rockchip,rk3188-mux-con";
 947                                                 rockchip,bits = <0 2>;
 948                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
 949                                                 clock-output-names = "dclk_lcdc1";
 950                                                 #clock-cells = <0>;
 951                                                 #clock-init-cells = <1>;
 952                                         };
 953
 954                                         /* reg[7:2]: reserved */
 955
 956                                         dclk_lcdc1_div: dclk_lcdc1_div {
 957                                                 compatible = "rockchip,rk3188-div-con";
 958                                                 rockchip,bits = <8 8>;
 959                                                 clocks = <&dclk_lcdc1>;
 960                                                 clock-output-names = "dclk_lcdc1";
 961                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 962                                                 #clock-cells = <0>;
 963                                                 rockchip,clkops-idx =
 964                                                         <CLKOPS_RATE_MUX_DIV>;
 965                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 966                                         };
 967                                 };
 968
 969                                 clk_sel_con30: sel-con@00bc {
 970                                         compatible = "rockchip,rk3188-selcon";
 971                                         reg = <0x00bc 0x4>;
 972                                         #address-cells = <1>;
 973                                         #size-cells = <1>;
 974
 975                                         clk_testout_div: clk_testout_div {
 976                                                 compatible = "rockchip,rk3188-div-con";
 977                                                 rockchip,bits = <0 5>;
 978                                                 clocks = <&dummy>;
 979                                                 clock-output-names = "clk_testout";
 980                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 981                                                 #clock-cells = <0>;
 982                                                 #clock-init-cells = <1>;
 983                                         };
 984
 985                                         /* reg[7:5]: reserved */
 986
 987                                         hclk_vio_pre_div: hclk_vio_pre_div {
 988                                                 compatible = "rockchip,rk3188-div-con";
 989                                                 rockchip,bits = <8 5>;
 990                                                 clocks = <&hclk_vio_pre>;
 991                                                 clock-output-names = "hclk_vio_pre";
 992                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 993                                                 #clock-cells = <0>;
 994                                                 rockchip,clkops-idx =
 995                                                         <CLKOPS_RATE_MUX_DIV>;
 996                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 997                                         };
 998
 999                                         /* reg[13]: reserved */
1000
1001                                         hclk_vio_pre: hclk_vio_pre_mux {
1002                                                 compatible = "rockchip,rk3188-mux-con";
1003                                                 rockchip,bits = <14 2>;
1004                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1005                                                 clock-output-names = "hclk_vio_pre";
1006                                                 #clock-cells = <0>;
1007                                                 #clock-init-cells = <1>;
1008                                         };
1009
1010                                 };
1011
1012                                 clk_sel_con31: sel-con@00c0 {
1013                                         compatible = "rockchip,rk3188-selcon";
1014                                         reg = <0x00c0 0x4>;
1015                                         #address-cells = <1>;
1016                                         #size-cells = <1>;
1017
1018                                         clk_hdmi: clk_hdmi_mux {
1019                                                 compatible = "rockchip,rk3188-mux-con";
1020                                                 rockchip,bits = <0 1>;
1021                                                 clocks = <&dclk_lcdc1_div>, <&dummy>;
1022                                                 clock-output-names = "clk_hdmi";
1023                                                 #clock-cells = <0>;
1024                                         };
1025
1026                                         /* reg[7:1]: reserved */
1027
1028                                         aclk_vio_pre_div: aclk_vio_pre_div {
1029                                                 compatible = "rockchip,rk3188-div-con";
1030                                                 rockchip,bits = <8 5>;
1031                                                 clocks = <&aclk_vio_pre>;
1032                                                 clock-output-names = "aclk_vio_pre";
1033                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1034                                                 #clock-cells = <0>;
1035                                                 rockchip,clkops-idx =
1036                                                         <CLKOPS_RATE_MUX_DIV>;
1037                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1038                                         };
1039
1040                                         /* reg[13]: reserved */
1041
1042                                         aclk_vio_pre: aclk_vio_pre_mux {
1043                                                 compatible = "rockchip,rk3188-mux-con";
1044                                                 rockchip,bits = <14 2>;
1045                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1046                                                 clock-output-names = "aclk_vio_pre";
1047                                                 #clock-cells = <0>;
1048                                                 #clock-init-cells = <1>;
1049                                         };
1050
1051                                 };
1052
1053                                 clk_sel_con32: sel-con@00c4 {
1054                                         compatible = "rockchip,rk3188-selcon";
1055                                         reg = <0x00c4 0x4>;
1056                                         #address-cells = <1>;
1057                                         #size-cells = <1>;
1058
1059                                         /* reg[7:0]: reserved */
1060
1061                                         aclk_vcodec_pre_div: aclk_vcodec_pre_div {
1062                                                 compatible = "rockchip,rk3188-div-con";
1063                                                 rockchip,bits = <8 5>;
1064                                                 clocks = <&aclk_vcodec_pre>;
1065                                                 clock-output-names = "aclk_vcodec_pre";
1066                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1067                                                 #clock-cells = <0>;
1068                                                 rockchip,clkops-idx =
1069                                                         <CLKOPS_RATE_MUX_DIV>;
1070                                         };
1071
1072                                         /* reg[13]: reserved */
1073
1074                                         aclk_vcodec_pre: aclk_vcodec_pre_mux {
1075                                                 compatible = "rockchip,rk3188-mux-con";
1076                                                 rockchip,bits = <14 2>;
1077                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1078                                                 clock-output-names = "aclk_vcodec_pre";
1079                                                 #clock-cells = <0>;
1080                                                 #clock-init-cells = <1>;
1081                                         };
1082                                 };
1083
1084                                 clk_sel_con34: sel-con@00cc {
1085                                         compatible = "rockchip,rk3188-selcon";
1086                                         reg = <0x00cc 0x4>;
1087                                         #address-cells = <1>;
1088                                         #size-cells = <1>;
1089
1090                                         clk_gpu_pre_div: clk_gpu_pre_div {
1091                                                 compatible = "rockchip,rk3188-div-con";
1092                                                 rockchip,bits = <0 5>;
1093                                                 clocks = <&clk_gpu_pre>;
1094                                                 clock-output-names = "clk_gpu_pre";
1095                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1096                                                 #clock-cells = <0>;
1097                                                 rockchip,clkops-idx =
1098                                                         <CLKOPS_RATE_MUX_DIV>;
1099                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1100                                         };
1101
1102                                         /* reg[7:5]: reserved */
1103
1104                                         clk_gpu_pre: clk_gpu_pre_mux {
1105                                                 compatible = "rockchip,rk3188-mux-con";
1106                                                 rockchip,bits = <8 2>;
1107                                                 clocks = <&dummy>, <&clk_dpll>, <&clk_gpll>;
1108                                                 clock-output-names = "clk_gpu_pre";
1109                                                 #clock-cells = <0>;
1110                                                 #clock-init-cells = <1>;
1111                                         };
1112
1113                                         /* reg[15:10]: reserved */
1114
1115                                 };
1116
1117                         };
1118
1119
1120                         /* Gate control regs */
1121                         clk_gate_cons {
1122                                 compatible = "rockchip,rk-gate-cons";
1123                                 #address-cells = <1>;
1124                                 #size-cells = <1>;
1125                                 ranges ;
1126
1127                                 clk_gates0: gate-clk@00d0{
1128                                         compatible = "rockchip,rk3188-gate-clk";
1129                                         reg = <0x00d0 0x4>;
1130                                         clocks =
1131                                                 <&clk_core_pre>,                <&clk_gpll>,
1132                                                 <&clk_dpll>,    <&aclk_cpu_pre>,
1133
1134                                                 <&aclk_cpu_pre>,        <&aclk_cpu_pre>,
1135                                                 <&clk_gpll>,            <&clk_core_pre>,
1136
1137                                                 <&clk_gpll>,    <&clk_i2s_pll>,
1138                                                 <&i2s_frac>,    <&hclk_vio_pre>,
1139
1140                                                 <&dummy>,               <&clk_i2s_out>,
1141                                                 <&clk_i2s>,             <&dummy>;
1142
1143                                         clock-output-names =
1144                                                 "pclk_dbg",                     "reserved",      /* do not use bit1 = "cpu_gpll" */
1145                                                 "reserved",             "aclk_cpu_pre",
1146
1147                                                 "hclk_cpu_pre",         "pclk_cpu_pre",
1148                                                 "reserved",             "aclk_core_pre",
1149
1150                                                 "reserved",             "clk_i2s_pll",
1151                                                 "i2s_frac",             "hclk_vio_pre",
1152
1153                                                 "clk_cryto",            "clk_i2s_out",
1154                                                 "clk_i2s",              "clk_testout";
1155                                         rockchip,suspend-clkgating-setting=<0x0 0x0>;
1156
1157                                         #clock-cells = <1>;
1158                                 };
1159
1160                                 clk_gates1: gate-clk@00d4{
1161                                         compatible = "rockchip,rk3188-gate-clk";
1162                                         reg = <0x00d4 0x4>;
1163                                         clocks =
1164                                                 <&clk_timer0>,          <&clk_timer1>,
1165                                                 <&dummy>,               <&jtag_tck>,
1166
1167                                                 <&aclk_vio_pre>,                <&xin12m>,
1168                                                 <&dummy>,               <&dummy>,
1169
1170                                                 <&clk_uart0_div>,               <&uart0_frac>,
1171                                                 <&clk_uart1_div>,               <&uart1_frac>,
1172
1173                                                 <&clk_uart2_div>,               <&uart2_frac>,
1174                                                 <&dummy>,               <&dummy>;
1175
1176                                         clock-output-names =
1177                                                 "clk_timer0",           "clk_timer1",
1178                                                 "reserved",             "clk_jatg",
1179
1180                                                 "aclk_vio_pre",         "clk_otgphy0",
1181                                                 "clk_otgphy1",                  "reserved",
1182
1183                                                 "clk_uart0_div",        "uart0_frac",
1184                                                 "clk_uart1_div",        "uart1_frac",
1185
1186                                                 "clk_uart2_div",        "uart2_frac",
1187                                                 "reserved",     "reserved";
1188
1189                                          rockchip,suspend-clkgating-setting=<0x0 0x0>;
1190                                         #clock-cells = <1>;
1191                                 };
1192
1193                                 clk_gates2: gate-clk@00d8 {
1194                                         compatible = "rockchip,rk3188-gate-clk";
1195                                         reg = <0x00d8 0x4>;
1196                                         clocks =
1197                                                 <&aclk_peri_pre>,               <&aclk_peri_pre>,
1198                                                 <&aclk_peri_pre>,               <&aclk_peri_pre>,
1199
1200                                                 <&clk_timer2>,          <&clk_timer3>,
1201                                                 <&clk_mac_ref>,         <&dummy>,
1202
1203                                                 <&dummy>,               <&clk_spi0>,
1204                                                 <&clk_spdif_pll>,               <&clk_sdmmc0>,
1205
1206                                                 <&spdif_frac>,          <&clk_sdio>,
1207                                                 <&clk_emmc>,            <&dummy>;
1208
1209                                         clock-output-names =
1210                                                 "aclk_peri",            "aclk_peri_pre",
1211                                                 "hclk_peri_pre",                "pclk_peri_pre",
1212
1213                                                 "clk_timer2",           "clk_timer3",
1214                                                 "clk_mac",              "reserved",
1215
1216                                                 "reserved",             "clk_spi0",
1217                                                 "clk_spdif_pll",                "clk_sdmmc0",
1218
1219                                                 "spdif_frac",           "clk_sdio",
1220                                                 "clk_emmc",             "reserved";
1221                                             rockchip,suspend-clkgating-setting=<0x0 0x0>;
1222
1223                                         #clock-cells = <1>;
1224                                 };
1225
1226                                 clk_gates3: gate-clk@00dc {
1227                                         compatible = "rockchip,rk3188-gate-clk";
1228                                         reg = <0x00dc 0x4>;
1229                                         clocks =
1230                                                 <&dummy>,               <&dummy>,
1231                                                 <&dclk_lcdc1>,          <&dummy>,
1232
1233                                                 <&dummy>,                       <&dummy>,
1234                                                 <&dummy>,               <&dummy>,
1235
1236                                                 <&pclk_cpu_pre>,                <&dummy>,
1237                                                 <&dummy>,               <&aclk_vcodec_pre>,
1238
1239                                                 <&aclk_vcodec_pre>,             <&clk_gpu_pre>,
1240                                                 <&hclk_peri_pre>,               <&dummy>;
1241
1242                                         clock-output-names =
1243                                                 "reserved",             "reserved",
1244                                                 "dclk_lcdc1",           "reserved",
1245
1246                                                 "reserved",             "reserved",
1247                                                 "reserved",             "reserved",
1248
1249                                                 "g_pclk_hdmi",          "reserved",
1250                                                 "reserved",             "aclk_vcodec_pre",
1251
1252                                                 "hclk_vcodec",          "clk_gpu_pre",
1253                                                 "g_hclk_sfc",           "reserved";
1254                                        rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1255
1256                                         #clock-cells = <1>;
1257                                 };
1258
1259                                 clk_gates4: gate-clk@00e0{
1260                                         compatible = "rockchip,rk3188-gate-clk";
1261                                         reg = <0x00e0 0x4>;
1262                                         clocks =
1263                                                 <&hclk_peri_pre>,               <&pclk_peri_pre>,
1264                                                 <&aclk_peri_pre>,               <&aclk_peri_pre>,
1265
1266                                                 <&dummy>,               <&dummy>,
1267                                                 <&dummy>,               <&dummy>,
1268
1269                                                 <&dummy>,               <&dummy>,
1270                                                 <&aclk_cpu_pre>,                <&dummy>,
1271
1272                                                 <&aclk_cpu_pre>,                <&dummy>,
1273                                                 <&dummy>,               <&dummy>;
1274
1275                                         clock-output-names =
1276                                                 "g_hp_axi_matrix",              "g_pp_axi_matrix",
1277                                                 "g_aclk_cpu_peri",              "g_ap_axi_matrix",
1278
1279                                                 "reserved",             "reserved",
1280                                                 "reserved",             "reserved",
1281
1282                                                 "reserved",             "reserved",
1283                                                 "g_aclk_strc_sys",              "reserved",
1284
1285                                                 /* Not use these ddr gates */
1286                                                 "g_aclk_intmem",                "reserved",
1287                                                 "reserved",             "reserved";
1288
1289                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1290                                         #clock-cells = <1>;
1291                                 };
1292
1293                                 clk_gates5: gate-clk@00e4 {
1294                                         compatible = "rockchip,rk3188-gate-clk";
1295                                         reg = <0x00e4 0x4>;
1296                                         clocks =
1297                                                 <&dummy>,               <&aclk_peri_pre>,
1298                                                 <&pclk_peri_pre>,               <&dummy>,
1299
1300                                                 <&pclk_cpu_pre>,                <&dummy>,
1301                                                 <&hclk_cpu_pre>,                <&pclk_cpu_pre>,
1302
1303                                                 <&dummy>,               <&hclk_peri_pre>,
1304                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1305
1306                                                 <&dummy>,               <&hclk_peri_pre>,
1307                                                 <&pclk_cpu_pre>,                <&dummy>;
1308
1309                                         clock-output-names =
1310                                                 "reserved",             "g_aclk_dmac2",
1311                                                 "g_pclk_efuse", "reserved",
1312
1313                                                 "g_pclk_grf",           "reserved",
1314                                                 "g_hclk_rom",           "g_pclk_ddrupctl",
1315
1316                                                 "reserved",             "g_hclk_nandc",
1317                                                 "g_hclk_sdmmc0",                "g_hclk_sdio",
1318
1319                                                 "reserved",             "g_hclk_otg0",
1320                                                 "g_pclk_acodec",                "reserved";
1321
1322                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1323
1324                                         #clock-cells = <1>;
1325                                 };
1326
1327                                 clk_gates6: gate-clk@00e8 {
1328                                         compatible = "rockchip,rk3188-gate-clk";
1329                                         reg = <0x00e8 0x4>;
1330                                         clocks =
1331                                                 <&dummy>,               <&dummy>,
1332                                                 <&dummy>,               <&dummy>,
1333
1334                                                 <&dummy>,               <&dummy>,
1335                                                 <&dummy>,               <&dummy>,
1336
1337                                                 <&dummy>,               <&dummy>,
1338                                                 <&dummy>,                       <&dummy>,
1339
1340                                                 <&hclk_vio_pre>,                <&aclk_vio_pre>,
1341                                                 <&dummy>,               <&dummy>;
1342
1343                                         clock-output-names =
1344                                                 "reserved",             "reserved",
1345                                                 "reserved",             "reserved",
1346
1347                                                 "reserved",             "reserved",
1348                                                 "reserved",             "reserved",
1349
1350                                                 "reserved",             "reserved",
1351                                                 "reserved",             "reserved",
1352
1353                                                 "g_hclk_vio_bus",               "g_aclk_vio",
1354                                                 "reserved",             "reserved";
1355
1356                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1357
1358                                         #clock-cells = <1>;
1359                                 };
1360
1361                                 clk_gates7: gate-clk@00ec {
1362                                         compatible = "rockchip,rk3188-gate-clk";
1363                                         reg = <0x00ec 0x4>;
1364                                         clocks =
1365                                                 <&hclk_peri_pre>,               <&dummy>,
1366                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1367
1368                                                 <&dummy>,               <&dummy>,
1369                                                 <&dummy>,               <&pclk_peri_pre>,
1370
1371                                                 <&dummy>,               <&dummy>,
1372                                                 <&pclk_peri_pre>,               <&dummy>,
1373
1374                                                 <&pclk_peri_pre>,               <&dummy>,
1375                                                 <&dummy>,               <&pclk_peri_pre>;
1376
1377                                         clock-output-names =
1378                                                 "g_hclk_emmc",          "reserved",
1379                                                 "g_hclk_i2s",           "g_hclk_otg1",
1380
1381                                                 "reserved",             "reserved",
1382                                                 "reserved",             "g_pclk_timer0",
1383
1384                                                 "reserved",             "reserved",
1385                                                 "g_pclk_pwm",           "reserved",
1386
1387                                                 "g_pclk_spi",           "reserved",
1388                                                 "reserved",             "g_pclk_wdt";
1389
1390                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1391
1392                                         #clock-cells = <1>;
1393                                 };
1394
1395                                 clk_gates8: gate-clk@00f0 {
1396                                         compatible = "rockchip,rk3188-gate-clk";
1397                                         reg = <0x00f0 0x4>;
1398                                         clocks =
1399                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1400                                                 <&pclk_peri_pre>,               <&dummy>,
1401
1402                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1403                                                 <&pclk_peri_pre>,               <&dummy>,
1404
1405                                                 <&dummy>,               <&pclk_peri_pre>,
1406                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1407
1408                                                 <&dummy>,               <&dummy>,
1409                                                 <&dummy>,               <&dummy>;
1410
1411                                         clock-output-names =
1412                                                 "g_pclk_uart0",         "g_pclk_uart1",
1413                                                 "g_pclk_uart2",         "reserved",
1414
1415                                                 "g_pclk_i2c0",          "g_pclk_i2c1",
1416                                                 "g_pclk_i2c2",          "reserved",
1417
1418                                                 "reserved",             "g_pclk_gpio0",
1419                                                 "g_pclk_gpio1",         "g_pclk_gpio2",
1420
1421                                                 "reserved",             "reserved",
1422                                                 "reserved",             "reserved";
1423
1424                                         rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1425                                         #clock-cells = <1>;
1426                                 };
1427
1428                                 clk_gates9: gate-clk@00f4 {
1429                                         compatible = "rockchip,rk3188-gate-clk";
1430                                         reg = <0x00f4 0x4>;
1431                                         clocks =
1432                                                 <&dummy>,               <&dummy>,
1433                                                 <&dummy>,               <&dummy>,
1434
1435                                                 <&dummy>,               <&hclk_vio_pre>,
1436                                                 <&aclk_vio_pre>,                <&dummy>,
1437
1438                                                 <&dummy>,               <&dummy>,
1439                                                 <&dummy>,               <&dummy>,
1440
1441                                                 <&dummy>,               <&hclk_peri_pre>,
1442                                                 <&hclk_peri_pre>,               <&aclk_peri_pre>;
1443
1444                                         clock-output-names =
1445                                                 "reserved",             "reserved",
1446                                                 "reserved",             "reserved",
1447
1448                                                 "reserved",             "g_hclk_lcdc",
1449                                                 "g_aclk_lcdc",          "reserved",
1450
1451                                                 "reserved",             "reserved",
1452                                                 "reserved",             "reserved",
1453
1454                                                 "reserved",             "g_hclk_usb_peri",
1455                                                 "g_hclk_pe_arbi",               "g_aclk_peri_niu";
1456
1457                                         rockchip,suspend-clkgating-setting=<0x0 0x0>;
1458
1459                                         #clock-cells = <1>;
1460                                 };
1461
1462                                 clk_gates10: gate-clk@00f8 {
1463                                         compatible = "rockchip,rk3188-gate-clk";
1464                                         reg = <0x00f8 0x4>;
1465                                         clocks =
1466                                                 <&xin24m>,              <&xin24m>,
1467                                                 <&xin24m>,              <&dummy>,
1468
1469                                                 <&clk_nandc>,           <&clk_sfc>,
1470                                                 <&clk_hevc_core>,               <&dummy>,
1471
1472                                                 <&clk_dpll>,            <&dummy>,
1473                                                 <&dummy>,               <&dummy>,
1474
1475                                                 <&dummy>,               <&dummy>,
1476                                                 <&dummy>,               <&dummy>;
1477
1478                                         clock-output-names =
1479                                                 "g_clk_pvtm_core",              "g_clk_pvtm_gpu",
1480                                                 "g_pvtm_video",         "reserved",
1481
1482                                                 "clk_nandc",            "clk_sfc",
1483                                                 "clk_hevc_core",                "reserved",
1484
1485                                                 "reserved",             "reserved",
1486                                                 "reserved",             "reserved",
1487
1488                                                 "reserved",             "reserved",
1489                                                 "reserved",             "reserved";
1490
1491                                         rockchip,suspend-clkgating-setting = <0x0 0x0>; /* pwm logic vol */
1492
1493                                         #clock-cells = <1>;
1494                                 };
1495
1496                         };
1497                 };
1498         };
1499 };