2 * Copyright (C) 2014 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <dt-bindings/clock/rockchip,rk3036.h>
19 compatible = "rockchip,rk-clocks";
22 ranges = <0x0 0x20000000 0x1f0>;
25 compatible = "rockchip,rk-fixed-rate-cons";
28 compatible = "rockchip,rk-fixed-clock";
29 clock-output-names = "xin24m";
30 clock-frequency = <24000000>;
35 compatible = "rockchip,rk-fixed-clock";
37 clock-output-names = "xin12m";
38 clock-frequency = <12000000>;
42 rmii_clkin: rmii_clkin {
43 compatible = "rockchip,rk-fixed-clock";
44 clock-output-names = "rmii_clkin";
45 clock-frequency = <50000000>;
50 compatible = "rockchip,rk-fixed-clock";
51 clock-output-names = "usb_480m";
52 clock-frequency = <480000000>;
56 i2s_clkin: i2s_clkin {
57 compatible = "rockchip,rk-fixed-clock";
58 clock-output-names = "i2s_clkin";
59 clock-frequency = <0>;
64 compatible = "rockchip,rk-fixed-clock";
65 clock-output-names = "jtag_tck";
66 clock-frequency = <0>;
71 compatible = "rockchip,rk-fixed-clock";
72 clock-output-names = "dummy";
73 clock-frequency = <0>;
77 dummy_cpll: dummy_cpll {
78 compatible = "rockchip,rk-fixed-clock";
79 clock-output-names = "dummy_cpll";
80 clock-frequency = <0>;
87 compatible = "rockchip,rk-fixed-factor-cons";
89 otgphy0_12m: otgphy0_12m {
90 compatible = "rockchip,rk-fixed-factor-clock";
91 clocks = <&clk_gates1 5>;
92 clock-output-names = "otgphy0_12m";
98 hclk_vcodec: hclk_vcodec {
99 compatible = "rockchip,rk-fixed-factor-clock";
100 clocks = <&aclk_vcodec_pre>;
101 clock-output-names = "hclk_vcodec";
107 io_mac_mdclkout: io_mac_mdclkout {
108 compatible = "rockchip,rk-fixed-factor-clock";
109 clocks = <&aclk_peri_pre>;
110 clock-output-names = "io_mac_mdclkout";
118 compatible = "rockchip,rk-clock-regs";
119 #address-cells = <1>;
121 reg = <0x0000 0x01f0>;
124 /* PLL control regs */
126 compatible = "rockchip,rk-pll-cons";
127 #address-cells = <1>;
131 clk_apll: pll-clk@0000 {
132 compatible = "rockchip,rk3188-pll-clk";
134 mode-reg = <0x0040 0>;
135 status-reg = <0x0004 10>;
137 clock-output-names = "clk_apll";
138 rockchip,pll-type = <CLK_PLL_3036_APLL>;
142 clk_dpll: pll-clk@0010 {
143 compatible = "rockchip,rk3188-pll-clk";
145 mode-reg = <0x0040 4>;
146 status-reg = <0x0014 10>;
148 clock-output-names = "clk_dpll";
149 rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
153 clk_gpll: pll-clk@0030 {
154 compatible = "rockchip,rk3188-pll-clk";
156 mode-reg = <0x0040 12>;
157 status-reg = <0x0034 10>;
159 clock-output-names = "clk_gpll";
160 rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
162 #clock-init-cells = <1>;
167 /* Select control regs */
169 compatible = "rockchip,rk-sel-cons";
170 #address-cells = <1>;
174 clk_sel_con0: sel-con@0044 {
175 compatible = "rockchip,rk3188-selcon";
177 #address-cells = <1>;
180 clk_core_div: clk_core_div {
181 compatible = "rockchip,rk3188-div-con";
182 rockchip,bits = <0 5>;
183 clocks = <&clk_core>;
184 clock-output-names = "clk_core";
185 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
187 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
188 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
189 CLK_SET_RATE_NO_REPARENT)>;
192 /* reg[6:5]: reserved */
194 clk_core: clk_core_mux {
195 compatible = "rockchip,rk3188-mux-con";
196 rockchip,bits = <7 1>;
197 clocks = <&clk_apll>, <&clk_gates0 6>;
198 clock-output-names = "clk_core";
200 #clock-init-cells = <1>;
203 aclk_cpu_pre_div: aclk_cpu_pre_div {
204 compatible = "rockchip,rk3188-div-con";
205 rockchip,bits = <8 5>;
206 clocks = <&aclk_cpu_pre>;
207 clock-output-names = "aclk_cpu_pre";
208 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
210 rockchip,clkops-idx =
211 <CLKOPS_RATE_MUX_DIV>;
212 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
215 /* reg[13]: reserved */
217 aclk_cpu_pre: aclk_cpu_pre_mux {
218 compatible = "rockchip,rk3188-mux-con";
219 rockchip,bits = <14 2>;
220 clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>;
221 clock-output-names = "aclk_cpu_pre";
223 #clock-init-cells = <1>;
228 clk_sel_con1: sel-con@0048 {
229 compatible = "rockchip,rk3188-selcon";
231 #address-cells = <1>;
234 pclk_dbg_div: pclk_dbg_div {
235 compatible = "rockchip,rk3188-div-con";
236 rockchip,bits = <0 4>;
237 clocks = <&clk_core>;
238 clock-output-names = "pclk_dbg";
239 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
241 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
244 aclk_core_pre: aclk_core_pre_div {
245 compatible = "rockchip,rk3188-div-con";
246 rockchip,bits = <4 3>;
247 clocks = <&clk_core>;
248 clock-output-names = "aclk_core_pre";
249 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
251 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
254 /* reg[7]: reserved */
256 hclk_cpu_pre: hclk_cpu_pre_div {
257 compatible = "rockchip,rk3188-div-con";
258 rockchip,bits = <8 2>;
259 clocks = <&aclk_cpu_pre>;
260 clock-output-names = "hclk_cpu_pre";
261 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
263 #clock-init-cells = <1>;
266 /* reg[11:10]: reserved */
268 pclk_cpu_pre: pclk_cpu_pre_div {
269 compatible = "rockchip,rk3188-div-con";
270 rockchip,bits = <12 3>;
271 clocks = <&aclk_cpu_pre>;
272 clock-output-names = "pclk_cpu_pre";
273 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
275 #clock-init-cells = <1>;
278 /* reg[15]: reserved */
281 clk_sel_con2: sel-con@004c {
282 compatible = "rockchip,rk3188-selcon";
284 #address-cells = <1>;
287 /* reg[3:0]: reserved */
289 clk_timer0: clk_timer0_mux {
290 compatible = "rockchip,rk3188-mux-con";
291 rockchip,bits = <4 1>;
292 clocks = <&xin24m>, <&aclk_peri_pre>;
293 clock-output-names = "clk_timer0";
295 #clock-init-cells = <1>;
298 clk_timer1: clk_timer1_mux {
299 compatible = "rockchip,rk3188-mux-con";
300 rockchip,bits = <5 1>;
301 clocks = <&xin24m>, <&aclk_peri_pre>;
302 clock-output-names = "clk_timer1";
304 #clock-init-cells = <1>;
307 clk_timer2: clk_timer2_mux {
308 compatible = "rockchip,rk3188-mux-con";
309 rockchip,bits = <6 1>;
310 clocks = <&xin24m>, <&aclk_peri_pre>;
311 clock-output-names = "clk_timer2";
313 #clock-init-cells = <1>;
316 clk_timer3: clk_timer3_mux {
317 compatible = "rockchip,rk3188-mux-con";
318 rockchip,bits = <7 1>;
319 clocks = <&xin24m>, <&aclk_peri_pre>;
320 clock-output-names = "clk_timer3";
322 #clock-init-cells = <1>;
325 /* reg[15:8]: reserved */
328 clk_sel_con3: sel-con@0050 {
329 compatible = "rockchip,rk3188-selcon";
331 #address-cells = <1>;
334 clk_i2s_pll_div: clk_i2s_pll_div {
335 compatible = "rockchip,rk3188-div-con";
336 rockchip,bits = <0 7>;
337 clocks = <&clk_i2s_pll>;
338 clock-output-names = "clk_i2s_pll";
339 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
341 rockchip,clkops-idx =
342 <CLKOPS_RATE_MUX_DIV>;
343 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
346 /* reg[7]: reserved */
348 clk_i2s: clk_i2s_mux {
349 compatible = "rockchip,rk3188-mux-con";
350 rockchip,bits = <8 2>;
351 clocks = <&clk_i2s_pll_div>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
352 clock-output-names = "clk_i2s";
354 rockchip,clkops-idx =
355 <CLKOPS_RATE_RK3288_I2S>;
356 rockchip,flags = <CLK_SET_RATE_PARENT>;
359 /* reg[11:10]: reserved */
361 clk_i2s_out: i2s_outclk_mux {
362 compatible = "rockchip,rk3188-mux-con";
363 rockchip,bits = <12 1>;
364 clocks = <&xin12m>, <&clk_i2s>;
365 clock-output-names = "i2s_clkout";
369 /* reg[13]: reserved */
371 clk_i2s_pll: i2s_pll_mux {
372 compatible = "rockchip,rk3188-mux-con";
373 rockchip,bits = <14 2>;
374 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
375 clock-output-names = "clk_i2s_pll";
377 #clock-init-cells = <1>;
382 clk_sel_con5: sel-con@0058 {
383 compatible = "rockchip,rk3188-selcon";
385 #address-cells = <1>;
388 spdif_div: spdif_div {
389 compatible = "rockchip,rk3188-div-con";
390 rockchip,bits = <0 7>;
391 clocks = <&clk_spdif_pll>;
392 clock-output-names = "clk_spdif_pll";
393 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
395 rockchip,clkops-idx =
396 <CLKOPS_RATE_MUX_DIV>;
397 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
400 /* reg[7]: reserved */
402 clk_spdif: spdif_mux {
403 compatible = "rockchip,rk3188-mux-con";
404 rockchip,bits = <8 2>;
405 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
406 clock-output-names = "clk_spdif";
408 rockchip,clkops-idx =
409 <CLKOPS_RATE_RK3288_I2S>;
410 rockchip,flags = <CLK_SET_RATE_PARENT>;
413 clk_spdif_pll: spdif_pll_mux {
414 compatible = "rockchip,rk3188-mux-con";
415 rockchip,bits = <10 2>;
416 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
417 clock-output-names = "clk_spdif_pll";
419 #clock-init-cells = <1>;
422 /* reg[15:12]: reserved */
425 clk_sel_con7: sel-con@0060 {
426 compatible = "rockchip,rk3188-selcon";
428 #address-cells = <1>;
432 compatible = "rockchip,rk3188-frac-con";
433 clocks = <&clk_i2s_pll>;
434 clock-output-names = "i2s_frac";
435 /* numerator denominator */
436 rockchip,bits = <0 32>;
437 rockchip,clkops-idx =
443 clk_sel_con9: sel-con@0068 {
444 compatible = "rockchip,rk3188-selcon";
446 #address-cells = <1>;
449 spdif_frac: spdif_frac {
450 compatible = "rockchip,rk3188-frac-con";
451 clocks = <&spdif_div>;
452 clock-output-names = "spdif_frac";
453 /* numerator denominator */
454 rockchip,bits = <0 32>;
455 rockchip,clkops-idx =
461 clk_sel_con10: sel-con@006c {
462 compatible = "rockchip,rk3188-selcon";
464 #address-cells = <1>;
467 aclk_peri_pre_div: aclk_peri_pre_div {
468 compatible = "rockchip,rk3188-div-con";
469 rockchip,bits = <0 5>;
470 clocks = <&aclk_peri_pre>;
471 clock-output-names = "aclk_peri_pre";
472 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
474 rockchip,clkops-idx =
475 <CLKOPS_RATE_MUX_DIV>;
476 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
479 /* reg[7:5]: reserved */
481 hclk_peri_pre: hclk_peri_pre_div {
482 compatible = "rockchip,rk3188-div-con";
483 rockchip,bits = <8 2>;
484 clocks = <&aclk_peri_pre>;
485 clock-output-names = "hclk_peri_pre";
486 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
487 rockchip,div-relations =
492 #clock-init-cells = <1>;
495 /* reg[11:10]: reserved */
497 pclk_peri_pre: pclk_peri_div {
498 compatible = "rockchip,rk3188-div-con";
499 rockchip,bits = <12 2>;
500 clocks = <&aclk_peri_pre>;
501 clock-output-names = "pclk_peri_pre";
502 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
503 rockchip,div-relations =
509 #clock-init-cells = <1>;
512 aclk_peri_pre: aclk_peri_pre_mux {
513 compatible = "rockchip,rk3188-mux-con";
514 rockchip,bits = <14 2>;
515 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
516 clock-output-names = "aclk_peri_pre";
518 #clock-init-cells = <1>;
522 clk_sel_con11: sel-con@0070 {
523 compatible = "rockchip,rk3188-selcon";
525 #address-cells = <1>;
528 clk_sdmmc0_div: clk_sdmmc0_div {
529 compatible = "rockchip,rk3188-div-con";
530 rockchip,bits = <0 6>;
531 clocks = <&clk_sdmmc0>;
532 clock-output-names = "clk_sdmmc0";
533 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
535 rockchip,clkops-idx =
536 <CLKOPS_RATE_MUX_EVENDIV>;
539 /* reg[7]: reserved */
541 clk_sdio_div: clk_sdio_div {
542 compatible = "rockchip,rk3188-div-con";
543 rockchip,bits = <8 7>;
544 clocks = <&clk_sdio>;
545 clock-output-names = "clk_sdio";
546 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
548 rockchip,clkops-idx =
549 <CLKOPS_RATE_MUX_EVENDIV>;
552 /* reg[15]: reserved */
556 clk_sel_con12: sel-con@0074 {
557 compatible = "rockchip,rk3188-selcon";
559 #address-cells = <1>;
562 clk_emmc_div: clk_emmc_div {
563 compatible = "rockchip,rk3188-div-con";
564 rockchip,bits = <0 7>;
565 clocks = <&clk_emmc>;
566 clock-output-names = "clk_emmc";
567 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
569 rockchip,clkops-idx =
570 <CLKOPS_RATE_MUX_EVENDIV>;
573 /* reg[7]: reserved */
575 clk_sdmmc0: clk_sdmmc0_mux {
576 compatible = "rockchip,rk3188-mux-con";
577 rockchip,bits = <8 2>;
578 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
579 clock-output-names = "clk_sdmmc0";
583 clk_sdio: clk_sdio_mux {
584 compatible = "rockchip,rk3188-mux-con";
585 rockchip,bits = <10 2>;
586 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
587 clock-output-names = "clk_sdio";
591 clk_emmc: clk_emmc_mux {
592 compatible = "rockchip,rk3188-mux-con";
593 rockchip,bits = <12 2>;
594 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
595 clock-output-names = "clk_emmc";
599 /* reg[15:14]: reserved */
602 clk_sel_con13: sel-con@0078 {
603 compatible = "rockchip,rk3188-selcon";
605 #address-cells = <1>;
608 clk_uart0_div: clk_uart0_div {
609 compatible = "rockchip,rk3188-div-con";
610 rockchip,bits = <0 7>;
611 clocks = <&clk_uart_pll>;
612 clock-output-names = "clk_uart0_div";
613 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
617 /* reg[7]: reserved */
619 clk_uart0: clk_uart0_mux {
620 compatible = "rockchip,rk3188-mux-con";
621 rockchip,bits = <8 2>;
622 clocks = <&clk_uart0_div>, <&uart0_frac>, <&xin24m>;
623 clock-output-names = "clk_uart0";
625 rockchip,clkops-idx =
626 <CLKOPS_RATE_RK3288_I2S>;
627 rockchip,flags = <CLK_SET_RATE_PARENT>;
630 clk_uart_pll: clk_uart_pll_mux {
631 compatible = "rockchip,rk3188-mux-con";
632 rockchip,bits = <10 2>;
633 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&usb_480m>;
634 clock-output-names = "clk_uart_pll";
636 #clock-init-cells = <1>;
639 /* reg[15:12]: reserved */
643 clk_sel_con14: sel-con@007c {
644 compatible = "rockchip,rk3188-selcon";
646 #address-cells = <1>;
649 clk_uart1_div: clk_uart1_div {
650 compatible = "rockchip,rk3188-div-con";
651 rockchip,bits = <0 7>;
652 clocks = <&clk_uart_pll>;
653 clock-output-names = "clk_uart1_div";
654 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
658 /* reg[7]: reserved */
660 clk_uart1: clk_uart1_mux {
661 compatible = "rockchip,rk3188-mux-con";
662 rockchip,bits = <8 2>;
663 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
664 clock-output-names = "clk_uart1";
666 rockchip,clkops-idx =
667 <CLKOPS_RATE_RK3288_I2S>;
668 rockchip,flags = <CLK_SET_RATE_PARENT>;
671 /* reg[15:10]: reserved */
674 clk_sel_con15: sel-con@0080 {
675 compatible = "rockchip,rk3188-selcon";
677 #address-cells = <1>;
680 clk_uart2_div: clk_uart2_div {
681 compatible = "rockchip,rk3188-div-con";
682 rockchip,bits = <0 7>;
683 clocks = <&clk_uart_pll>;
684 clock-output-names = "clk_uart2_div";
685 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
689 /* reg[7]: reserved */
691 clk_uart2: clk_uart2_mux {
692 compatible = "rockchip,rk3188-mux-con";
693 rockchip,bits = <8 2>;
694 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
695 clock-output-names = "clk_uart2";
697 rockchip,clkops-idx =
698 <CLKOPS_RATE_RK3288_I2S>;
699 rockchip,flags = <CLK_SET_RATE_PARENT>;
702 /* reg[15:10]: reserved */
705 clk_sel_con16: sel-con@0084 {
706 compatible = "rockchip,rk3188-selcon";
708 #address-cells = <1>;
711 clk_sfc: clk_sfc_mux {
712 compatible = "rockchip,rk3188-mux-con";
713 rockchip,bits = <0 2>;
714 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>, <&xin24m>;
715 clock-output-names = "clk_sfc";
719 clk_sfc_div: clk_sfc_div {
720 compatible = "rockchip,rk3188-div-con";
721 rockchip,bits = <2 5>;
723 clock-output-names = "clk_sfc";
724 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
726 rockchip,clkops-idx =
727 <CLKOPS_RATE_MUX_DIV>;
730 /* reg[7]: reserved */
732 clk_nandc: clk_nandc_mux {
733 compatible = "rockchip,rk3188-mux-con";
734 rockchip,bits = <8 2>;
735 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
736 clock-output-names = "clk_nandc";
740 clk_nandc_div: clk_nandc_div {
741 compatible = "rockchip,rk3188-div-con";
742 rockchip,bits = <10 5>;
743 clocks = <&clk_nandc>;
744 clock-output-names = "clk_nandc";
745 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
747 rockchip,clkops-idx =
748 <CLKOPS_RATE_MUX_DIV>;
751 /* reg[31:15]: reserved */
754 clk_sel_con17: sel-con@0088 {
755 compatible = "rockchip,rk3188-selcon";
757 #address-cells = <1>;
760 uart0_frac: uart0_frac {
761 compatible = "rockchip,rk3188-frac-con";
762 clocks = <&clk_uart0_div>;
763 clock-output-names = "uart0_frac";
764 /* numerator denominator */
765 rockchip,bits = <0 32>;
766 rockchip,clkops-idx =
772 clk_sel_con18: sel-con@008c {
773 compatible = "rockchip,rk3188-selcon";
775 #address-cells = <1>;
778 uart1_frac: uart1_frac {
779 compatible = "rockchip,rk3188-frac-con";
780 clocks = <&clk_uart1_div>;
781 clock-output-names = "uart1_frac";
782 /* numerator denominator */
783 rockchip,bits = <0 32>;
784 rockchip,clkops-idx =
790 clk_sel_con19: sel-con@0090 {
791 compatible = "rockchip,rk3188-selcon";
793 #address-cells = <1>;
796 uart2_frac: uart2_frac {
797 compatible = "rockchip,rk3188-frac-con";
798 clocks = <&clk_uart2_div>;
799 clock-output-names = "uart2_frac";
800 /* numerator denominator */
801 rockchip,bits = <0 32>;
802 rockchip,clkops-idx =
809 clk_sel_con20: sel-con@0094 {
810 compatible = "rockchip,rk3188-selcon";
812 #address-cells = <1>;
815 clk_hevc_core: clk_hevc_core_mux {
816 compatible = "rockchip,rk3188-mux-con";
817 rockchip,bits = <0 2>;
818 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
819 clock-output-names = "clk_hevc_core";
821 #clock-init-cells = <1>;
824 clk_hevc_core_div: clk_hevc_core_div {
825 compatible = "rockchip,rk3188-div-con";
826 rockchip,bits = <2 5>;
827 clocks = <&clk_hevc_core>;
828 clock-output-names = "clk_hevc_core";
829 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
831 rockchip,clkops-idx =
832 <CLKOPS_RATE_MUX_DIV>;
833 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
836 /* reg[31:7]: reserved */
840 clk_sel_con21: sel-con@0098 {
841 compatible = "rockchip,rk3188-selcon";
843 #address-cells = <1>;
846 clk_mac_pll: clk_mac_pll_mux {
847 compatible = "rockchip,rk3188-mux-con";
848 rockchip,bits = <0 2>;
849 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
850 clock-output-names = "clk_mac_pll";
852 #clock-init-cells = <1>;
855 /* reg[2]: reserved */
857 clk_mac_ref: clk_mac_ref_mux {
858 compatible = "rockchip,rk3188-mux-con";
859 rockchip,bits = <3 1>;
860 clocks = <&clk_mac_pll_div>, <&rmii_clkin>;
861 clock-output-names = "clk_mac_ref";
863 rockchip,clkops-idx =
864 <CLKOPS_RATE_MAC_REF>;
865 rockchip,flags = <CLK_SET_RATE_PARENT>;
866 #clock-init-cells = <1>;
869 clk_mac_ref_div: clk_mac_ref_div {
870 compatible = "rockchip,rk3188-div-con";
871 rockchip,bits = <4 5>;
872 clocks = <&clk_mac_ref>;
873 clock-output-names = "clk_mac";
874 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
876 #clock-init-cells = <1>;
879 clk_mac_pll_div: clk_mac_pll_div {
880 compatible = "rockchip,rk3188-div-con";
881 rockchip,bits = <9 5>;
882 clocks = <&clk_mac_pll>;
883 clock-output-names = "clk_mac_pll";
884 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
886 rockchip,clkops-idx =
887 <CLKOPS_RATE_MUX_DIV>;
888 #clock-init-cells = <1>;
891 /* reg[15:14]: reserved */
894 clk_sel_con25: sel-con@00a8 {
895 compatible = "rockchip,rk3188-selcon";
897 #address-cells = <1>;
900 clk_spi0_div: clk_spi0_div {
901 compatible = "rockchip,rk3188-div-con";
902 rockchip,bits = <0 7>;
903 clocks = <&clk_spi0>;
904 clock-output-names = "clk_spi0";
905 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
907 rockchip,clkops-idx =
908 <CLKOPS_RATE_MUX_DIV>;
911 /* reg[7]: reserved */
913 clk_spi0: clk_spi0_mux {
914 compatible = "rockchip,rk3188-mux-con";
915 rockchip,bits = <8 2>;
916 clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>;
917 clock-output-names = "clk_spi0";
921 /* reg[15:10]: reserved */
925 clk_sel_con26: sel-con@00ac {
926 compatible = "rockchip,rk3188-selcon";
928 #address-cells = <1>;
932 compatible = "rockchip,rk3188-div-con";
933 rockchip,bits = <0 2>;
935 clock-output-names = "clk_ddr";
936 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
937 rockchip,div-relations =
942 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
943 CLK_SET_RATE_NO_REPARENT)>;
944 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
947 /* reg[7:1]: reserved */
949 clk_ddr: ddr_clk_pll_mux {
950 compatible = "rockchip,rk3188-mux-con";
951 rockchip,bits = <8 1>;
952 clocks = <&clk_dpll>, <&dummy>;
953 clock-output-names = "clk_ddr";
957 /* reg[15:9]: reserved */
960 clk_sel_con28: sel-con@00b4 {
961 compatible = "rockchip,rk3188-selcon";
963 #address-cells = <1>;
966 dclk_lcdc1: dclk_lcdc1_mux {
967 compatible = "rockchip,rk3188-mux-con";
968 rockchip,bits = <0 2>;
969 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
970 clock-output-names = "dclk_lcdc1";
972 #clock-init-cells = <1>;
975 /* reg[7:2]: reserved */
977 dclk_lcdc1_div: dclk_lcdc1_div {
978 compatible = "rockchip,rk3188-div-con";
979 rockchip,bits = <8 8>;
980 clocks = <&dclk_lcdc1>;
981 clock-output-names = "dclk_lcdc1";
982 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
984 rockchip,clkops-idx =
985 <CLKOPS_RATE_MUX_DIV>;
986 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
990 clk_sel_con30: sel-con@00bc {
991 compatible = "rockchip,rk3188-selcon";
993 #address-cells = <1>;
996 clk_testout_div: clk_testout_div {
997 compatible = "rockchip,rk3188-div-con";
998 rockchip,bits = <0 5>;
1000 clock-output-names = "clk_testout";
1001 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1003 #clock-init-cells = <1>;
1006 /* reg[7:5]: reserved */
1008 hclk_vio_pre_div: hclk_vio_pre_div {
1009 compatible = "rockchip,rk3188-div-con";
1010 rockchip,bits = <8 5>;
1011 clocks = <&hclk_vio_pre>;
1012 clock-output-names = "hclk_vio_pre";
1013 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1015 rockchip,clkops-idx =
1016 <CLKOPS_RATE_MUX_DIV>;
1017 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1020 /* reg[13]: reserved */
1022 hclk_vio_pre: hclk_vio_pre_mux {
1023 compatible = "rockchip,rk3188-mux-con";
1024 rockchip,bits = <14 2>;
1025 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1026 clock-output-names = "hclk_vio_pre";
1028 #clock-init-cells = <1>;
1033 clk_sel_con31: sel-con@00c0 {
1034 compatible = "rockchip,rk3188-selcon";
1036 #address-cells = <1>;
1039 clk_hdmi: clk_hdmi_mux {
1040 compatible = "rockchip,rk3188-mux-con";
1041 rockchip,bits = <0 1>;
1042 clocks = <&dclk_lcdc1_div>, <&dummy>;
1043 clock-output-names = "clk_hdmi";
1047 /* reg[7:1]: reserved */
1049 aclk_vio_pre_div: aclk_vio_pre_div {
1050 compatible = "rockchip,rk3188-div-con";
1051 rockchip,bits = <8 5>;
1052 clocks = <&aclk_vio_pre>;
1053 clock-output-names = "aclk_vio_pre";
1054 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1056 rockchip,clkops-idx =
1057 <CLKOPS_RATE_MUX_DIV>;
1058 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1061 /* reg[13]: reserved */
1063 aclk_vio_pre: aclk_vio_pre_mux {
1064 compatible = "rockchip,rk3188-mux-con";
1065 rockchip,bits = <14 2>;
1066 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1067 clock-output-names = "aclk_vio_pre";
1069 #clock-init-cells = <1>;
1074 clk_sel_con32: sel-con@00c4 {
1075 compatible = "rockchip,rk3188-selcon";
1077 #address-cells = <1>;
1080 /* reg[7:0]: reserved */
1082 aclk_vcodec_pre_div: aclk_vcodec_pre_div {
1083 compatible = "rockchip,rk3188-div-con";
1084 rockchip,bits = <8 5>;
1085 clocks = <&aclk_vcodec_pre>;
1086 clock-output-names = "aclk_vcodec_pre";
1087 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1089 rockchip,clkops-idx =
1090 <CLKOPS_RATE_MUX_DIV>;
1091 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1094 /* reg[13]: reserved */
1096 aclk_vcodec_pre: aclk_vcodec_pre_mux {
1097 compatible = "rockchip,rk3188-mux-con";
1098 rockchip,bits = <14 2>;
1099 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1100 clock-output-names = "aclk_vcodec_pre";
1102 #clock-init-cells = <1>;
1106 clk_sel_con34: sel-con@00cc {
1107 compatible = "rockchip,rk3188-selcon";
1109 #address-cells = <1>;
1112 clk_gpu_div: clk_gpu_div {
1113 compatible = "rockchip,rk3188-div-con";
1114 rockchip,bits = <0 5>;
1115 clocks = <&clk_gpu>;
1116 clock-output-names = "clk_gpu";
1117 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1119 rockchip,clkops-idx =
1120 <CLKOPS_RATE_MUX_DIV>;
1121 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1124 /* reg[7:5]: reserved */
1126 clk_gpu: clk_gpu_mux {
1127 compatible = "rockchip,rk3188-mux-con";
1128 rockchip,bits = <8 2>;
1129 clocks = <&dummy>, <&dummy>, <&clk_gpll>;
1130 clock-output-names = "clk_gpu";
1132 #clock-init-cells = <1>;
1135 /* reg[15:10]: reserved */
1142 /* Gate control regs */
1144 compatible = "rockchip,rk-gate-cons";
1145 #address-cells = <1>;
1149 clk_gates0: gate-clk@00d0{
1150 compatible = "rockchip,rk3188-gate-clk";
1153 <&clk_core>, <&clk_gpll>,
1154 <&clk_dpll>, <&aclk_cpu_pre>,
1156 <&aclk_cpu_pre>, <&aclk_cpu_pre>,
1157 <&clk_gpll>, <&clk_core>,
1159 <&clk_gpll>, <&clk_i2s_pll>,
1160 <&i2s_frac>, <&hclk_vio_pre>,
1162 <&dummy>, <&clk_i2s_out>,
1163 <&clk_i2s>, <&dummy>;
1165 clock-output-names =
1166 "pclk_dbg", "reserved", /* do not use bit1 = "cpu_gpll" */
1167 "reserved", "aclk_cpu_pre",
1169 "hclk_cpu_pre", "pclk_cpu_pre",
1170 "reserved", "aclk_core_pre",
1172 "reserved", "clk_i2s_pll",
1173 "i2s_frac", "hclk_vio_pre",
1175 "clk_cryto", "clk_i2s_out",
1176 "clk_i2s", "clk_testout";
1177 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1182 clk_gates1: gate-clk@00d4{
1183 compatible = "rockchip,rk3188-gate-clk";
1186 <&clk_timer0>, <&clk_timer1>,
1187 <&dummy>, <&jtag_tck>,
1189 <&aclk_vio_pre>, <&xin12m>,
1192 <&clk_uart0_div>, <&uart0_frac>,
1193 <&clk_uart1_div>, <&uart1_frac>,
1195 <&clk_uart2_div>, <&uart2_frac>,
1198 clock-output-names =
1199 "clk_timer0", "clk_timer1",
1200 "reserved", "clk_jatg",
1202 "aclk_vio_pre", "clk_otgphy0",
1203 "clk_otgphy1", "reserved",
1205 "clk_uart0_div", "uart0_frac",
1206 "clk_uart1_div", "uart1_frac",
1208 "clk_uart2_div", "uart2_frac",
1209 "reserved", "reserved";
1211 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1215 clk_gates2: gate-clk@00d8 {
1216 compatible = "rockchip,rk3188-gate-clk";
1219 <&aclk_peri_pre>, <&aclk_peri_pre>,
1220 <&aclk_peri_pre>, <&aclk_peri_pre>,
1222 <&clk_timer2>, <&clk_timer3>,
1223 <&clk_mac_ref>, <&dummy>,
1225 <&dummy>, <&clk_spi0>,
1226 <&clk_spdif_pll>, <&clk_sdmmc0>,
1228 <&spdif_frac>, <&clk_sdio>,
1229 <&clk_emmc>, <&dummy>;
1231 clock-output-names =
1232 "aclk_peri", "aclk_peri_pre",
1233 "hclk_peri_pre", "pclk_peri_pre",
1235 "clk_timer2", "clk_timer3",
1236 "clk_mac", "reserved",
1238 "reserved", "clk_spi0",
1239 "clk_spdif_pll", "clk_sdmmc0",
1241 "spdif_frac", "clk_sdio",
1242 "clk_emmc", "reserved";
1243 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1248 clk_gates3: gate-clk@00dc {
1249 compatible = "rockchip,rk3188-gate-clk";
1253 <&dclk_lcdc1>, <&dummy>,
1255 <&dummy>, <&hclk_peri_pre>,
1258 <&pclk_cpu_pre>, <&dummy>,
1259 <&dummy>, <&aclk_vcodec_pre>,
1261 <&aclk_vcodec_pre>, <&clk_gpu>,
1262 <&hclk_peri_pre>, <&dummy>;
1264 clock-output-names =
1265 "reserved", "reserved",
1266 "dclk_lcdc1", "reserved",
1268 "reserved", "g_hclk_mac",
1269 "reserved", "reserved",
1271 "g_pclk_hdmi", "reserved",
1272 "reserved", "aclk_vcodec_pre",
1274 "hclk_vcodec", "clk_gpu",
1275 "g_hclk_sfc", "reserved";
1276 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1281 clk_gates4: gate-clk@00e0{
1282 compatible = "rockchip,rk3188-gate-clk";
1285 <&hclk_peri_pre>, <&pclk_peri_pre>,
1286 <&aclk_peri_pre>, <&aclk_peri_pre>,
1292 <&aclk_cpu_pre>, <&dummy>,
1294 <&aclk_cpu_pre>, <&dummy>,
1297 clock-output-names =
1298 "g_hp_axi_matrix", "g_pp_axi_matrix",
1299 "g_aclk_cpu_peri", "g_ap_axi_matrix",
1301 "reserved", "g_hclk_mac",
1302 "reserved", "reserved",
1304 "reserved", "reserved",
1305 "g_aclk_strc_sys", "reserved",
1307 /* Not use these ddr gates */
1308 "g_aclk_intmem", "reserved",
1309 "reserved", "reserved";
1311 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1315 clk_gates5: gate-clk@00e4 {
1316 compatible = "rockchip,rk3188-gate-clk";
1319 <&dummy>, <&aclk_peri_pre>,
1320 <&pclk_peri_pre>, <&dummy>,
1322 <&pclk_cpu_pre>, <&dummy>,
1323 <&hclk_cpu_pre>, <&pclk_cpu_pre>,
1325 <&dummy>, <&hclk_peri_pre>,
1326 <&hclk_peri_pre>, <&hclk_peri_pre>,
1328 <&dummy>, <&hclk_peri_pre>,
1329 <&pclk_cpu_pre>, <&dummy>;
1331 clock-output-names =
1332 "reserved", "g_aclk_dmac2",
1333 "g_pclk_efuse", "reserved",
1335 "g_pclk_grf", "reserved",
1336 "g_hclk_rom", "g_pclk_ddrupctl",
1338 "reserved", "g_hclk_nandc",
1339 "g_hclk_sdmmc0", "g_hclk_sdio",
1341 "reserved", "g_hclk_otg0",
1342 "g_pclk_acodec", "reserved";
1344 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1349 clk_gates6: gate-clk@00e8 {
1350 compatible = "rockchip,rk3188-gate-clk";
1362 <&hclk_vio_pre>, <&aclk_vio_pre>,
1365 clock-output-names =
1366 "reserved", "reserved",
1367 "reserved", "reserved",
1369 "reserved", "reserved",
1370 "reserved", "reserved",
1372 "reserved", "reserved",
1373 "reserved", "reserved",
1375 "g_hclk_vio_bus", "g_aclk_vio",
1376 "reserved", "reserved";
1378 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1383 clk_gates7: gate-clk@00ec {
1384 compatible = "rockchip,rk3188-gate-clk";
1387 <&hclk_peri_pre>, <&dummy>,
1388 <&hclk_peri_pre>, <&hclk_peri_pre>,
1391 <&dummy>, <&pclk_peri_pre>,
1394 <&pclk_peri_pre>, <&dummy>,
1396 <&pclk_peri_pre>, <&dummy>,
1397 <&dummy>, <&pclk_peri_pre>;
1399 clock-output-names =
1400 "g_hclk_emmc", "reserved",
1401 "g_hclk_i2s", "g_hclk_otg1",
1403 "reserved", "reserved",
1404 "reserved", "g_pclk_timer0",
1406 "reserved", "reserved",
1407 "g_pclk_pwm", "reserved",
1409 "g_pclk_spi", "reserved",
1410 "reserved", "g_pclk_wdt";
1412 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1417 clk_gates8: gate-clk@00f0 {
1418 compatible = "rockchip,rk3188-gate-clk";
1421 <&pclk_peri_pre>, <&pclk_peri_pre>,
1422 <&pclk_peri_pre>, <&dummy>,
1424 <&pclk_peri_pre>, <&pclk_peri_pre>,
1425 <&pclk_peri_pre>, <&dummy>,
1427 <&dummy>, <&pclk_peri_pre>,
1428 <&pclk_peri_pre>, <&pclk_peri_pre>,
1433 clock-output-names =
1434 "g_pclk_uart0", "g_pclk_uart1",
1435 "g_pclk_uart2", "reserved",
1437 "g_pclk_i2c0", "g_pclk_i2c1",
1438 "g_pclk_i2c2", "reserved",
1440 "reserved", "g_pclk_gpio0",
1441 "g_pclk_gpio1", "g_pclk_gpio2",
1443 "reserved", "reserved",
1444 "reserved", "reserved";
1446 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1450 clk_gates9: gate-clk@00f4 {
1451 compatible = "rockchip,rk3188-gate-clk";
1457 <&dummy>, <&hclk_vio_pre>,
1458 <&aclk_vio_pre>, <&dummy>,
1463 <&dummy>, <&hclk_peri_pre>,
1464 <&hclk_peri_pre>, <&aclk_peri_pre>;
1466 clock-output-names =
1467 "reserved", "reserved",
1468 "reserved", "reserved",
1470 "reserved", "g_hclk_lcdc",
1471 "g_aclk_lcdc", "reserved",
1473 "reserved", "reserved",
1474 "reserved", "reserved",
1476 "reserved", "g_hclk_usb_peri",
1477 "g_hclk_pe_arbi", "g_aclk_peri_niu";
1479 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1484 clk_gates10: gate-clk@00f8 {
1485 compatible = "rockchip,rk3188-gate-clk";
1488 <&xin24m>, <&xin24m>,
1489 <&xin24m>, <&dummy>,
1491 <&clk_nandc>, <&clk_sfc>,
1492 <&clk_hevc_core>, <&dummy>,
1494 <&clk_dpll>, <&dummy>,
1500 clock-output-names =
1501 "g_clk_pvtm_core", "g_clk_pvtm_gpu",
1502 "g_pvtm_video", "reserved",
1504 "clk_nandc", "clk_sfc",
1505 "clk_hevc_core", "reserved",
1507 "reserved", "reserved",
1508 "reserved", "reserved",
1510 "reserved", "reserved",
1511 "reserved", "reserved";
1513 rockchip,suspend-clkgating-setting = <0x0 0x0>; /* pwm logic vol */