2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3036-cru.h>
46 #include "skeleton.dtsi"
49 compatible = "rockchip,rk3036";
51 interrupt-parent = <&gic>;
64 device_type = "memory";
65 reg = <0x60000000 0x40000000>;
71 enable-method = "rockchip,rk3036-smp";
75 compatible = "arm,cortex-a7";
77 resets = <&cru SRST_CORE0>;
82 clock-latency = <40000>;
83 clocks = <&cru ARMCLK>;
88 compatible = "arm,cortex-a7";
90 resets = <&cru SRST_CORE1>;
95 compatible = "arm,amba-bus";
100 pdma: pdma@20078000 {
101 compatible = "arm,pl330", "arm,primecell";
102 reg = <0x20078000 0x4000>;
103 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&cru ACLK_DMAC2>;
107 clock-names = "apb_pclk";
112 compatible = "arm,cortex-a7-pmu";
113 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
115 interrupt-affinity = <&cpu0>, <&cpu1>;
119 compatible = "arm,armv7-timer";
120 arm,cpu-registers-not-fw-configured;
121 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
122 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
123 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
124 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
125 clock-frequency = <24000000>;
129 compatible = "fixed-clock";
130 clock-frequency = <24000000>;
131 clock-output-names = "xin24m";
135 bus_intmem@10080000 {
136 compatible = "mmio-sram";
137 reg = <0x10080000 0x2000>;
138 #address-cells = <1>;
140 ranges = <0 0x10080000 0x2000>;
143 compatible = "rockchip,rk3066-smp-sram";
148 gic: interrupt-controller@10139000 {
149 compatible = "arm,gic-400";
150 interrupt-controller;
151 #interrupt-cells = <3>;
152 #address-cells = <0>;
154 reg = <0x10139000 0x1000>,
158 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
161 usb_otg: usb@10180000 {
162 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
164 reg = <0x10180000 0x40000>;
165 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&cru HCLK_OTG0>;
169 g-np-tx-fifo-size = <16>;
170 g-rx-fifo-size = <275>;
171 g-tx-fifo-size = <256 128 128 64 64 32>;
176 usb_host: usb@101c0000 {
177 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
179 reg = <0x101c0000 0x40000>;
180 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&cru HCLK_OTG1>;
187 emmc: dwmmc@1021c000 {
188 compatible = "rockchip,rk3288-dw-mshc";
189 reg = <0x1021c000 0x4000>;
190 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
194 clock-frequency = <37500000>;
195 clock-freq-min-max = <400000 37500000>;
196 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
197 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
198 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
199 default-sample-phase = <158>;
203 fifo-depth = <0x100>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
213 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
214 reg = <0x10220000 0x4000>;
215 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
216 #address-cells = <1>;
218 clock-names = "i2s_hclk", "i2s_clk";
219 clocks = <&cru HCLK_I2S>, <&cru SCLK_I2S>;
220 dmas = <&pdma 0>, <&pdma 1>;
221 dma-names = "tx", "rx";
222 pinctrl-names = "default";
223 pinctrl-0 = <&i2s_bus>;
227 cru: clock-controller@20000000 {
228 compatible = "rockchip,rk3036-cru";
229 reg = <0x20000000 0x1000>;
230 rockchip,grf = <&grf>;
233 assigned-clocks = <&cru PLL_GPLL>;
234 assigned-clock-rates = <594000000>;
237 grf: syscon@20008000 {
238 compatible = "rockchip,rk3036-grf", "syscon";
239 reg = <0x20008000 0x1000>;
242 acodec: acodec-ana@20030000 {
243 compatible = "rk3036-codec";
244 reg = <0x20030000 0x4000>;
245 rockchip,grf = <&grf>;
246 clock-names = "acodec_pclk";
247 clocks = <&cru PCLK_ACODEC>;
251 timer: timer@20044000 {
252 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
253 reg = <0x20044000 0x20>;
254 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&xin24m>, <&cru PCLK_TIMER>;
256 clock-names = "timer", "pclk";
260 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
261 reg = <0x20050000 0x10>;
263 clocks = <&cru PCLK_PWM>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pwm0_pin>;
271 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
272 reg = <0x20050010 0x10>;
274 clocks = <&cru PCLK_PWM>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pwm1_pin>;
282 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
283 reg = <0x20050020 0x10>;
285 clocks = <&cru PCLK_PWM>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pwm2_pin>;
293 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
294 reg = <0x20050030 0x10>;
296 clocks = <&cru PCLK_PWM>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pwm3_pin>;
304 compatible = "rockchip,rk3288-i2c";
305 reg = <0x20056000 0x1000>;
306 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
307 #address-cells = <1>;
310 clocks = <&cru PCLK_I2C1>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&i2c1_xfer>;
317 compatible = "rockchip,rk3288-i2c";
318 reg = <0x2005a000 0x1000>;
319 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
323 clocks = <&cru PCLK_I2C2>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&i2c2_xfer>;
329 uart0: serial@20060000 {
330 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
331 reg = <0x20060000 0x100>;
332 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
335 clock-frequency = <24000000>;
336 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
337 clock-names = "baudclk", "apb_pclk";
338 pinctrl-names = "default";
339 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
343 uart1: serial@20064000 {
344 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
345 reg = <0x20064000 0x100>;
346 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
349 clock-frequency = <24000000>;
350 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
351 clock-names = "baudclk", "apb_pclk";
352 pinctrl-names = "default";
353 pinctrl-0 = <&uart1_xfer>;
357 uart2: serial@20068000 {
358 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
359 reg = <0x20068000 0x100>;
360 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
363 clock-frequency = <24000000>;
364 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
365 clock-names = "baudclk", "apb_pclk";
366 pinctrl-names = "default";
367 pinctrl-0 = <&uart2_xfer>;
372 compatible = "rockchip,rk3288-i2c";
373 reg = <0x20072000 0x1000>;
374 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
375 #address-cells = <1>;
378 clocks = <&cru PCLK_I2C0>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&i2c0_xfer>;
385 compatible = "rockchip,rk3036-pinctrl";
386 rockchip,grf = <&grf>;
387 #address-cells = <1>;
391 gpio0: gpio0@2007c000 {
392 compatible = "rockchip,gpio-bank";
393 reg = <0x2007c000 0x100>;
394 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&cru PCLK_GPIO0>;
400 interrupt-controller;
401 #interrupt-cells = <2>;
404 gpio1: gpio1@20080000 {
405 compatible = "rockchip,gpio-bank";
406 reg = <0x20080000 0x100>;
407 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&cru PCLK_GPIO1>;
413 interrupt-controller;
414 #interrupt-cells = <2>;
417 gpio2: gpio2@20084000 {
418 compatible = "rockchip,gpio-bank";
419 reg = <0x20084000 0x100>;
420 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cru PCLK_GPIO2>;
426 interrupt-controller;
427 #interrupt-cells = <2>;
430 pcfg_pull_up: pcfg-pull-up {
434 pcfg_pull_down: pcfg-pull-down {
438 pcfg_pull_none: pcfg-pull-none {
444 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
450 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
456 rockchip,pins = <0 1 2 &pcfg_pull_none>;
462 rockchip,pins = <0 27 1 &pcfg_pull_none>;
468 * We run eMMC at max speed; bump up drive strength.
469 * We also have external pulls, so disable the internal ones.
472 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
476 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
479 emmc_bus8: emmc-bus8 {
480 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
481 <1 25 RK_FUNC_2 &pcfg_pull_none>,
482 <1 26 RK_FUNC_2 &pcfg_pull_none>,
483 <1 27 RK_FUNC_2 &pcfg_pull_none>,
484 <1 28 RK_FUNC_2 &pcfg_pull_none>,
485 <1 29 RK_FUNC_2 &pcfg_pull_none>,
486 <1 30 RK_FUNC_2 &pcfg_pull_none>,
487 <1 31 RK_FUNC_2 &pcfg_pull_none>;
492 i2c0_xfer: i2c0-xfer {
493 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
494 <0 1 RK_FUNC_1 &pcfg_pull_none>;
499 i2c1_xfer: i2c1-xfer {
500 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
501 <0 3 RK_FUNC_1 &pcfg_pull_none>;
506 i2c2_xfer: i2c2-xfer {
507 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
508 <2 21 RK_FUNC_1 &pcfg_pull_none>;
514 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_none>,
515 <1 1 RK_FUNC_1 &pcfg_pull_none>,
516 <1 2 RK_FUNC_1 &pcfg_pull_none>,
517 <1 3 RK_FUNC_1 &pcfg_pull_none>,
518 <1 4 RK_FUNC_1 &pcfg_pull_none>,
519 <1 5 RK_FUNC_1 &pcfg_pull_none>;
524 uart0_xfer: uart0-xfer {
525 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_up>,
526 <0 17 RK_FUNC_1 &pcfg_pull_none>;
529 uart0_cts: uart0-cts {
530 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_up>;
533 uart0_rts: uart0-rts {
534 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
539 uart1_xfer: uart1-xfer {
540 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
541 <2 23 RK_FUNC_1 &pcfg_pull_none>;
543 /* no rts / cts for uart1 */
547 uart2_xfer: uart2-xfer {
548 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
549 <1 19 RK_FUNC_2 &pcfg_pull_none>;
551 /* no rts / cts for uart2 */