2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3036-cru.h>
46 #include "skeleton.dtsi"
49 compatible = "rockchip,rk3036";
51 interrupt-parent = <&gic>;
67 device_type = "memory";
68 reg = <0x60000000 0x40000000>;
74 enable-method = "rockchip,rk3036-smp";
78 compatible = "arm,cortex-a7";
80 resets = <&cru SRST_CORE0>;
85 clock-latency = <40000>;
86 clocks = <&cru ARMCLK>;
91 compatible = "arm,cortex-a7";
93 resets = <&cru SRST_CORE1>;
98 compatible = "arm,amba-bus";
103 pdma: pdma@20078000 {
104 compatible = "arm,pl330", "arm,primecell";
105 reg = <0x20078000 0x4000>;
106 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
109 clocks = <&cru ACLK_DMAC2>;
110 clock-names = "apb_pclk";
115 compatible = "arm,cortex-a7-pmu";
116 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
118 interrupt-affinity = <&cpu0>, <&cpu1>;
122 compatible = "rockchip,display-subsystem";
127 compatible = "arm,armv7-timer";
128 arm,cpu-registers-not-fw-configured;
129 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
130 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
131 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
132 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
133 clock-frequency = <24000000>;
137 compatible = "fixed-clock";
138 clock-frequency = <24000000>;
139 clock-output-names = "xin24m";
143 bus_intmem@10080000 {
144 compatible = "mmio-sram";
145 reg = <0x10080000 0x2000>;
146 #address-cells = <1>;
148 ranges = <0 0x10080000 0x2000>;
151 compatible = "rockchip,rk3066-smp-sram";
157 compatible = "rockchip,rk3036-vop";
158 reg = <0x10118000 0x19c>;
159 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
161 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
162 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
163 reset-names = "axi", "ahb", "dclk";
168 #address-cells = <1>;
173 vop_mmu: iommu@10118300 {
174 compatible = "rockchip,iommu";
175 reg = <0x10118300 0x100>;
176 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
177 interrupt-names = "vop_mmu";
182 gic: interrupt-controller@10139000 {
183 compatible = "arm,gic-400";
184 interrupt-controller;
185 #interrupt-cells = <3>;
186 #address-cells = <0>;
188 reg = <0x10139000 0x1000>,
192 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
195 usb_otg: usb@10180000 {
196 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
198 reg = <0x10180000 0x40000>;
199 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&cru HCLK_OTG0>;
203 g-np-tx-fifo-size = <16>;
204 g-rx-fifo-size = <275>;
205 g-tx-fifo-size = <256 128 128 64 64 32>;
210 usb_host: usb@101c0000 {
211 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
213 reg = <0x101c0000 0x40000>;
214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&cru HCLK_OTG1>;
221 emac: ethernet@10200000 {
222 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
223 reg = <0x10200000 0x4000>;
224 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
225 #address-cells = <1>;
227 rockchip,grf = <&grf>;
228 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
229 clock-names = "hclk", "macref", "macclk";
231 * Fix the emac parent clock is DPLL instead of APLL.
232 * since that will cause some unstable things if the cpufreq
233 * is working. (e.g: the accurate 50MHz what mac_ref need)
235 assigned-clocks = <&cru SCLK_MACPLL>;
236 assigned-clock-parents = <&cru PLL_DPLL>;
242 sdmmc: dwmmc@10214000 {
243 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
244 reg = <0x10214000 0x4000>;
245 clock-frequency = <37500000>;
246 clock-freq-min-max = <400000 37500000>;
247 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
248 clock-names = "biu", "ciu";
249 fifo-depth = <0x100>;
250 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
254 sdio: dwmmc@10218000 {
255 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
256 reg = <0x10218000 0x4000>;
257 clock-freq-min-max = <400000 37500000>;
258 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
259 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
260 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
261 fifo-depth = <0x100>;
262 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
266 emmc: dwmmc@1021c000 {
267 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
268 reg = <0x1021c000 0x4000>;
269 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
273 clock-frequency = <37500000>;
274 clock-freq-min-max = <400000 37500000>;
275 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
276 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
277 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
278 default-sample-phase = <158>;
282 fifo-depth = <0x100>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
292 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
293 reg = <0x10220000 0x4000>;
294 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
295 #address-cells = <1>;
297 clock-names = "i2s_clk", "i2s_hclk";
298 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
299 dmas = <&pdma 0>, <&pdma 1>;
300 dma-names = "tx", "rx";
301 pinctrl-names = "default";
302 pinctrl-0 = <&i2s_bus>;
306 cru: clock-controller@20000000 {
307 compatible = "rockchip,rk3036-cru";
308 reg = <0x20000000 0x1000>;
309 rockchip,grf = <&grf>;
312 assigned-clocks = <&cru PLL_GPLL>;
313 assigned-clock-rates = <594000000>;
316 grf: syscon@20008000 {
317 compatible = "rockchip,rk3036-grf", "syscon";
318 reg = <0x20008000 0x1000>;
321 acodec: acodec-ana@20030000 {
322 compatible = "rk3036-codec";
323 reg = <0x20030000 0x4000>;
324 rockchip,grf = <&grf>;
325 clock-names = "acodec_pclk";
326 clocks = <&cru PCLK_ACODEC>;
330 timer: timer@20044000 {
331 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
332 reg = <0x20044000 0x20>;
333 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&xin24m>, <&cru PCLK_TIMER>;
335 clock-names = "timer", "pclk";
339 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
340 reg = <0x20050000 0x10>;
342 clocks = <&cru PCLK_PWM>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&pwm0_pin>;
350 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
351 reg = <0x20050010 0x10>;
353 clocks = <&cru PCLK_PWM>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pwm1_pin>;
361 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
362 reg = <0x20050020 0x10>;
364 clocks = <&cru PCLK_PWM>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pwm2_pin>;
372 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
373 reg = <0x20050030 0x10>;
375 clocks = <&cru PCLK_PWM>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&pwm3_pin>;
383 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
384 reg = <0x20056000 0x1000>;
385 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
386 #address-cells = <1>;
389 clocks = <&cru PCLK_I2C1>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&i2c1_xfer>;
396 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
397 reg = <0x2005a000 0x1000>;
398 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
399 #address-cells = <1>;
402 clocks = <&cru PCLK_I2C2>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&i2c2_xfer>;
408 uart0: serial@20060000 {
409 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
410 reg = <0x20060000 0x100>;
411 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
414 clock-frequency = <24000000>;
415 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
416 clock-names = "baudclk", "apb_pclk";
417 pinctrl-names = "default";
418 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
422 uart1: serial@20064000 {
423 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
424 reg = <0x20064000 0x100>;
425 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
428 clock-frequency = <24000000>;
429 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
430 clock-names = "baudclk", "apb_pclk";
431 pinctrl-names = "default";
432 pinctrl-0 = <&uart1_xfer>;
436 uart2: serial@20068000 {
437 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
438 reg = <0x20068000 0x100>;
439 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
442 clock-frequency = <24000000>;
443 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
444 clock-names = "baudclk", "apb_pclk";
445 pinctrl-names = "default";
446 pinctrl-0 = <&uart2_xfer>;
451 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
452 reg = <0x20072000 0x1000>;
453 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
457 clocks = <&cru PCLK_I2C0>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&i2c0_xfer>;
464 compatible = "rockchip,rockchip-spi";
465 reg = <0x20074000 0x1000>;
466 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
467 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
468 clock-names = "apb-pclk","spi_pclk";
469 dmas = <&pdma 8>, <&pdma 9>;
470 dma-names = "tx", "rx";
471 pinctrl-names = "default";
472 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
473 #address-cells = <1>;
479 compatible = "rockchip,rk3036-pinctrl";
480 rockchip,grf = <&grf>;
481 #address-cells = <1>;
485 gpio0: gpio0@2007c000 {
486 compatible = "rockchip,gpio-bank";
487 reg = <0x2007c000 0x100>;
488 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&cru PCLK_GPIO0>;
494 interrupt-controller;
495 #interrupt-cells = <2>;
498 gpio1: gpio1@20080000 {
499 compatible = "rockchip,gpio-bank";
500 reg = <0x20080000 0x100>;
501 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&cru PCLK_GPIO1>;
507 interrupt-controller;
508 #interrupt-cells = <2>;
511 gpio2: gpio2@20084000 {
512 compatible = "rockchip,gpio-bank";
513 reg = <0x20084000 0x100>;
514 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&cru PCLK_GPIO2>;
520 interrupt-controller;
521 #interrupt-cells = <2>;
524 pcfg_pull_default: pcfg_pull_default {
525 bias-pull-pin-default;
528 pcfg_pull_none: pcfg-pull-none {
534 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
540 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
546 rockchip,pins = <0 1 2 &pcfg_pull_none>;
552 rockchip,pins = <0 27 1 &pcfg_pull_none>;
557 sdmmc_clk: sdmmc-clk {
558 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
561 sdmmc_cmd: sdmmc-cmd {
562 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
566 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
569 sdmmc_bus1: sdmmc-bus1 {
570 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
573 sdmmc_bus4: sdmmc-bus4 {
574 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
575 <1 19 RK_FUNC_1 &pcfg_pull_default>,
576 <1 20 RK_FUNC_1 &pcfg_pull_default>,
577 <1 21 RK_FUNC_1 &pcfg_pull_default>;
582 sdio_bus1: sdio-bus1 {
583 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
586 sdio_bus4: sdio-bus4 {
587 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
588 <0 12 RK_FUNC_1 &pcfg_pull_default>,
589 <0 13 RK_FUNC_1 &pcfg_pull_default>,
590 <0 14 RK_FUNC_1 &pcfg_pull_default>;
594 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
598 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
604 * We run eMMC at max speed; bump up drive strength.
605 * We also have external pulls, so disable the internal ones.
608 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
612 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
615 emmc_bus8: emmc-bus8 {
616 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
617 <1 25 RK_FUNC_2 &pcfg_pull_default>,
618 <1 26 RK_FUNC_2 &pcfg_pull_default>,
619 <1 27 RK_FUNC_2 &pcfg_pull_default>,
620 <1 28 RK_FUNC_2 &pcfg_pull_default>,
621 <1 29 RK_FUNC_2 &pcfg_pull_default>,
622 <1 30 RK_FUNC_2 &pcfg_pull_default>,
623 <1 31 RK_FUNC_2 &pcfg_pull_default>;
628 emac_xfer: emac-xfer {
629 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
630 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
631 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
632 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
633 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
634 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
635 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
636 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
639 emac_mdio: emac-mdio {
640 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
641 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
646 i2c0_xfer: i2c0-xfer {
647 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
648 <0 1 RK_FUNC_1 &pcfg_pull_none>;
653 i2c1_xfer: i2c1-xfer {
654 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
655 <0 3 RK_FUNC_1 &pcfg_pull_none>;
660 i2c2_xfer: i2c2-xfer {
661 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
662 <2 21 RK_FUNC_1 &pcfg_pull_none>;
668 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
669 <1 1 RK_FUNC_1 &pcfg_pull_default>,
670 <1 2 RK_FUNC_1 &pcfg_pull_default>,
671 <1 3 RK_FUNC_1 &pcfg_pull_default>,
672 <1 4 RK_FUNC_1 &pcfg_pull_default>,
673 <1 5 RK_FUNC_1 &pcfg_pull_default>;
678 uart0_xfer: uart0-xfer {
679 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
680 <0 17 RK_FUNC_1 &pcfg_pull_none>;
683 uart0_cts: uart0-cts {
684 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
687 uart0_rts: uart0-rts {
688 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
693 uart1_xfer: uart1-xfer {
694 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
695 <2 23 RK_FUNC_1 &pcfg_pull_none>;
697 /* no rts / cts for uart1 */
701 uart2_xfer: uart2-xfer {
702 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
703 <1 19 RK_FUNC_2 &pcfg_pull_none>;
705 /* no rts / cts for uart2 */
710 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
714 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
718 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
722 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
727 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;