2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3036-cru.h>
46 #include "skeleton.dtsi"
49 compatible = "rockchip,rk3036";
51 interrupt-parent = <&gic>;
69 enable-method = "rockchip,rk3036-smp";
73 compatible = "arm,cortex-a7";
75 resets = <&cru SRST_CORE0>;
80 clock-latency = <40000>;
81 clocks = <&cru ARMCLK>;
86 compatible = "arm,cortex-a7";
88 resets = <&cru SRST_CORE1>;
93 compatible = "arm,amba-bus";
99 compatible = "arm,pl330", "arm,primecell";
100 reg = <0x20078000 0x4000>;
101 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
104 arm,pl330-broken-no-flushp;
105 peripherals-req-type-burst;
106 clocks = <&cru ACLK_DMAC2>;
107 clock-names = "apb_pclk";
112 compatible = "arm,cortex-a7-pmu";
113 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
115 interrupt-affinity = <&cpu0>, <&cpu1>;
119 compatible = "rockchip,display-subsystem";
124 compatible = "arm,armv7-timer";
125 arm,cpu-registers-not-fw-configured;
126 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
130 clock-frequency = <24000000>;
134 compatible = "fixed-clock";
135 clock-frequency = <24000000>;
136 clock-output-names = "xin24m";
140 bus_intmem@10080000 {
141 compatible = "mmio-sram";
142 reg = <0x10080000 0x2000>;
143 #address-cells = <1>;
145 ranges = <0 0x10080000 0x2000>;
148 compatible = "rockchip,rk3066-smp-sram";
153 vpu: video-codec@10108000 {
154 compatible = "rockchip,rk3036-vpu", "rockchip,rk3288-vpu";
155 reg = <0x10108000 0x800>;
156 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
158 interrupt-names = "vepu", "vdpu";
159 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
160 clock-names = "aclk", "hclk";
163 * 3036's vpu could not run higher than 300M
165 assigned-clocks = <&cru ACLK_VCODEC>;
166 assigned-clock-rates = <297000000>;
167 assigned-clock-parents = <&cru PLL_GPLL>;
171 vpu_mmu: iommu@10108800 {
172 compatible = "rockchip,iommu";
173 reg = <0x10108800 0x100>;
174 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
175 interrupt-names = "vpu_mmu";
180 compatible = "rockchip,rk3036-vop";
181 reg = <0x10118000 0x19c>;
182 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
184 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
185 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
186 reset-names = "axi", "ahb", "dclk";
191 #address-cells = <1>;
193 vop_out_hdmi: endpoint@0 {
195 remote-endpoint = <&hdmi_in_vop>;
200 vop_mmu: iommu@10118300 {
201 compatible = "rockchip,iommu";
202 reg = <0x10118300 0x100>;
203 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
204 interrupt-names = "vop_mmu";
209 gic: interrupt-controller@10139000 {
210 compatible = "arm,gic-400";
211 interrupt-controller;
212 #interrupt-cells = <3>;
213 #address-cells = <0>;
215 reg = <0x10139000 0x1000>,
219 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
222 usb_otg: usb@10180000 {
223 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
225 reg = <0x10180000 0x40000>;
226 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&cru HCLK_OTG0>;
230 g-np-tx-fifo-size = <16>;
231 g-rx-fifo-size = <275>;
232 g-tx-fifo-size = <256 128 128 64 64 32>;
237 usb_host: usb@101c0000 {
238 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
240 reg = <0x101c0000 0x40000>;
241 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&cru HCLK_OTG1>;
248 emac: ethernet@10200000 {
249 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
250 reg = <0x10200000 0x4000>;
251 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
252 #address-cells = <1>;
254 rockchip,grf = <&grf>;
255 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
256 clock-names = "hclk", "macref", "macclk";
258 * Fix the emac parent clock is DPLL instead of APLL.
259 * since that will cause some unstable things if the cpufreq
260 * is working. (e.g: the accurate 50MHz what mac_ref need)
262 assigned-clocks = <&cru SCLK_MACPLL>;
263 assigned-clock-parents = <&cru PLL_DPLL>;
269 sdmmc: dwmmc@10214000 {
270 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
271 reg = <0x10214000 0x4000>;
272 clock-frequency = <37500000>;
273 clock-freq-min-max = <400000 37500000>;
274 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
275 clock-names = "biu", "ciu";
276 fifo-depth = <0x100>;
277 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
281 sdio: dwmmc@10218000 {
282 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
283 reg = <0x10218000 0x4000>;
284 clock-freq-min-max = <400000 37500000>;
285 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
286 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
287 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
288 fifo-depth = <0x100>;
289 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
293 emmc: dwmmc@1021c000 {
294 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
295 reg = <0x1021c000 0x4000>;
296 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
299 clock-frequency = <37500000>;
300 clock-freq-min-max = <400000 37500000>;
301 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
302 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
303 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
304 default-sample-phase = <158>;
308 fifo-depth = <0x100>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
319 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
320 reg = <0x10220000 0x4000>;
321 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
322 #address-cells = <1>;
324 clock-names = "i2s_clk", "i2s_hclk";
325 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
326 dmas = <&pdma 0>, <&pdma 1>;
327 dma-names = "tx", "rx";
328 pinctrl-names = "default";
329 pinctrl-0 = <&i2s_bus>;
333 cru: clock-controller@20000000 {
334 compatible = "rockchip,rk3036-cru";
335 reg = <0x20000000 0x1000>;
336 rockchip,grf = <&grf>;
339 assigned-clocks = <&cru PLL_GPLL>;
340 assigned-clock-rates = <594000000>;
343 grf: syscon@20008000 {
344 compatible = "rockchip,rk3036-grf", "syscon";
345 reg = <0x20008000 0x1000>;
348 acodec: acodec-ana@20030000 {
349 compatible = "rk3036-codec";
350 reg = <0x20030000 0x4000>;
351 rockchip,grf = <&grf>;
352 clock-names = "acodec_pclk";
353 clocks = <&cru PCLK_ACODEC>;
357 hdmi: hdmi@20034000 {
358 compatible = "rockchip,rk3036-inno-hdmi";
359 reg = <0x20034000 0x4000>;
360 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&cru PCLK_HDMI>;
362 clock-names = "pclk";
363 rockchip,grf = <&grf>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&hdmi_ctl>;
366 #address-cells = <1>;
368 #sound-dai-cells = <0>;
372 #address-cells = <1>;
374 hdmi_in_vop: endpoint@0 {
376 remote-endpoint = <&vop_out_hdmi>;
381 hdmi_sound: hdmi-sound {
382 compatible = "simple-audio-card";
383 simple-audio-card,name = "rockchip,hdmi";
384 simple-audio-card,widgets = "Headphone", "Out Jack",
388 simple-audio-card,dai-link {
400 timer: timer@20044000 {
401 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
402 reg = <0x20044000 0x20>;
403 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&xin24m>, <&cru PCLK_TIMER>;
405 clock-names = "timer", "pclk";
409 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
410 reg = <0x20050000 0x10>;
412 clocks = <&cru PCLK_PWM>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&pwm0_pin>;
420 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
421 reg = <0x20050010 0x10>;
423 clocks = <&cru PCLK_PWM>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&pwm1_pin>;
431 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
432 reg = <0x20050020 0x10>;
434 clocks = <&cru PCLK_PWM>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&pwm2_pin>;
442 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
443 reg = <0x20050030 0x10>;
445 clocks = <&cru PCLK_PWM>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&pwm3_pin>;
453 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
454 reg = <0x20056000 0x1000>;
455 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
459 clocks = <&cru PCLK_I2C1>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&i2c1_xfer>;
466 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
467 reg = <0x2005a000 0x1000>;
468 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
469 #address-cells = <1>;
472 clocks = <&cru PCLK_I2C2>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&i2c2_xfer>;
478 uart0: serial@20060000 {
479 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
480 reg = <0x20060000 0x100>;
481 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
484 clock-frequency = <24000000>;
485 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
486 clock-names = "baudclk", "apb_pclk";
487 pinctrl-names = "default";
488 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
492 uart1: serial@20064000 {
493 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
494 reg = <0x20064000 0x100>;
495 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
498 clock-frequency = <24000000>;
499 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
500 clock-names = "baudclk", "apb_pclk";
501 pinctrl-names = "default";
502 pinctrl-0 = <&uart1_xfer>;
506 uart2: serial@20068000 {
507 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
508 reg = <0x20068000 0x100>;
509 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
512 clock-frequency = <24000000>;
513 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
514 clock-names = "baudclk", "apb_pclk";
515 pinctrl-names = "default";
516 pinctrl-0 = <&uart2_xfer>;
521 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
522 reg = <0x20072000 0x1000>;
523 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
524 #address-cells = <1>;
527 clocks = <&cru PCLK_I2C0>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&i2c0_xfer>;
534 compatible = "rockchip,rockchip-spi";
535 reg = <0x20074000 0x1000>;
536 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
537 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
538 clock-names = "apb-pclk","spi_pclk";
539 dmas = <&pdma 8>, <&pdma 9>;
540 dma-names = "tx", "rx";
541 pinctrl-names = "default";
542 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
543 #address-cells = <1>;
549 compatible = "rockchip,rk3036-pinctrl";
550 rockchip,grf = <&grf>;
551 #address-cells = <1>;
555 gpio0: gpio0@2007c000 {
556 compatible = "rockchip,gpio-bank";
557 reg = <0x2007c000 0x100>;
558 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&cru PCLK_GPIO0>;
564 interrupt-controller;
565 #interrupt-cells = <2>;
568 gpio1: gpio1@20080000 {
569 compatible = "rockchip,gpio-bank";
570 reg = <0x20080000 0x100>;
571 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&cru PCLK_GPIO1>;
577 interrupt-controller;
578 #interrupt-cells = <2>;
581 gpio2: gpio2@20084000 {
582 compatible = "rockchip,gpio-bank";
583 reg = <0x20084000 0x100>;
584 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&cru PCLK_GPIO2>;
590 interrupt-controller;
591 #interrupt-cells = <2>;
594 pcfg_pull_default: pcfg_pull_default {
595 bias-pull-pin-default;
598 pcfg_pull_none: pcfg-pull-none {
604 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
610 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
616 rockchip,pins = <0 1 2 &pcfg_pull_none>;
622 rockchip,pins = <0 27 1 &pcfg_pull_none>;
627 sdmmc_clk: sdmmc-clk {
628 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
631 sdmmc_cmd: sdmmc-cmd {
632 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
636 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
639 sdmmc_bus1: sdmmc-bus1 {
640 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
643 sdmmc_bus4: sdmmc-bus4 {
644 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
645 <1 19 RK_FUNC_1 &pcfg_pull_default>,
646 <1 20 RK_FUNC_1 &pcfg_pull_default>,
647 <1 21 RK_FUNC_1 &pcfg_pull_default>;
652 sdio_bus1: sdio-bus1 {
653 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
656 sdio_bus4: sdio-bus4 {
657 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
658 <0 12 RK_FUNC_1 &pcfg_pull_default>,
659 <0 13 RK_FUNC_1 &pcfg_pull_default>,
660 <0 14 RK_FUNC_1 &pcfg_pull_default>;
664 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
668 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
674 * We run eMMC at max speed; bump up drive strength.
675 * We also have external pulls, so disable the internal ones.
678 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
682 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
685 emmc_bus8: emmc-bus8 {
686 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
687 <1 25 RK_FUNC_2 &pcfg_pull_default>,
688 <1 26 RK_FUNC_2 &pcfg_pull_default>,
689 <1 27 RK_FUNC_2 &pcfg_pull_default>,
690 <1 28 RK_FUNC_2 &pcfg_pull_default>,
691 <1 29 RK_FUNC_2 &pcfg_pull_default>,
692 <1 30 RK_FUNC_2 &pcfg_pull_default>,
693 <1 31 RK_FUNC_2 &pcfg_pull_default>;
698 emac_xfer: emac-xfer {
699 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
700 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
701 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
702 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
703 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
704 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
705 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
706 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
709 emac_mdio: emac-mdio {
710 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
711 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
716 i2c0_xfer: i2c0-xfer {
717 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
718 <0 1 RK_FUNC_1 &pcfg_pull_none>;
723 i2c1_xfer: i2c1-xfer {
724 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
725 <0 3 RK_FUNC_1 &pcfg_pull_none>;
730 i2c2_xfer: i2c2-xfer {
731 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
732 <2 21 RK_FUNC_1 &pcfg_pull_none>;
738 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
739 <1 1 RK_FUNC_1 &pcfg_pull_default>,
740 <1 2 RK_FUNC_1 &pcfg_pull_default>,
741 <1 3 RK_FUNC_1 &pcfg_pull_default>,
742 <1 4 RK_FUNC_1 &pcfg_pull_default>,
743 <1 5 RK_FUNC_1 &pcfg_pull_default>;
749 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
750 <1 9 RK_FUNC_1 &pcfg_pull_none>,
751 <1 10 RK_FUNC_1 &pcfg_pull_none>,
752 <1 11 RK_FUNC_1 &pcfg_pull_none>;
757 uart0_xfer: uart0-xfer {
758 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
759 <0 17 RK_FUNC_1 &pcfg_pull_none>;
762 uart0_cts: uart0-cts {
763 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
766 uart0_rts: uart0-rts {
767 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
772 uart1_xfer: uart1-xfer {
773 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
774 <2 23 RK_FUNC_1 &pcfg_pull_none>;
776 /* no rts / cts for uart1 */
780 uart2_xfer: uart2-xfer {
781 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
782 <1 19 RK_FUNC_2 &pcfg_pull_none>;
784 /* no rts / cts for uart2 */
789 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
793 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
797 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
801 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
806 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;