arch/arm/boot/dts/rk3036.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3036-cru.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         compatible = "rockchip,rk3036";
  50
  51         interrupt-parent = <&gic>;
  52
  53         aliases {
  54                 i2c0 = &i2c0;
  55                 i2c1 = &i2c1;
  56                 i2c2 = &i2c2;
  57                 mshc0 = &emmc;
  58                 mshc1 = &sdmmc;
  59                 mshc2 = &sdio;
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 spi = &spi;
  64         };
  65
  66         cpus {
  67                 #address-cells = <1>;
  68                 #size-cells = <0>;
  69                 enable-method = "rockchip,rk3036-smp";
  70
  71                 cpu0: cpu@f00 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a7";
  74                         reg = <0xf00>;
  75                         resets = <&cru SRST_CORE0>;
  76                         operating-points = <
  77                                 /* KHz    uV */
  78                                  816000 1000000
  79                         >;
  80                         clock-latency = <40000>;
  81                         clocks = <&cru ARMCLK>;
  82                 };
  83
  84                 cpu1: cpu@f01 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a7";
  87                         reg = <0xf01>;
  88                         resets = <&cru SRST_CORE1>;
  89                 };
  90         };
  91
  92         amba {
  93                 compatible = "arm,amba-bus";
  94                 #address-cells = <1>;
  95                 #size-cells = <1>;
  96                 ranges;
  97
  98                 pdma: pdma@20078000 {
  99                         compatible = "arm,pl330", "arm,primecell";
 100                         reg = <0x20078000 0x4000>;
 101                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 102                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 103                         #dma-cells = <1>;
 104                         arm,pl330-broken-no-flushp;
 105                         peripherals-req-type-burst;
 106                         clocks = <&cru ACLK_DMAC2>;
 107                         clock-names = "apb_pclk";
 108                 };
 109         };
 110
 111         arm-pmu {
 112                 compatible = "arm,cortex-a7-pmu";
 113                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 114                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 115                 interrupt-affinity = <&cpu0>, <&cpu1>;
 116         };
 117
 118         display-subsystem {
 119                 compatible = "rockchip,display-subsystem";
 120                 ports = <&vop_out>;
 121         };
 122
 123         timer {
 124                 compatible = "arm,armv7-timer";
 125                 arm,cpu-registers-not-fw-configured;
 126                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 127                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 128                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 129                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 130                 clock-frequency = <24000000>;
 131         };
 132
 133         xin24m: oscillator {
 134                 compatible = "fixed-clock";
 135                 clock-frequency = <24000000>;
 136                 clock-output-names = "xin24m";
 137                 #clock-cells = <0>;
 138         };
 139
 140         bus_intmem@10080000 {
 141                 compatible = "mmio-sram";
 142                 reg = <0x10080000 0x2000>;
 143                 #address-cells = <1>;
 144                 #size-cells = <1>;
 145                 ranges = <0 0x10080000 0x2000>;
 146
 147                 smp-sram@0 {
 148                         compatible = "rockchip,rk3066-smp-sram";
 149                         reg = <0x00 0x10>;
 150                 };
 151         };
 152
 153         gpu: gpu@10090000 {
 154                 compatible = "arm,mali400";
 155
 156                 reg = <0x10091000 0x200>,
 157                       <0x10090000 0x100>,
 158                       <0x10093000 0x100>,
 159                       <0x10098000 0x1100>,
 160                       <0x10094000 0x100>;
 161
 162                 reg-names = "Mali_L2",
 163                             "Mali_GP",
 164                             "Mali_GP_MMU",
 165                             "Mali_PP0",
 166                             "Mali_PP0_MMU";
 167
 168                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 172                 interrupt-names = "Mali_GP_IRQ",
 173                                   "Mali_GP_MMU_IRQ",
 174                                   "Mali_PP0_IRQ",
 175                                   "Mali_PP0_MMU_IRQ";
 176
 177                 clocks = <&cru  SCLK_GPU>;
 178                 clock-names = "clk_mali";
 179
 180                 status = "disabled";
 181         };
 182
 183         vpu: video-codec@10108000 {
 184                 compatible = "rockchip,rk3036-vpu", "rockchip,rk3288-vpu";
 185                 reg = <0x10108000 0x800>;
 186                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 188                 interrupt-names = "vepu", "vdpu";
 189                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 190                 clock-names = "aclk", "hclk";
 191                 iommus = <&vpu_mmu>;
 192                 /*
 193                  * 3036's vpu could not run higher than 300M
 194                  */
 195                 assigned-clocks = <&cru ACLK_VCODEC>;
 196                 assigned-clock-rates = <297000000>;
 197                 assigned-clock-parents = <&cru PLL_GPLL>;
 198                 status = "disabled";
 199         };
 200
 201         vpu_mmu: iommu@10108800 {
 202                 compatible = "rockchip,iommu";
 203                 reg = <0x10108800 0x100>;
 204                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 205                 interrupt-names = "vpu_mmu";
 206                 #iommu-cells = <0>;
 207         };
 208
 209         vop: vop@10118000 {
 210                 compatible = "rockchip,rk3036-vop";
 211                 reg = <0x10118000 0x19c>;
 212                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
 214                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 215                 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
 216                 reset-names = "axi", "ahb", "dclk";
 217                 iommus = <&vop_mmu>;
 218                 status = "disabled";
 219
 220                 vop_out: port {
 221                         #address-cells = <1>;
 222                         #size-cells = <0>;
 223                         vop_out_hdmi: endpoint@0 {
 224                                 reg = <0>;
 225                                 remote-endpoint = <&hdmi_in_vop>;
 226                         };
 227                 };
 228         };
 229
 230         vop_mmu: iommu@10118300 {
 231                 compatible = "rockchip,iommu";
 232                 reg = <0x10118300 0x100>;
 233                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 234                 interrupt-names = "vop_mmu";
 235                 #iommu-cells = <0>;
 236                 status = "disabled";
 237         };
 238
 239         gic: interrupt-controller@10139000 {
 240                 compatible = "arm,gic-400";
 241                 interrupt-controller;
 242                 #interrupt-cells = <3>;
 243                 #address-cells = <0>;
 244
 245                 reg = <0x10139000 0x1000>,
 246                       <0x1013a000 0x1000>,
 247                       <0x1013c000 0x2000>,
 248                       <0x1013e000 0x2000>;
 249                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 250         };
 251
 252         usb_otg: usb@10180000 {
 253                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 254                                 "snps,dwc2";
 255                 reg = <0x10180000 0x40000>;
 256                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 257                 clocks = <&cru HCLK_OTG0>;
 258                 clock-names = "otg";
 259                 dr_mode = "otg";
 260                 g-np-tx-fifo-size = <16>;
 261                 g-rx-fifo-size = <275>;
 262                 g-tx-fifo-size = <256 128 128 64 64 32>;
 263                 g-use-dma;
 264                 status = "disabled";
 265         };
 266
 267         usb_host: usb@101c0000 {
 268                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 269                                 "snps,dwc2";
 270                 reg = <0x101c0000 0x40000>;
 271                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 272                 clocks = <&cru HCLK_OTG1>;
 273                 clock-names = "otg";
 274                 dr_mode = "host";
 275                 status = "disabled";
 276         };
 277
 278         emac: ethernet@10200000 {
 279                 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
 280                 reg = <0x10200000 0x4000>;
 281                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 282                 #address-cells = <1>;
 283                 #size-cells = <0>;
 284                 rockchip,grf = <&grf>;
 285                 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
 286                 clock-names = "hclk", "macref", "macclk";
 287                 /*
 288                  * Fix the emac parent clock is DPLL instead of APLL.
 289                  * since that will cause some unstable things if the cpufreq
 290                  * is working. (e.g: the accurate 50MHz what mac_ref need)
 291                  */
 292                 assigned-clocks = <&cru SCLK_MACPLL>;
 293                 assigned-clock-parents = <&cru PLL_DPLL>;
 294                 max-speed = <100>;
 295                 phy-mode = "rmii";
 296                 status = "disabled";
 297         };
 298
 299         sdmmc: dwmmc@10214000 {
 300                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 301                 reg = <0x10214000 0x4000>;
 302                 clock-frequency = <37500000>;
 303                 clock-freq-min-max = <400000 37500000>;
 304                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 305                 clock-names = "biu", "ciu";
 306                 fifo-depth = <0x100>;
 307                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 308                 status = "disabled";
 309         };
 310
 311         sdio: dwmmc@10218000 {
 312                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 313                 reg = <0x10218000 0x4000>;
 314                 clock-freq-min-max = <400000 37500000>;
 315                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 316                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 317                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 318                 fifo-depth = <0x100>;
 319                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 320                 status = "disabled";
 321         };
 322
 323         emmc: dwmmc@1021c000 {
 324                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 325                 reg = <0x1021c000 0x4000>;
 326                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 327                 bus-width = <8>;
 328                 cap-mmc-highspeed;
 329                 clock-frequency = <37500000>;
 330                 clock-freq-min-max = <400000 37500000>;
 331                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 332                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 333                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 334                 default-sample-phase = <158>;
 335                 disable-wp;
 336                 dmas = <&pdma 12>;
 337                 dma-names = "rx-tx";
 338                 fifo-depth = <0x100>;
 339                 mmc-ddr-1_8v;
 340                 non-removable;
 341                 num-slots = <1>;
 342                 supports-emmc;
 343                 pinctrl-names = "default";
 344                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 345                 status = "disabled";
 346         };
 347
 348         i2s: i2s@10220000 {
 349                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 350                 reg = <0x10220000 0x4000>;
 351                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 clock-names = "i2s_clk", "i2s_hclk";
 355                 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 356                 dmas = <&pdma 0>, <&pdma 1>;
 357                 dma-names = "tx", "rx";
 358                 pinctrl-names = "default";
 359                 pinctrl-0 = <&i2s_bus>;
 360                 status = "disabled";
 361         };
 362
 363         cru: clock-controller@20000000 {
 364                 compatible = "rockchip,rk3036-cru";
 365                 reg = <0x20000000 0x1000>;
 366                 rockchip,grf = <&grf>;
 367                 #clock-cells = <1>;
 368                 #reset-cells = <1>;
 369                 assigned-clocks = <&cru PLL_GPLL>;
 370                 assigned-clock-rates = <594000000>;
 371         };
 372
 373         grf: syscon@20008000 {
 374                 compatible = "rockchip,rk3036-grf", "syscon";
 375                 reg = <0x20008000 0x1000>;
 376         };
 377
 378         acodec: acodec-ana@20030000 {
 379                 compatible = "rk3036-codec";
 380                 reg = <0x20030000 0x4000>;
 381                 rockchip,grf = <&grf>;
 382                 clock-names = "acodec_pclk";
 383                 clocks = <&cru PCLK_ACODEC>;
 384                 status = "disabled";
 385         };
 386
 387         hdmi: hdmi@20034000 {
 388                 compatible = "rockchip,rk3036-inno-hdmi";
 389                 reg = <0x20034000 0x4000>;
 390                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 391                 clocks = <&cru  PCLK_HDMI>;
 392                 clock-names = "pclk";
 393                 rockchip,grf = <&grf>;
 394                 pinctrl-names = "default";
 395                 pinctrl-0 = <&hdmi_ctl>;
 396                 #address-cells = <1>;
 397                 #size-cells = <0>;
 398                 #sound-dai-cells = <0>;
 399                 status = "disabled";
 400
 401                 hdmi_in: port {
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                         hdmi_in_vop: endpoint@0 {
 405                                 reg = <0>;
 406                                 remote-endpoint = <&vop_out_hdmi>;
 407                         };
 408                 };
 409         };
 410
 411         hdmi_sound: hdmi-sound {
 412                 compatible = "simple-audio-card";
 413                 simple-audio-card,name = "rockchip,hdmi";
 414                 simple-audio-card,widgets = "Headphone", "Out Jack",
 415                                             "Line", "In Jack";
 416                 status = "disabled";
 417
 418                 simple-audio-card,dai-link {
 419                         format = "i2s";
 420                         mclk-fs = <256>;
 421                         cpu {
 422                                 sound-dai = <&i2s>;
 423                         };
 424                         codec {
 425                                 sound-dai = <&hdmi>;
 426                         };
 427                 };
 428         };
 429
 430         timer: timer@20044000 {
 431                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 432                 reg = <0x20044000 0x20>;
 433                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 434                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 435                 clock-names = "timer", "pclk";
 436         };
 437
 438         pwm0: pwm@20050000 {
 439                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 440                 reg = <0x20050000 0x10>;
 441                 #pwm-cells = <3>;
 442                 clocks = <&cru PCLK_PWM>;
 443                 clock-names = "pwm";
 444                 pinctrl-names = "default";
 445                 pinctrl-0 = <&pwm0_pin>;
 446                 status = "disabled";
 447         };
 448
 449         pwm1: pwm@20050010 {
 450                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 451                 reg = <0x20050010 0x10>;
 452                 #pwm-cells = <3>;
 453                 clocks = <&cru PCLK_PWM>;
 454                 clock-names = "pwm";
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&pwm1_pin>;
 457                 status = "disabled";
 458         };
 459
 460         pwm2: pwm@20050020 {
 461                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 462                 reg = <0x20050020 0x10>;
 463                 #pwm-cells = <3>;
 464                 clocks = <&cru PCLK_PWM>;
 465                 clock-names = "pwm";
 466                 pinctrl-names = "default";
 467                 pinctrl-0 = <&pwm2_pin>;
 468                 status = "disabled";
 469         };
 470
 471         pwm3: pwm@20050030 {
 472                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 473                 reg = <0x20050030 0x10>;
 474                 #pwm-cells = <2>;
 475                 clocks = <&cru PCLK_PWM>;
 476                 clock-names = "pwm";
 477                 pinctrl-names = "default";
 478                 pinctrl-0 = <&pwm3_pin>;
 479                 status = "disabled";
 480         };
 481
 482         i2c1: i2c@20056000 {
 483                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 484                 reg = <0x20056000 0x1000>;
 485                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 clock-names = "i2c";
 489                 clocks = <&cru PCLK_I2C1>;
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&i2c1_xfer>;
 492                 status = "disabled";
 493         };
 494
 495         i2c2: i2c@2005a000 {
 496                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 497                 reg = <0x2005a000 0x1000>;
 498                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 clock-names = "i2c";
 502                 clocks = <&cru PCLK_I2C2>;
 503                 pinctrl-names = "default";
 504                 pinctrl-0 = <&i2c2_xfer>;
 505                 status = "disabled";
 506         };
 507
 508         uart0: serial@20060000 {
 509                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 510                 reg = <0x20060000 0x100>;
 511                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 512                 reg-shift = <2>;
 513                 reg-io-width = <4>;
 514                 clock-frequency = <24000000>;
 515                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 516                 clock-names = "baudclk", "apb_pclk";
 517                 pinctrl-names = "default";
 518                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 519                 status = "disabled";
 520         };
 521
 522         uart1: serial@20064000 {
 523                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 524                 reg = <0x20064000 0x100>;
 525                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 526                 reg-shift = <2>;
 527                 reg-io-width = <4>;
 528                 clock-frequency = <24000000>;
 529                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 530                 clock-names = "baudclk", "apb_pclk";
 531                 pinctrl-names = "default";
 532                 pinctrl-0 = <&uart1_xfer>;
 533                 status = "disabled";
 534         };
 535
 536         uart2: serial@20068000 {
 537                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 538                 reg = <0x20068000 0x100>;
 539                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 540                 reg-shift = <2>;
 541                 reg-io-width = <4>;
 542                 clock-frequency = <24000000>;
 543                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 544                 clock-names = "baudclk", "apb_pclk";
 545                 pinctrl-names = "default";
 546                 pinctrl-0 = <&uart2_xfer>;
 547                 status = "disabled";
 548         };
 549
 550         i2c0: i2c@20072000 {
 551                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 552                 reg = <0x20072000 0x1000>;
 553                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 554                 #address-cells = <1>;
 555                 #size-cells = <0>;
 556                 clock-names = "i2c";
 557                 clocks = <&cru PCLK_I2C0>;
 558                 pinctrl-names = "default";
 559                 pinctrl-0 = <&i2c0_xfer>;
 560                 status = "disabled";
 561         };
 562
 563         spi: spi@20074000 {
 564                 compatible = "rockchip,rockchip-spi";
 565                 reg = <0x20074000 0x1000>;
 566                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 567                 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
 568                 clock-names = "apb-pclk","spi_pclk";
 569                 dmas = <&pdma 8>, <&pdma 9>;
 570                 dma-names = "tx", "rx";
 571                 pinctrl-names = "default";
 572                 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
 573                 #address-cells = <1>;
 574                 #size-cells = <0>;
 575                 status = "disabled";
 576         };
 577
 578         pinctrl: pinctrl {
 579                 compatible = "rockchip,rk3036-pinctrl";
 580                 rockchip,grf = <&grf>;
 581                 #address-cells = <1>;
 582                 #size-cells = <1>;
 583                 ranges;
 584
 585                 gpio0: gpio0@2007c000 {
 586                         compatible = "rockchip,gpio-bank";
 587                         reg = <0x2007c000 0x100>;
 588                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 589                         clocks = <&cru PCLK_GPIO0>;
 590
 591                         gpio-controller;
 592                         #gpio-cells = <2>;
 593
 594                         interrupt-controller;
 595                         #interrupt-cells = <2>;
 596                 };
 597
 598                 gpio1: gpio1@20080000 {
 599                         compatible = "rockchip,gpio-bank";
 600                         reg = <0x20080000 0x100>;
 601                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 602                         clocks = <&cru PCLK_GPIO1>;
 603
 604                         gpio-controller;
 605                         #gpio-cells = <2>;
 606
 607                         interrupt-controller;
 608                         #interrupt-cells = <2>;
 609                 };
 610
 611                 gpio2: gpio2@20084000 {
 612                         compatible = "rockchip,gpio-bank";
 613                         reg = <0x20084000 0x100>;
 614                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 615                         clocks = <&cru PCLK_GPIO2>;
 616
 617                         gpio-controller;
 618                         #gpio-cells = <2>;
 619
 620                         interrupt-controller;
 621                         #interrupt-cells = <2>;
 622                 };
 623
 624                 pcfg_pull_default: pcfg_pull_default {
 625                         bias-pull-pin-default;
 626                 };
 627
 628                 pcfg_pull_none: pcfg-pull-none {
 629                         bias-disable;
 630                 };
 631
 632                 pwm0 {
 633                         pwm0_pin: pwm0-pin {
 634                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
 635                         };
 636                 };
 637
 638                 pwm1 {
 639                         pwm1_pin: pwm1-pin {
 640                                 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
 641                         };
 642                 };
 643
 644                 pwm2 {
 645                         pwm2_pin: pwm2-pin {
 646                                 rockchip,pins = <0 1 2 &pcfg_pull_none>;
 647                         };
 648                 };
 649
 650                 pwm3 {
 651                         pwm3_pin: pwm3-pin {
 652                                 rockchip,pins = <0 27 1 &pcfg_pull_none>;
 653                         };
 654                 };
 655
 656                 sdmmc {
 657                         sdmmc_clk: sdmmc-clk {
 658                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
 659                         };
 660
 661                         sdmmc_cmd: sdmmc-cmd {
 662                                 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
 663                         };
 664
 665                         sdmmc_cd: sdmcc-cd {
 666                                 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
 667                         };
 668
 669                         sdmmc_bus1: sdmmc-bus1 {
 670                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
 671                         };
 672
 673                         sdmmc_bus4: sdmmc-bus4 {
 674                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
 675                                                 <1 19 RK_FUNC_1 &pcfg_pull_default>,
 676                                                 <1 20 RK_FUNC_1 &pcfg_pull_default>,
 677                                                 <1 21 RK_FUNC_1 &pcfg_pull_default>;
 678                         };
 679                 };
 680
 681                 sdio {
 682                         sdio_bus1: sdio-bus1 {
 683                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
 684                         };
 685
 686                         sdio_bus4: sdio-bus4 {
 687                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
 688                                                 <0 12 RK_FUNC_1 &pcfg_pull_default>,
 689                                                 <0 13 RK_FUNC_1 &pcfg_pull_default>,
 690                                                 <0 14 RK_FUNC_1 &pcfg_pull_default>;
 691                         };
 692
 693                         sdio_cmd: sdio-cmd {
 694                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
 695                         };
 696
 697                         sdio_clk: sdio-clk {
 698                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
 699                         };
 700                 };
 701
 702                 emmc {
 703                         /*
 704                          * We run eMMC at max speed; bump up drive strength.
 705                          * We also have external pulls, so disable the internal ones.
 706                          */
 707                         emmc_clk: emmc-clk {
 708                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 709                         };
 710
 711                         emmc_cmd: emmc-cmd {
 712                                 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
 713                         };
 714
 715                         emmc_bus8: emmc-bus8 {
 716                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
 717                                                 <1 25 RK_FUNC_2 &pcfg_pull_default>,
 718                                                 <1 26 RK_FUNC_2 &pcfg_pull_default>,
 719                                                 <1 27 RK_FUNC_2 &pcfg_pull_default>,
 720                                                 <1 28 RK_FUNC_2 &pcfg_pull_default>,
 721                                                 <1 29 RK_FUNC_2 &pcfg_pull_default>,
 722                                                 <1 30 RK_FUNC_2 &pcfg_pull_default>,
 723                                                 <1 31 RK_FUNC_2 &pcfg_pull_default>;
 724                         };
 725                 };
 726
 727                 emac {
 728                         emac_xfer: emac-xfer {
 729                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
 730                                                 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
 731                                                 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
 732                                                 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
 733                                                 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
 734                                                 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
 735                                                 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
 736                                                 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
 737                         };
 738
 739                         emac_mdio: emac-mdio {
 740                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
 741                                                 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
 742                         };
 743                 };
 744
 745                 i2c0 {
 746                         i2c0_xfer: i2c0-xfer {
 747                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 748                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 749                         };
 750                 };
 751
 752                 i2c1 {
 753                         i2c1_xfer: i2c1-xfer {
 754                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 755                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 756                         };
 757                 };
 758
 759                 i2c2 {
 760                         i2c2_xfer: i2c2-xfer {
 761                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 762                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 763                         };
 764                 };
 765
 766                 i2s {
 767                         i2s_bus: i2s-bus {
 768                                 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
 769                                                 <1 1 RK_FUNC_1 &pcfg_pull_default>,
 770                                                 <1 2 RK_FUNC_1 &pcfg_pull_default>,
 771                                                 <1 3 RK_FUNC_1 &pcfg_pull_default>,
 772                                                 <1 4 RK_FUNC_1 &pcfg_pull_default>,
 773                                                 <1 5 RK_FUNC_1 &pcfg_pull_default>;
 774                         };
 775                 };
 776
 777                 hdmi {
 778                         hdmi_ctl: hdmi-ctl {
 779                                 rockchip,pins = <1 8  RK_FUNC_1 &pcfg_pull_none>,
 780                                                 <1 9  RK_FUNC_1 &pcfg_pull_none>,
 781                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,
 782                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;
 783                         };
 784                 };
 785
 786                 uart0 {
 787                         uart0_xfer: uart0-xfer {
 788                                 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
 789                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>;
 790                         };
 791
 792                         uart0_cts: uart0-cts {
 793                                 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
 794                         };
 795
 796                         uart0_rts: uart0-rts {
 797                                 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
 798                         };
 799                 };
 800
 801                 uart1 {
 802                         uart1_xfer: uart1-xfer {
 803                                 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
 804                                                 <2 23 RK_FUNC_1 &pcfg_pull_none>;
 805                         };
 806                         /* no rts / cts for uart1 */
 807                 };
 808
 809                 uart2 {
 810                         uart2_xfer: uart2-xfer {
 811                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
 812                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 813                         };
 814                         /* no rts / cts for uart2 */
 815                 };
 816
 817                 spi {
 818                         spi_txd:spi-txd {
 819                                 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
 820                         };
 821
 822                         spi_rxd:spi-rxd {
 823                                 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
 824                         };
 825
 826                         spi_clk:spi-clk {
 827                                 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
 828                         };
 829
 830                         spi_cs0:spi-cs0 {
 831                                 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
 832
 833                         };
 834
 835                         spi_cs1:spi-cs1 {
 836                                 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
 837
 838                         };
 839                 };
 840         };
 841 };