arch/arm/boot/dts/rk3036.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3036-cru.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         compatible = "rockchip,rk3036";
  50
  51         interrupt-parent = <&gic>;
  52
  53         aliases {
  54                 i2c0 = &i2c0;
  55                 i2c1 = &i2c1;
  56                 i2c2 = &i2c2;
  57                 mshc0 = &emmc;
  58                 mshc1 = &sdmmc;
  59                 mshc2 = &sdio;
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 spi = &spi;
  64         };
  65
  66         cpus {
  67                 #address-cells = <1>;
  68                 #size-cells = <0>;
  69                 enable-method = "rockchip,rk3036-smp";
  70
  71                 cpu0: cpu@f00 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a7";
  74                         reg = <0xf00>;
  75                         resets = <&cru SRST_CORE0>;
  76                         operating-points = <
  77                                 /* KHz    uV */
  78                                  816000 1000000
  79                         >;
  80                         clock-latency = <40000>;
  81                         clocks = <&cru ARMCLK>;
  82                 };
  83
  84                 cpu1: cpu@f01 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a7";
  87                         reg = <0xf01>;
  88                         resets = <&cru SRST_CORE1>;
  89                 };
  90         };
  91
  92         amba {
  93                 compatible = "arm,amba-bus";
  94                 #address-cells = <1>;
  95                 #size-cells = <1>;
  96                 ranges;
  97
  98                 pdma: pdma@20078000 {
  99                         compatible = "arm,pl330", "arm,primecell";
 100                         reg = <0x20078000 0x4000>;
 101                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 102                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 103                         #dma-cells = <1>;
 104                         arm,pl330-broken-no-flushp;
 105                         peripherals-req-type-burst;
 106                         clocks = <&cru ACLK_DMAC2>;
 107                         clock-names = "apb_pclk";
 108                 };
 109         };
 110
 111         arm-pmu {
 112                 compatible = "arm,cortex-a7-pmu";
 113                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 114                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 115                 interrupt-affinity = <&cpu0>, <&cpu1>;
 116         };
 117
 118         display-subsystem {
 119                 compatible = "rockchip,display-subsystem";
 120                 ports = <&vop_out>;
 121         };
 122
 123         timer {
 124                 compatible = "arm,armv7-timer";
 125                 arm,cpu-registers-not-fw-configured;
 126                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 127                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 128                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 129                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 130                 clock-frequency = <24000000>;
 131         };
 132
 133         xin24m: oscillator {
 134                 compatible = "fixed-clock";
 135                 clock-frequency = <24000000>;
 136                 clock-output-names = "xin24m";
 137                 #clock-cells = <0>;
 138         };
 139
 140         bus_intmem@10080000 {
 141                 compatible = "mmio-sram";
 142                 reg = <0x10080000 0x2000>;
 143                 #address-cells = <1>;
 144                 #size-cells = <1>;
 145                 ranges = <0 0x10080000 0x2000>;
 146
 147                 smp-sram@0 {
 148                         compatible = "rockchip,rk3066-smp-sram";
 149                         reg = <0x00 0x10>;
 150                 };
 151         };
 152
 153         vop: vop@10118000 {
 154                 compatible = "rockchip,rk3036-vop";
 155                 reg = <0x10118000 0x19c>;
 156                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 157                 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
 158                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 159                 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
 160                 reset-names = "axi", "ahb", "dclk";
 161                 iommus = <&vop_mmu>;
 162                 status = "disabled";
 163
 164                 vop_out: port {
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         vop_out_hdmi: endpoint@0 {
 168                                 reg = <0>;
 169                                 remote-endpoint = <&hdmi_in_vop>;
 170                         };
 171                 };
 172         };
 173
 174         vop_mmu: iommu@10118300 {
 175                 compatible = "rockchip,iommu";
 176                 reg = <0x10118300 0x100>;
 177                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 178                 interrupt-names = "vop_mmu";
 179                 #iommu-cells = <0>;
 180                 status = "disabled";
 181         };
 182
 183         gic: interrupt-controller@10139000 {
 184                 compatible = "arm,gic-400";
 185                 interrupt-controller;
 186                 #interrupt-cells = <3>;
 187                 #address-cells = <0>;
 188
 189                 reg = <0x10139000 0x1000>,
 190                       <0x1013a000 0x1000>,
 191                       <0x1013c000 0x2000>,
 192                       <0x1013e000 0x2000>;
 193                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 194         };
 195
 196         usb_otg: usb@10180000 {
 197                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 198                                 "snps,dwc2";
 199                 reg = <0x10180000 0x40000>;
 200                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 201                 clocks = <&cru HCLK_OTG0>;
 202                 clock-names = "otg";
 203                 dr_mode = "otg";
 204                 g-np-tx-fifo-size = <16>;
 205                 g-rx-fifo-size = <275>;
 206                 g-tx-fifo-size = <256 128 128 64 64 32>;
 207                 g-use-dma;
 208                 status = "disabled";
 209         };
 210
 211         usb_host: usb@101c0000 {
 212                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 213                                 "snps,dwc2";
 214                 reg = <0x101c0000 0x40000>;
 215                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 216                 clocks = <&cru HCLK_OTG1>;
 217                 clock-names = "otg";
 218                 dr_mode = "host";
 219                 status = "disabled";
 220         };
 221
 222         emac: ethernet@10200000 {
 223                 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
 224                 reg = <0x10200000 0x4000>;
 225                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 226                 #address-cells = <1>;
 227                 #size-cells = <0>;
 228                 rockchip,grf = <&grf>;
 229                 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
 230                 clock-names = "hclk", "macref", "macclk";
 231                 /*
 232                  * Fix the emac parent clock is DPLL instead of APLL.
 233                  * since that will cause some unstable things if the cpufreq
 234                  * is working. (e.g: the accurate 50MHz what mac_ref need)
 235                  */
 236                 assigned-clocks = <&cru SCLK_MACPLL>;
 237                 assigned-clock-parents = <&cru PLL_DPLL>;
 238                 max-speed = <100>;
 239                 phy-mode = "rmii";
 240                 status = "disabled";
 241         };
 242
 243         sdmmc: dwmmc@10214000 {
 244                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 245                 reg = <0x10214000 0x4000>;
 246                 clock-frequency = <37500000>;
 247                 clock-freq-min-max = <400000 37500000>;
 248                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 249                 clock-names = "biu", "ciu";
 250                 fifo-depth = <0x100>;
 251                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 252                 status = "disabled";
 253         };
 254
 255         sdio: dwmmc@10218000 {
 256                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 257                 reg = <0x10218000 0x4000>;
 258                 clock-freq-min-max = <400000 37500000>;
 259                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 260                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 261                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 262                 fifo-depth = <0x100>;
 263                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 264                 status = "disabled";
 265         };
 266
 267         emmc: dwmmc@1021c000 {
 268                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 269                 reg = <0x1021c000 0x4000>;
 270                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 271                 bus-width = <8>;
 272                 cap-mmc-highspeed;
 273                 clock-frequency = <37500000>;
 274                 clock-freq-min-max = <400000 37500000>;
 275                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 276                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 277                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 278                 default-sample-phase = <158>;
 279                 disable-wp;
 280                 dmas = <&pdma 12>;
 281                 dma-names = "rx-tx";
 282                 fifo-depth = <0x100>;
 283                 mmc-ddr-1_8v;
 284                 non-removable;
 285                 num-slots = <1>;
 286                 supports-emmc;
 287                 pinctrl-names = "default";
 288                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 289                 status = "disabled";
 290         };
 291
 292         i2s: i2s@10220000 {
 293                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 294                 reg = <0x10220000 0x4000>;
 295                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 296                 #address-cells = <1>;
 297                 #size-cells = <0>;
 298                 clock-names = "i2s_clk", "i2s_hclk";
 299                 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 300                 dmas = <&pdma 0>, <&pdma 1>;
 301                 dma-names = "tx", "rx";
 302                 pinctrl-names = "default";
 303                 pinctrl-0 = <&i2s_bus>;
 304                 status = "disabled";
 305         };
 306
 307         cru: clock-controller@20000000 {
 308                 compatible = "rockchip,rk3036-cru";
 309                 reg = <0x20000000 0x1000>;
 310                 rockchip,grf = <&grf>;
 311                 #clock-cells = <1>;
 312                 #reset-cells = <1>;
 313                 assigned-clocks = <&cru PLL_GPLL>;
 314                 assigned-clock-rates = <594000000>;
 315         };
 316
 317         grf: syscon@20008000 {
 318                 compatible = "rockchip,rk3036-grf", "syscon";
 319                 reg = <0x20008000 0x1000>;
 320         };
 321
 322         acodec: acodec-ana@20030000 {
 323                 compatible = "rk3036-codec";
 324                 reg = <0x20030000 0x4000>;
 325                 rockchip,grf = <&grf>;
 326                 clock-names = "acodec_pclk";
 327                 clocks = <&cru PCLK_ACODEC>;
 328                 status = "disabled";
 329         };
 330
 331         hdmi: hdmi@20034000 {
 332                 compatible = "rockchip,rk3036-inno-hdmi";
 333                 reg = <0x20034000 0x4000>;
 334                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 335                 clocks = <&cru  PCLK_HDMI>;
 336                 clock-names = "pclk";
 337                 rockchip,grf = <&grf>;
 338                 pinctrl-names = "default";
 339                 pinctrl-0 = <&hdmi_ctl>;
 340                 status = "disabled";
 341
 342                 hdmi_in: port {
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                         hdmi_in_vop: endpoint@0 {
 346                                 reg = <0>;
 347                                 remote-endpoint = <&vop_out_hdmi>;
 348                         };
 349                 };
 350         };
 351
 352         timer: timer@20044000 {
 353                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 354                 reg = <0x20044000 0x20>;
 355                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 356                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 357                 clock-names = "timer", "pclk";
 358         };
 359
 360         pwm0: pwm@20050000 {
 361                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 362                 reg = <0x20050000 0x10>;
 363                 #pwm-cells = <3>;
 364                 clocks = <&cru PCLK_PWM>;
 365                 clock-names = "pwm";
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&pwm0_pin>;
 368                 status = "disabled";
 369         };
 370
 371         pwm1: pwm@20050010 {
 372                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 373                 reg = <0x20050010 0x10>;
 374                 #pwm-cells = <3>;
 375                 clocks = <&cru PCLK_PWM>;
 376                 clock-names = "pwm";
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&pwm1_pin>;
 379                 status = "disabled";
 380         };
 381
 382         pwm2: pwm@20050020 {
 383                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 384                 reg = <0x20050020 0x10>;
 385                 #pwm-cells = <3>;
 386                 clocks = <&cru PCLK_PWM>;
 387                 clock-names = "pwm";
 388                 pinctrl-names = "default";
 389                 pinctrl-0 = <&pwm2_pin>;
 390                 status = "disabled";
 391         };
 392
 393         pwm3: pwm@20050030 {
 394                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 395                 reg = <0x20050030 0x10>;
 396                 #pwm-cells = <2>;
 397                 clocks = <&cru PCLK_PWM>;
 398                 clock-names = "pwm";
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&pwm3_pin>;
 401                 status = "disabled";
 402         };
 403
 404         i2c1: i2c@20056000 {
 405                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 406                 reg = <0x20056000 0x1000>;
 407                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 clock-names = "i2c";
 411                 clocks = <&cru PCLK_I2C1>;
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&i2c1_xfer>;
 414                 status = "disabled";
 415         };
 416
 417         i2c2: i2c@2005a000 {
 418                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 419                 reg = <0x2005a000 0x1000>;
 420                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 421                 #address-cells = <1>;
 422                 #size-cells = <0>;
 423                 clock-names = "i2c";
 424                 clocks = <&cru PCLK_I2C2>;
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&i2c2_xfer>;
 427                 status = "disabled";
 428         };
 429
 430         uart0: serial@20060000 {
 431                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 432                 reg = <0x20060000 0x100>;
 433                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 434                 reg-shift = <2>;
 435                 reg-io-width = <4>;
 436                 clock-frequency = <24000000>;
 437                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 438                 clock-names = "baudclk", "apb_pclk";
 439                 pinctrl-names = "default";
 440                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 441                 status = "disabled";
 442         };
 443
 444         uart1: serial@20064000 {
 445                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 446                 reg = <0x20064000 0x100>;
 447                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 448                 reg-shift = <2>;
 449                 reg-io-width = <4>;
 450                 clock-frequency = <24000000>;
 451                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 452                 clock-names = "baudclk", "apb_pclk";
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&uart1_xfer>;
 455                 status = "disabled";
 456         };
 457
 458         uart2: serial@20068000 {
 459                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 460                 reg = <0x20068000 0x100>;
 461                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 462                 reg-shift = <2>;
 463                 reg-io-width = <4>;
 464                 clock-frequency = <24000000>;
 465                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 466                 clock-names = "baudclk", "apb_pclk";
 467                 pinctrl-names = "default";
 468                 pinctrl-0 = <&uart2_xfer>;
 469                 status = "disabled";
 470         };
 471
 472         i2c0: i2c@20072000 {
 473                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 474                 reg = <0x20072000 0x1000>;
 475                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 476                 #address-cells = <1>;
 477                 #size-cells = <0>;
 478                 clock-names = "i2c";
 479                 clocks = <&cru PCLK_I2C0>;
 480                 pinctrl-names = "default";
 481                 pinctrl-0 = <&i2c0_xfer>;
 482                 status = "disabled";
 483         };
 484
 485         spi: spi@20074000 {
 486                 compatible = "rockchip,rockchip-spi";
 487                 reg = <0x20074000 0x1000>;
 488                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 489                 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
 490                 clock-names = "apb-pclk","spi_pclk";
 491                 dmas = <&pdma 8>, <&pdma 9>;
 492                 dma-names = "tx", "rx";
 493                 pinctrl-names = "default";
 494                 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 status = "disabled";
 498         };
 499
 500         pinctrl: pinctrl {
 501                 compatible = "rockchip,rk3036-pinctrl";
 502                 rockchip,grf = <&grf>;
 503                 #address-cells = <1>;
 504                 #size-cells = <1>;
 505                 ranges;
 506
 507                 gpio0: gpio0@2007c000 {
 508                         compatible = "rockchip,gpio-bank";
 509                         reg = <0x2007c000 0x100>;
 510                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 511                         clocks = <&cru PCLK_GPIO0>;
 512
 513                         gpio-controller;
 514                         #gpio-cells = <2>;
 515
 516                         interrupt-controller;
 517                         #interrupt-cells = <2>;
 518                 };
 519
 520                 gpio1: gpio1@20080000 {
 521                         compatible = "rockchip,gpio-bank";
 522                         reg = <0x20080000 0x100>;
 523                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 524                         clocks = <&cru PCLK_GPIO1>;
 525
 526                         gpio-controller;
 527                         #gpio-cells = <2>;
 528
 529                         interrupt-controller;
 530                         #interrupt-cells = <2>;
 531                 };
 532
 533                 gpio2: gpio2@20084000 {
 534                         compatible = "rockchip,gpio-bank";
 535                         reg = <0x20084000 0x100>;
 536                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 537                         clocks = <&cru PCLK_GPIO2>;
 538
 539                         gpio-controller;
 540                         #gpio-cells = <2>;
 541
 542                         interrupt-controller;
 543                         #interrupt-cells = <2>;
 544                 };
 545
 546                 pcfg_pull_default: pcfg_pull_default {
 547                         bias-pull-pin-default;
 548                 };
 549
 550                 pcfg_pull_none: pcfg-pull-none {
 551                         bias-disable;
 552                 };
 553
 554                 pwm0 {
 555                         pwm0_pin: pwm0-pin {
 556                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
 557                         };
 558                 };
 559
 560                 pwm1 {
 561                         pwm1_pin: pwm1-pin {
 562                                 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
 563                         };
 564                 };
 565
 566                 pwm2 {
 567                         pwm2_pin: pwm2-pin {
 568                                 rockchip,pins = <0 1 2 &pcfg_pull_none>;
 569                         };
 570                 };
 571
 572                 pwm3 {
 573                         pwm3_pin: pwm3-pin {
 574                                 rockchip,pins = <0 27 1 &pcfg_pull_none>;
 575                         };
 576                 };
 577
 578                 sdmmc {
 579                         sdmmc_clk: sdmmc-clk {
 580                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
 581                         };
 582
 583                         sdmmc_cmd: sdmmc-cmd {
 584                                 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
 585                         };
 586
 587                         sdmmc_cd: sdmcc-cd {
 588                                 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
 589                         };
 590
 591                         sdmmc_bus1: sdmmc-bus1 {
 592                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
 593                         };
 594
 595                         sdmmc_bus4: sdmmc-bus4 {
 596                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
 597                                                 <1 19 RK_FUNC_1 &pcfg_pull_default>,
 598                                                 <1 20 RK_FUNC_1 &pcfg_pull_default>,
 599                                                 <1 21 RK_FUNC_1 &pcfg_pull_default>;
 600                         };
 601                 };
 602
 603                 sdio {
 604                         sdio_bus1: sdio-bus1 {
 605                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
 606                         };
 607
 608                         sdio_bus4: sdio-bus4 {
 609                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
 610                                                 <0 12 RK_FUNC_1 &pcfg_pull_default>,
 611                                                 <0 13 RK_FUNC_1 &pcfg_pull_default>,
 612                                                 <0 14 RK_FUNC_1 &pcfg_pull_default>;
 613                         };
 614
 615                         sdio_cmd: sdio-cmd {
 616                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
 617                         };
 618
 619                         sdio_clk: sdio-clk {
 620                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
 621                         };
 622                 };
 623
 624                 emmc {
 625                         /*
 626                          * We run eMMC at max speed; bump up drive strength.
 627                          * We also have external pulls, so disable the internal ones.
 628                          */
 629                         emmc_clk: emmc-clk {
 630                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 631                         };
 632
 633                         emmc_cmd: emmc-cmd {
 634                                 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
 635                         };
 636
 637                         emmc_bus8: emmc-bus8 {
 638                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
 639                                                 <1 25 RK_FUNC_2 &pcfg_pull_default>,
 640                                                 <1 26 RK_FUNC_2 &pcfg_pull_default>,
 641                                                 <1 27 RK_FUNC_2 &pcfg_pull_default>,
 642                                                 <1 28 RK_FUNC_2 &pcfg_pull_default>,
 643                                                 <1 29 RK_FUNC_2 &pcfg_pull_default>,
 644                                                 <1 30 RK_FUNC_2 &pcfg_pull_default>,
 645                                                 <1 31 RK_FUNC_2 &pcfg_pull_default>;
 646                         };
 647                 };
 648
 649                 emac {
 650                         emac_xfer: emac-xfer {
 651                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
 652                                                 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
 653                                                 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
 654                                                 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
 655                                                 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
 656                                                 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
 657                                                 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
 658                                                 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
 659                         };
 660
 661                         emac_mdio: emac-mdio {
 662                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
 663                                                 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
 664                         };
 665                 };
 666
 667                 i2c0 {
 668                         i2c0_xfer: i2c0-xfer {
 669                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 670                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 671                         };
 672                 };
 673
 674                 i2c1 {
 675                         i2c1_xfer: i2c1-xfer {
 676                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 677                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 678                         };
 679                 };
 680
 681                 i2c2 {
 682                         i2c2_xfer: i2c2-xfer {
 683                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 684                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 685                         };
 686                 };
 687
 688                 i2s {
 689                         i2s_bus: i2s-bus {
 690                                 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
 691                                                 <1 1 RK_FUNC_1 &pcfg_pull_default>,
 692                                                 <1 2 RK_FUNC_1 &pcfg_pull_default>,
 693                                                 <1 3 RK_FUNC_1 &pcfg_pull_default>,
 694                                                 <1 4 RK_FUNC_1 &pcfg_pull_default>,
 695                                                 <1 5 RK_FUNC_1 &pcfg_pull_default>;
 696                         };
 697                 };
 698
 699                 hdmi {
 700                         hdmi_ctl: hdmi-ctl {
 701                                 rockchip,pins = <1 8  RK_FUNC_1 &pcfg_pull_none>,
 702                                                 <1 9  RK_FUNC_1 &pcfg_pull_none>,
 703                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,
 704                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;
 705                         };
 706                 };
 707
 708                 uart0 {
 709                         uart0_xfer: uart0-xfer {
 710                                 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
 711                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>;
 712                         };
 713
 714                         uart0_cts: uart0-cts {
 715                                 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
 716                         };
 717
 718                         uart0_rts: uart0-rts {
 719                                 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
 720                         };
 721                 };
 722
 723                 uart1 {
 724                         uart1_xfer: uart1-xfer {
 725                                 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
 726                                                 <2 23 RK_FUNC_1 &pcfg_pull_none>;
 727                         };
 728                         /* no rts / cts for uart1 */
 729                 };
 730
 731                 uart2 {
 732                         uart2_xfer: uart2-xfer {
 733                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
 734                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 735                         };
 736                         /* no rts / cts for uart2 */
 737                 };
 738
 739                 spi {
 740                         spi_txd:spi-txd {
 741                                 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
 742                         };
 743
 744                         spi_rxd:spi-rxd {
 745                                 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
 746                         };
 747
 748                         spi_clk:spi-clk {
 749                                 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
 750                         };
 751
 752                         spi_cs0:spi-cs0 {
 753                                 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
 754
 755                         };
 756
 757                         spi_cs1:spi-cs1 {
 758                                 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
 759
 760                         };
 761                 };
 762         };
 763 };