1 #include <dt-bindings/interrupt-controller/arm-gic.h>
3 #include "skeleton.dtsi"
4 #include "rk3036-clocks.dtsi"
5 #include "rk3036-pinctrl.dtsi"
6 #include <dt-bindings/suspend/rockchip-pm.h>
9 compatible = "rockchip,rk3036";
10 rockchip,sram = <&sram>;
11 interrupt-parent = <&gic>;
29 compatible = "arm,cortex-a7";
34 compatible = "arm,cortex-a7";
39 gic: interrupt-controller@10139000 {
40 compatible = "arm,cortex-a15-gic";
42 #interrupt-cells = <3>;
44 reg = <0x10139000 0x1000>,
49 compatible = "arm,cortex-a7-pmu";
50 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
54 cpu_axi_bus: cpu_axi_bus {
55 compatible = "rockchip,cpu_axi_bus";
66 reg = <0x1012a000 0x20>;
67 rockchip,priority = <3 2>;
70 reg = <0x1012c000 0x20>;
73 reg = <0x1012d000 0x20>;
76 reg = <0x1012e000 0x20>;
79 reg = <0x1012e080 0x20>;
82 reg = <0x1012f000 0x20>;
83 rockchip,priority = <3 3>;
93 reg = <0x10128000 0x40>;
94 rockchip,read-latency = <0x80>;
100 compatible = "mmio-sram";
101 reg = <0x10080000 0x2000>;
106 compatible = "arm,armv7-timer";
107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
108 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
109 clock-frequency = <24000000>;
113 compatible = "rockchip,timer";
114 reg = <0x20044000 0x20>;
115 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
116 rockchip,broadcast = <1>;
119 watchdog: wdt@2004c000 {
120 compatible = "rockchip,watch dog";
121 reg = <0x2004c000 0x100>;
122 clocks = <&clk_gates7 15>;
123 clock-names = "pclk_wdt";
124 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
126 rockchip,timeout = <60>;
127 rockchip,atboot = <1>;
128 rockchip,debug = <0>;
133 #address-cells = <1>;
135 compatible = "arm,amba-bus";
136 interrupt-parent = <&gic>;
139 pdma: pdma@20078000 {
140 compatible = "arm,pl330", "arm,primecell";
141 reg = <0x20078000 0x4000>;
142 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
148 reset: reset@20000110{
149 compatible = "rockchip,reset";
150 reg = <0x20000110 0x24>;
151 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
155 nandc: nandc@10500000 {
156 compatible = "rockchip,rk-nandc";
157 reg = <0x10500000 0x4000>;
158 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
159 //pinctrl-names = "default";
160 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
162 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 4>;
163 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
166 nandc0reg: nandc0@10500000 {
167 compatible = "rockchip,rk-nandc";
168 reg = <0x10500000 0x4000>;
172 compatible = "rockchip,rockchip-spi";
173 reg = <0x20074000 0x1000>;
174 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
175 #address-cells = <1>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
179 rockchip,spi-src-clk = <0>;
181 clocks =<&clk_spi0>, <&clk_gates2 9>;
182 clock-names = "spi","pclk_spi0";
183 dmas = <&pdma 8>, <&pdma 9>;
185 dma-names = "tx", "rx";
189 uart0: serial@20060000 {
190 compatible = "rockchip,serial";
191 reg = <0x20060000 0x100>;
192 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
193 clock-frequency = <24000000>;
194 clocks = <&clk_uart0>, <&clk_gates8 0>;
195 clock-names = "sclk_uart", "pclk_uart";
198 dmas = <&pdma 2>, <&pdma 3>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
205 uart1: serial@20064000 {
206 compatible = "rockchip,serial";
207 reg = <0x20064000 0x100>;
208 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
209 clock-frequency = <24000000>;
210 clocks = <&clk_uart1>, <&clk_gates8 1>;
211 clock-names = "sclk_uart", "pclk_uart";
214 dmas = <&pdma 4>, <&pdma 5>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&uart1_xfer>;
221 uart2: serial@20068000 {
222 compatible = "rockchip,serial";
223 reg = <0x20068000 0x100>;
224 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
225 clock-frequency = <24000000>;
226 clocks = <&clk_uart2>, <&clk_gates8 2>;
227 clock-names = "sclk_uart", "pclk_uart";
230 dmas = <&pdma 6>, <&pdma 7>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&uart2_xfer>;
238 compatible = "rockchip,fiq-debugger";
239 rockchip,serial-id = <2>;
240 rockchip,signal-irq = <106>;
241 rockchip,wake-irq = <0>;
246 compatible = "rockchip,clocks-init";
247 rockchip,clocks-init-parent =
248 <&clk_core &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
249 <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
250 <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
251 <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
252 <&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>;
253 rockchip,clocks-init-rate =
254 <&clk_core 1000000000>, <&clk_gpll 594000000>,
255 <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
256 <&pclk_cpu_pre 75000000>, <&aclk_peri_pre 150000000>,
257 <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
258 <&clk_gpu 300000000>, <&aclk_vio_pre 300000000>,
259 <&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
260 <&clk_hevc_core 200000000>, <&clk_mac_pll_div 50000000>,
261 <&clk_mac_ref_div 25000000>;
262 /* rockchip,clocks-uboot-has-init =
267 compatible = "rockchip,clocks-enable";
270 <&clk_gates0 0>, <&clk_gates0 7>,
273 <&clk_gates0 3>, <&clk_gates0 4>,
277 <&clk_gates1 0>, <&clk_gates1 1>,
278 <&clk_gates2 4>, <&clk_gates2 5>,
281 <&clk_gates2 0>, <&hclk_peri_pre>,
282 <&pclk_peri_pre>, <&clk_gates2 1>,
285 <&clk_gates4 12>,/*aclk_intmem*/
286 <&clk_gates4 10>,/*aclk_strc_sys*/
289 <&clk_gates5 6>,/*hclk_rom*/
292 <&clk_gates5 4>,/*pclk_grf*/
293 <&clk_gates5 7>,/*pclk_ddrupctl*/
294 <&clk_gates5 14>,/*pclk_acodec*/
295 <&clk_gates3 8>,/*pclk_hdmi*/
298 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
299 <&clk_gates5 1>,/*aclk_dmac2*/
300 <&clk_gates9 15>,/*aclk_peri_niu*/
301 <&clk_gates4 2>,/*aclk_cpu_peri*/
304 <&clk_gates4 0>,/*hclk_peri_matrix*/
305 <&clk_gates9 13>,/*hclk_usb_peri*/
306 <&clk_gates9 14>,/*hclk_peri_arbi*/
309 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
312 <&clk_gates6 12>,/*hclk_vio_bus*/
313 <&clk_gates9 5>,/*hclk_lcdc*/
316 <&clk_gates6 13>,/*aclk_vio*/
317 <&clk_gates9 6>,/*aclk_lcdc*/
322 <&clk_gates8 2>,/*pclk_uart2*/
327 <&clk_gates1 3>;/*clk_jtag*/
331 compatible = "rockchip,rk30-i2c";
332 reg = <0x20072000 0x1000>;
333 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
334 #address-cells = <1>;
336 pinctrl-names = "default", "gpio";
337 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
338 pinctrl-1 = <&i2c0_gpio>;
339 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
340 clocks = <&clk_gates8 4>;
341 rockchip,check-idle = <1>;
346 compatible = "rockchip,rk30-i2c";
347 reg = <0x20056000 0x1000>;
348 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
349 #address-cells = <1>;
351 pinctrl-names = "default", "gpio";
352 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
353 pinctrl-1 = <&i2c1_gpio>;
354 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
355 clocks = <&clk_gates8 5>;
356 rockchip,check-idle = <1>;
361 compatible = "rockchip,rk30-i2c";
362 reg = <0x2005a000 0x1000>;
363 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
364 #address-cells = <1>;
366 pinctrl-names = "default", "gpio";
367 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
368 pinctrl-1 = <&i2c2_gpio>;
369 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
370 clocks = <&clk_gates8 6>;
371 rockchip,check-idle = <1>;
376 compatible = "rockchip-i2s";
377 reg = <0x10220000 0x1000>;
379 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
380 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
381 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
382 dmas = <&pdma 0>, <&pdma 1>;
384 dma-names = "tx", "rx";
385 //pinctrl-names = "default", "sleep";
386 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
387 //pinctrl-1 = <&i2s_gpio>;
390 codec: codec@20030000 {
391 compatible = "rk3036-codec";
392 reg = <0x20030000 0x1000>;
393 spk_ctl_io = <&gpio1 GPIO_A0 0>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&i2s0_gpio>;
398 pa_enable_time = <1000>;
399 clocks = <&clk_gates5 14>;
400 clock-names = "g_pclk_acodec";
403 spdif: spdif@10204000 {
404 compatible = "rockchip-spdif";
405 reg = <0x10204000 0x1000>;
406 clocks = <&clk_spdif>;
407 clock-names = "spdif_mclk";
408 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&spdif_tx>;
417 compatible = "rockchip,rk-pwm";
418 reg = <0x20050000 0x10>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&pwm0_pin>;
422 clocks = <&clk_gates7 10>;
423 clock-names = "pclk_pwm";
428 compatible = "rockchip,rk-pwm";
429 reg = <0x20050010 0x10>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&pwm1_pin>;
433 clocks = <&clk_gates7 10>;
434 clock-names = "pclk_pwm";
439 compatible = "rockchip,rk-pwm";
440 reg = <0x20050020 0x10>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&pwm2_pin>;
444 clocks = <&clk_gates7 10>;
445 clock-names = "pclk_pwm";
450 compatible = "rockchip,rk-pwm";
451 reg = <0x20050030 0x10>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&pwm3_pin>;
455 clocks = <&clk_gates7 10>;
456 clock-names = "pclk_pwm";
460 remotectl: pwm@20050030 {
461 compatible = "rockchip,remotectl-pwm";
462 reg = <0x20050030 0x10>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&pwm3_pin>;
466 clocks = <&clk_gates7 10>;
467 clock-names = "pclk_pwm";
468 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
472 emmc: rksdmmc@1021c000 {
473 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
474 reg = <0x1021c000 0x4000>;
475 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
476 #address-cells = <1>;
478 //pinctrl-names = "default",,"suspend";
479 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
480 clocks = <&clk_emmc>, <&clk_gates7 0>;
481 clock-names = "clk_mmc", "hclk_mmc";
483 dma-names = "dw_mci";
485 fifo-depth = <0x100>;
490 sdmmc: rksdmmc@10214000 {
491 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
492 reg = <0x10214000 0x4000>;
493 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
494 #address-cells = <1>;
496 pinctrl-names = "default", "idle";
497 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
498 pinctrl-1 = <&sdmmc0_gpio>;
499 cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
500 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
501 clock-names = "clk_mmc", "hclk_mmc";
503 dma-names = "dw_mci";
505 fifo-depth = <0x100>;
509 sdio: rksdmmc@10218000 {
510 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
511 reg = <0x10218000 0x4000>;
512 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
513 #address-cells = <1>;
515 pinctrl-names = "default","idle";
516 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
517 pinctrl-1 = <&sdio0_gpio>;
518 clocks = <&clk_sdio>, <&clk_gates5 11>;
519 clock-names = "clk_mmc", "hclk_mmc";
521 dma-names = "dw_mci";
523 fifo-depth = <0x100>;
527 compatible = "arm,mali400";
528 reg = <0x10091000 0x200>,
533 reg-names = "Mali_L2",
539 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
543 interrupt-names = "Mali_GP_IRQ",
548 dwc_control_usb: dwc-control-usb@20008000 {
549 compatible = "rockchip,rk3036-dwc-control-usb";
550 reg = <0x20008000 0x4>;
551 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
552 interrupt-names = "otg_bvalid";
553 clocks = <&clk_gates9 13>;
554 clock-names = "hclk_usb_peri";
555 rockchip,remote_wakeup;
556 rockchip,usb_irq_wakeup;
557 resets = <&reset RK3036_RST_USBPOR>;
558 reset-names = "usbphy_por";
560 compatible = "rockchip,ctrl";
561 rk_usb,bvalid = <0x14c 8 1>;
562 rk_usb,iddig = <0x14c 11 1>;
563 rk_usb,line = <0x14c 9 2>;
564 rk_usb,softctrl = <0x17c 0 1>;
565 rk_usb,opmode = <0x17c 2 2>;
566 rk_usb,xcvrsel = <0x17c 4 2>;
567 rk_usb,termsel = <0x17c 6 1>;
571 compatible = "rockchip,rk3036_usb20_otg";
572 reg = <0x10180000 0x40000>;
573 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
575 clock-names = "clk_usbphy0", "hclk_usb0";
576 resets = <&reset RK3036_RST_USBOTG0>, <&reset RK3036_RST_UTMI0>,
577 <&reset RK3036_RST_OTGC0>;
578 reset-names = "otg_ahb", "otg_phy", "otg_controller";
579 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
580 rockchip,usb-mode = <0>;
584 compatible = "rockchip,rk3036_usb20_host";
585 reg = <0x101c0000 0x40000>;
586 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
588 clock-names = "clk_usbphy1", "hclk_usb1";
589 resets = <&reset RK3036_RST_USBOTG1>, <&reset RK3036_RST_UTMI1>,
590 <&reset RK3036_RST_OTGC1>;
591 reset-names = "host_ahb", "host_phy", "host_controller";
595 compatible = "rockchip,rk-fb";
596 rockchip,disp-mode = <NO_DUAL>;
599 rk_screen: rk_screen{
600 compatible = "rockchip,screen";
603 lcdc: lcdc@10118000 {
604 compatible = "rockchip,rk3036-lcdc";
605 reg = <0x10118000 0x200>;
606 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
609 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
610 rockchip,iommu-enabled = <1>;
613 hdmi: hdmi@20034000 {
614 compatible = "rockchip,rk3036-hdmi";
615 reg = <0x20034000 0x4000>;
616 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
617 rockchip,hdmi_lcdc_source = <0>;
618 pinctrl-names = "default", "gpio";
619 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
620 pinctrl-1 = <&hdmi_gpio>;
621 clocks = <&clk_gates3 8>;
622 clock-names = "pclk_hdmi";
627 compatible = "rockchip,rk3036-tve";
628 reg = <0x10118200 0x100>;
633 compatible = "rockchip,ion";
634 #address-cells = <1>;
637 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
638 compatible = "rockchip,ion-reserve";
639 rockchip,ion_heap = <1>;
640 reg = <0x00000000 0x00000000>; /* 0MB */
642 rockchip,ion-heap@3 { /* VMALLOC HEAP */
643 rockchip,ion_heap = <3>;
647 vpu: vpu_service@10108000 {
648 compatible = "vpu_service";
650 reg = <0x10108000 0x800>;
651 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
652 interrupt-names = "irq_dec";
653 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>;
654 clock-names = "aclk_vcodec", "hclk_vcodec";
655 name = "vpu_service";
659 hevc: hevc_service@1010c000 {
660 compatible = "rockchip,hevc_service";
662 reg = <0x1010c000 0x400>;
663 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
664 interrupt-names = "irq_dec";
665 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
666 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
667 name = "hevc_service";
673 compatible = "rockchip,vop_mmu";
674 reg = <0x10118300 0x100>;
675 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
676 interrupt-names = "vop_mmu";
681 compatible = "rockchip,hevc_mmu";
682 reg = <0x1010c440 0x40>,
684 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
685 interrupt-names = "hevc_mmu";
690 compatible = "rockchip,vpu_mmu";
691 reg = <0x10108800 0x100>;
692 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
693 interrupt-names = "vpu_mmu";
702 |RKPM_CTR_IDLESRAM_MD
705 //|RKPM_CTR_SYSCLK_DIV
706 //|RKPM_CTR_IDLEAUTO_MD
707 //|RKPM_CTR_ARMOFF_LPMD
708 //|RKPM_CTR_ARMOFF_LOGDP_LPMD
712 rockchip,pmic-suspend_gpios = <
713 RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
715 rockchip,pmic-resume_gpios = <
716 RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
722 compatible = "rockchip,vmac";
723 reg = <0x10200000 0x4000>;
724 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
725 interrupt-names = "macirq";
726 clocks = <&clk_mac_pll>, <&clk_mac_ref>,
727 <&clk_mac_pll_div>, <&clk_mac_ref_div>,
728 <&clk_gates2 6>, <&clk_gates3 5>;
729 clock-names = "clk_mac_pll", "clk_mac_ref",
730 "clk_mac_pll_div", "clk_mac_ref_div",
731 "clk_tx_rx_gate", "hclk_mac";
732 pinctrl-names = "default";
733 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_crs &mac_mdpins>;