1 #include <dt-bindings/interrupt-controller/arm-gic.h>
3 #include "skeleton.dtsi"
4 #include "rk3036-clocks.dtsi"
5 #include "rk3036-pinctrl.dtsi"
8 compatible = "rockchip,rk3036";
9 rockchip,sram = <&sram>;
10 interrupt-parent = <&gic>;
28 compatible = "arm,cortex-a7";
33 compatible = "arm,cortex-a7";
38 gic: interrupt-controller@10139000 {
39 compatible = "arm,cortex-a15-gic";
41 #interrupt-cells = <3>;
43 reg = <0x10139000 0x1000>,
48 compatible = "arm,cortex-a7-pmu";
49 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
53 cpu_axi_bus: cpu_axi_bus {
54 compatible = "rockchip,cpu_axi_bus";
65 reg = <0x1012a000 0x20>;
66 rockchip,priority = <3 2>;
69 reg = <0x1012c000 0x20>;
72 reg = <0x1012d000 0x20>;
75 reg = <0x1012e000 0x20>;
78 reg = <0x1012e080 0x20>;
81 reg = <0x1012f000 0x20>;
82 rockchip,priority = <3 3>;
92 reg = <0x10128000 0x40>;
93 rockchip,read-latency = <0x80>;
99 compatible = "mmio-sram";
100 reg = <0x10080000 0x2000>;
105 compatible = "arm,armv7-timer";
106 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
107 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
108 clock-frequency = <24000000>;
112 compatible = "rockchip,timer";
113 reg = <0x20044000 0x20>;
114 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
115 rockchip,broadcast = <1>;
118 watchdog: wdt@2004c000 {
119 compatible = "rockchip,watch dog";
120 reg = <0x2004c000 0x100>;
121 clocks = <&clk_gates7 15>;
122 clock-names = "pclk_wdt";
123 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
125 rockchip,timeout = <60>;
126 rockchip,atboot = <1>;
127 rockchip,debug = <0>;
132 #address-cells = <1>;
134 compatible = "arm,amba-bus";
135 interrupt-parent = <&gic>;
138 pdma: pdma@20078000 {
139 compatible = "arm,pl330", "arm,primecell";
140 reg = <0x20078000 0x4000>;
141 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
147 reset: reset@20000110{
148 compatible = "rockchip,reset";
149 reg = <0x20000110 0x24>;
150 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
154 nandc: nandc@10500000 {
155 compatible = "rockchip,rk-nandc";
156 reg = <0x10500000 0x4000>;
157 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
158 //pinctrl-names = "default";
159 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
161 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 4>;
162 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
165 nandc0reg: nandc0@10500000 {
166 compatible = "rockchip,rk-nandc";
167 reg = <0x10500000 0x4000>;
171 compatible = "rockchip,rockchip-spi";
172 reg = <0x20074000 0x1000>;
173 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
174 #address-cells = <1>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
178 rockchip,spi-src-clk = <0>;
180 clocks =<&clk_spi0>, <&clk_gates2 9>;
181 clock-names = "spi","pclk_spi0";
182 dmas = <&pdma 8>, <&pdma 9>;
184 dma-names = "tx", "rx";
188 uart0: serial@20060000 {
189 compatible = "rockchip,serial";
190 reg = <0x20060000 0x100>;
191 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
192 clock-frequency = <24000000>;
193 clocks = <&clk_uart0>, <&clk_gates8 0>;
194 clock-names = "sclk_uart", "pclk_uart";
197 dmas = <&pdma 2>, <&pdma 3>;
199 pinctrl-names = "default";
200 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
204 uart1: serial@20064000 {
205 compatible = "rockchip,serial";
206 reg = <0x20064000 0x100>;
207 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
208 clock-frequency = <24000000>;
209 clocks = <&clk_uart1>, <&clk_gates8 1>;
210 clock-names = "sclk_uart", "pclk_uart";
213 dmas = <&pdma 4>, <&pdma 5>;
215 pinctrl-names = "default";
216 pinctrl-0 = <&uart1_xfer>;
220 uart2: serial@20068000 {
221 compatible = "rockchip,serial";
222 reg = <0x20068000 0x100>;
223 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
224 clock-frequency = <24000000>;
225 clocks = <&clk_uart2>, <&clk_gates8 2>;
226 clock-names = "sclk_uart", "pclk_uart";
229 dmas = <&pdma 6>, <&pdma 7>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&uart2_xfer>;
237 compatible = "rockchip,fiq-debugger";
238 rockchip,serial-id = <2>;
239 rockchip,signal-irq = <106>;
240 rockchip,wake-irq = <0>;
245 compatible = "rockchip,clocks-init";
246 rockchip,clocks-init-parent =
247 <&clk_core &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
248 <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
249 <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
250 <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
251 <&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>;
252 rockchip,clocks-init-rate =
253 <&clk_core 1000000000>, <&clk_gpll 594000000>,
254 <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
255 <&pclk_cpu_pre 75000000>, <&aclk_peri_pre 150000000>,
256 <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
257 <&clk_gpu 300000000>, <&aclk_vio_pre 300000000>,
258 <&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
259 <&clk_hevc_core 200000000>, <&clk_mac_pll_div 50000000>,
260 <&clk_mac_ref_div 25000000>;
261 /* rockchip,clocks-uboot-has-init =
266 compatible = "rockchip,clocks-enable";
269 <&clk_gates0 0>, <&clk_gates0 7>,
272 <&clk_gates0 3>, <&clk_gates0 4>,
276 <&clk_gates1 0>, <&clk_gates1 1>,
277 <&clk_gates2 4>, <&clk_gates2 5>,
280 <&clk_gates2 0>, <&hclk_peri_pre>,
281 <&pclk_peri_pre>, <&clk_gates2 1>,
284 <&clk_gates4 12>,/*aclk_intmem*/
285 <&clk_gates4 10>,/*aclk_strc_sys*/
288 <&clk_gates5 6>,/*hclk_rom*/
291 <&clk_gates5 4>,/*pclk_grf*/
292 <&clk_gates5 7>,/*pclk_ddrupctl*/
293 <&clk_gates5 14>,/*pclk_acodec*/
294 <&clk_gates3 8>,/*pclk_hdmi*/
297 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
298 <&clk_gates5 1>,/*aclk_dmac2*/
299 <&clk_gates9 15>,/*aclk_peri_niu*/
300 <&clk_gates4 2>,/*aclk_cpu_peri*/
303 <&clk_gates4 0>,/*hclk_peri_matrix*/
304 <&clk_gates9 13>,/*hclk_usb_peri*/
305 <&clk_gates9 14>,/*hclk_peri_arbi*/
308 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
311 <&clk_gates6 12>,/*hclk_vio_bus*/
312 <&clk_gates9 5>,/*hclk_lcdc*/
315 <&clk_gates6 13>,/*aclk_vio*/
316 <&clk_gates9 6>,/*aclk_lcdc*/
321 <&clk_gates8 2>,/*pclk_uart2*/
326 <&clk_gates1 3>;/*clk_jtag*/
330 compatible = "rockchip,rk30-i2c";
331 reg = <0x20072000 0x1000>;
332 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
333 #address-cells = <1>;
335 pinctrl-names = "default", "gpio";
336 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
337 pinctrl-1 = <&i2c0_gpio>;
338 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
339 clocks = <&clk_gates8 4>;
340 rockchip,check-idle = <1>;
345 compatible = "rockchip,rk30-i2c";
346 reg = <0x20056000 0x1000>;
347 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
350 pinctrl-names = "default", "gpio";
351 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
352 pinctrl-1 = <&i2c1_gpio>;
353 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
354 clocks = <&clk_gates8 5>;
355 rockchip,check-idle = <1>;
360 compatible = "rockchip,rk30-i2c";
361 reg = <0x2005a000 0x1000>;
362 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
363 #address-cells = <1>;
365 pinctrl-names = "default", "gpio";
366 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
367 pinctrl-1 = <&i2c2_gpio>;
368 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
369 clocks = <&clk_gates8 6>;
370 rockchip,check-idle = <1>;
375 compatible = "rockchip-i2s";
376 reg = <0x10220000 0x1000>;
378 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
379 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
380 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
381 dmas = <&pdma 0>, <&pdma 1>;
383 dma-names = "tx", "rx";
384 //pinctrl-names = "default", "sleep";
385 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
386 //pinctrl-1 = <&i2s_gpio>;
389 codec: codec@20030000 {
390 compatible = "rk3036-codec";
391 reg = <0x20030000 0x1000>;
392 spk_ctl_io = <&gpio1 GPIO_A0 0>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&i2s0_gpio>;
397 pa_enable_time = <1000>;
398 clocks = <&clk_gates5 14>;
399 clock-names = "g_pclk_acodec";
402 spdif: spdif@10204000 {
403 compatible = "rockchip-spdif";
404 reg = <0x10204000 0x1000>;
405 clocks = <&clk_spdif>;
406 clock-names = "spdif_mclk";
407 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&spdif_tx>;
416 compatible = "rockchip,rk-pwm";
417 reg = <0x20050000 0x10>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&pwm0_pin>;
421 clocks = <&clk_gates7 10>;
422 clock-names = "pclk_pwm";
427 compatible = "rockchip,rk-pwm";
428 reg = <0x20050010 0x10>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&pwm1_pin>;
432 clocks = <&clk_gates7 10>;
433 clock-names = "pclk_pwm";
438 compatible = "rockchip,rk-pwm";
439 reg = <0x20050020 0x10>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&pwm2_pin>;
443 clocks = <&clk_gates7 10>;
444 clock-names = "pclk_pwm";
449 compatible = "rockchip,rk-pwm";
450 reg = <0x20050030 0x10>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pwm3_pin>;
454 clocks = <&clk_gates7 10>;
455 clock-names = "pclk_pwm";
459 remotectl: pwm@20050030 {
460 compatible = "rockchip,remotectl-pwm";
461 reg = <0x20050030 0x10>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&pwm3_pin>;
465 clocks = <&clk_gates7 10>;
466 clock-names = "pclk_pwm";
467 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
471 emmc: rksdmmc@1021c000 {
472 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
473 reg = <0x1021c000 0x4000>;
474 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
475 #address-cells = <1>;
477 //pinctrl-names = "default",,"suspend";
478 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
479 clocks = <&clk_emmc>, <&clk_gates7 0>;
480 clock-names = "clk_mmc", "hclk_mmc";
482 dma-names = "dw_mci";
484 fifo-depth = <0x100>;
489 sdmmc: rksdmmc@10214000 {
490 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
491 reg = <0x10214000 0x4000>;
492 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
493 #address-cells = <1>;
495 pinctrl-names = "default", "idle";
496 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
497 pinctrl-1 = <&sdmmc0_gpio>;
498 cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
499 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
500 clock-names = "clk_mmc", "hclk_mmc";
502 dma-names = "dw_mci";
504 fifo-depth = <0x100>;
508 sdio: rksdmmc@10218000 {
509 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
510 reg = <0x10218000 0x4000>;
511 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
512 #address-cells = <1>;
514 pinctrl-names = "default","idle";
515 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
516 pinctrl-1 = <&sdio0_gpio>;
517 clocks = <&clk_sdio>, <&clk_gates5 11>;
518 clock-names = "clk_mmc", "hclk_mmc";
520 dma-names = "dw_mci";
522 fifo-depth = <0x100>;
526 compatible = "arm,mali400";
527 reg = <0x10091000 0x200>,
532 reg-names = "Mali_L2",
538 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
542 interrupt-names = "Mali_GP_IRQ",
547 dwc_control_usb: dwc-control-usb@20008000 {
548 compatible = "rockchip,rk3036-dwc-control-usb";
549 reg = <0x20008000 0x4>;
550 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
551 interrupt-names = "otg_bvalid";
552 clocks = <&clk_gates9 13>;
553 clock-names = "hclk_usb_peri";
554 rockchip,remote_wakeup;
555 rockchip,usb_irq_wakeup;
556 resets = <&reset RK3036_RST_USBPOR>;
557 reset-names = "usbphy_por";
559 compatible = "rockchip,ctrl";
560 rk_usb,bvalid = <0x14c 8 1>;
561 rk_usb,iddig = <0x14c 11 1>;
562 rk_usb,line = <0x14c 9 2>;
563 rk_usb,softctrl = <0x17c 0 1>;
564 rk_usb,opmode = <0x17c 2 2>;
565 rk_usb,xcvrsel = <0x17c 4 2>;
566 rk_usb,termsel = <0x17c 6 1>;
570 compatible = "rockchip,rk3036_usb20_otg";
571 reg = <0x10180000 0x40000>;
572 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
574 clock-names = "clk_usbphy0", "hclk_usb0";
575 resets = <&reset RK3036_RST_USBOTG0>, <&reset RK3036_RST_UTMI0>,
576 <&reset RK3036_RST_OTGC0>;
577 reset-names = "otg_ahb", "otg_phy", "otg_controller";
578 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
579 rockchip,usb-mode = <0>;
583 compatible = "rockchip,rk3036_usb20_host";
584 reg = <0x101c0000 0x40000>;
585 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
587 clock-names = "clk_usbphy1", "hclk_usb1";
588 resets = <&reset RK3036_RST_USBOTG1>, <&reset RK3036_RST_UTMI1>,
589 <&reset RK3036_RST_OTGC1>;
590 reset-names = "host_ahb", "host_phy", "host_controller";
594 compatible = "rockchip,rk-fb";
595 rockchip,disp-mode = <NO_DUAL>;
598 rk_screen: rk_screen{
599 compatible = "rockchip,screen";
602 lcdc: lcdc@10118000 {
603 compatible = "rockchip,rk3036-lcdc";
604 reg = <0x10118000 0x200>;
605 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
608 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
609 rockchip,iommu-enabled = <1>;
612 hdmi: hdmi@20034000 {
613 compatible = "rockchip,rk3036-hdmi";
614 reg = <0x20034000 0x4000>;
615 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
616 rockchip,hdmi_lcdc_source = <0>;
617 pinctrl-names = "default", "gpio";
618 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
619 pinctrl-1 = <&hdmi_gpio>;
620 clocks = <&clk_gates3 8>;
621 clock-names = "pclk_hdmi";
626 compatible = "rockchip,rk3036-tve";
627 reg = <0x10118200 0x100>;
632 compatible = "rockchip,ion";
633 #address-cells = <1>;
636 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
637 compatible = "rockchip,ion-reserve";
638 rockchip,ion_heap = <1>;
639 reg = <0x00000000 0x00000000>; /* 0MB */
641 rockchip,ion-heap@3 { /* VMALLOC HEAP */
642 rockchip,ion_heap = <3>;
646 vpu: vpu_service@10108000 {
647 compatible = "vpu_service";
649 reg = <0x10108000 0x800>;
650 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
651 interrupt-names = "irq_dec";
652 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>;
653 clock-names = "aclk_vcodec", "hclk_vcodec";
654 name = "vpu_service";
658 hevc: hevc_service@1010c000 {
659 compatible = "rockchip,hevc_service";
661 reg = <0x1010c000 0x400>;
662 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
663 interrupt-names = "irq_dec";
664 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
665 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
666 name = "hevc_service";
672 compatible = "iommu,vop_mmu";
673 reg = <0x10118300 0x100>;
674 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
675 interrupt-names = "vop_mmu";
680 compatible = "iommu,hevc_mmu";
681 reg = <0x1010c440 0x100>,
683 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
684 interrupt-names = "hevc_mmu";
689 compatible = "iommu,vpu_mmu";
690 reg = <0x10108800 0x100>;
691 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
692 interrupt-names = "vpu_mmu";
696 compatible = "rockchip,vmac";
697 reg = <0x10200000 0x4000>;
698 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
699 interrupt-names = "macirq";
700 clocks = <&clk_mac_pll>, <&clk_mac_ref>,
701 <&clk_mac_pll_div>, <&clk_mac_ref_div>,
702 <&clk_gates2 6>, <&clk_gates3 5>;
703 clock-names = "clk_mac_pll", "clk_mac_ref",
704 "clk_mac_pll_div", "clk_mac_ref_div",
705 "clk_tx_rx_gate", "hclk_mac";
706 pinctrl-names = "default";
707 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_crs &mac_mdpins>;