arch/arm/boot/dts/rk3036.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3036-cru.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         compatible = "rockchip,rk3036";
  50
  51         interrupt-parent = <&gic>;
  52
  53         aliases {
  54                 i2c0 = &i2c0;
  55                 i2c1 = &i2c1;
  56                 i2c2 = &i2c2;
  57                 mshc0 = &emmc;
  58                 mshc1 = &sdmmc;
  59                 mshc2 = &sdio;
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 spi = &spi;
  64         };
  65
  66         memory {
  67                 device_type = "memory";
  68                 reg = <0x60000000 0x40000000>;
  69         };
  70
  71         cpus {
  72                 #address-cells = <1>;
  73                 #size-cells = <0>;
  74                 enable-method = "rockchip,rk3036-smp";
  75
  76                 cpu0: cpu@f00 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a7";
  79                         reg = <0xf00>;
  80                         resets = <&cru SRST_CORE0>;
  81                         operating-points = <
  82                                 /* KHz    uV */
  83                                  816000 1000000
  84                         >;
  85                         clock-latency = <40000>;
  86                         clocks = <&cru ARMCLK>;
  87                 };
  88
  89                 cpu1: cpu@f01 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a7";
  92                         reg = <0xf01>;
  93                         resets = <&cru SRST_CORE1>;
  94                 };
  95         };
  96
  97         amba {
  98                 compatible = "arm,amba-bus";
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges;
 102
 103                 pdma: pdma@20078000 {
 104                         compatible = "arm,pl330", "arm,primecell";
 105                         reg = <0x20078000 0x4000>;
 106                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 107                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 108                         #dma-cells = <1>;
 109                         clocks = <&cru ACLK_DMAC2>;
 110                         clock-names = "apb_pclk";
 111                 };
 112         };
 113
 114         arm-pmu {
 115                 compatible = "arm,cortex-a7-pmu";
 116                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 117                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 118                 interrupt-affinity = <&cpu0>, <&cpu1>;
 119         };
 120
 121         timer {
 122                 compatible = "arm,armv7-timer";
 123                 arm,cpu-registers-not-fw-configured;
 124                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 125                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 126                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 127                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 128                 clock-frequency = <24000000>;
 129         };
 130
 131         xin24m: oscillator {
 132                 compatible = "fixed-clock";
 133                 clock-frequency = <24000000>;
 134                 clock-output-names = "xin24m";
 135                 #clock-cells = <0>;
 136         };
 137
 138         bus_intmem@10080000 {
 139                 compatible = "mmio-sram";
 140                 reg = <0x10080000 0x2000>;
 141                 #address-cells = <1>;
 142                 #size-cells = <1>;
 143                 ranges = <0 0x10080000 0x2000>;
 144
 145                 smp-sram@0 {
 146                         compatible = "rockchip,rk3066-smp-sram";
 147                         reg = <0x00 0x10>;
 148                 };
 149         };
 150
 151         gic: interrupt-controller@10139000 {
 152                 compatible = "arm,gic-400";
 153                 interrupt-controller;
 154                 #interrupt-cells = <3>;
 155                 #address-cells = <0>;
 156
 157                 reg = <0x10139000 0x1000>,
 158                       <0x1013a000 0x1000>,
 159                       <0x1013c000 0x2000>,
 160                       <0x1013e000 0x2000>;
 161                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 162         };
 163
 164         usb_otg: usb@10180000 {
 165                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 166                                 "snps,dwc2";
 167                 reg = <0x10180000 0x40000>;
 168                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 169                 clocks = <&cru HCLK_OTG0>;
 170                 clock-names = "otg";
 171                 dr_mode = "otg";
 172                 g-np-tx-fifo-size = <16>;
 173                 g-rx-fifo-size = <275>;
 174                 g-tx-fifo-size = <256 128 128 64 64 32>;
 175                 g-use-dma;
 176                 status = "disabled";
 177         };
 178
 179         usb_host: usb@101c0000 {
 180                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 181                                 "snps,dwc2";
 182                 reg = <0x101c0000 0x40000>;
 183                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 184                 clocks = <&cru HCLK_OTG1>;
 185                 clock-names = "otg";
 186                 dr_mode = "host";
 187                 status = "disabled";
 188         };
 189
 190         sdmmc: dwmmc@10214000 {
 191                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 192                 reg = <0x10214000 0x4000>;
 193                 clock-frequency = <37500000>;
 194                 clock-freq-min-max = <400000 37500000>;
 195                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 196                 clock-names = "biu", "ciu";
 197                 fifo-depth = <0x100>;
 198                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 199                 status = "disabled";
 200         };
 201
 202         sdio: dwmmc@10218000 {
 203                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 204                 reg = <0x10218000 0x4000>;
 205                 clock-freq-min-max = <400000 37500000>;
 206                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 207                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 208                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 209                 fifo-depth = <0x100>;
 210                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 211                 status = "disabled";
 212         };
 213
 214         emmc: dwmmc@1021c000 {
 215                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 216                 reg = <0x1021c000 0x4000>;
 217                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 218                 broken-cd;
 219                 bus-width = <8>;
 220                 cap-mmc-highspeed;
 221                 clock-frequency = <37500000>;
 222                 clock-freq-min-max = <400000 37500000>;
 223                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 224                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 225                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 226                 default-sample-phase = <158>;
 227                 disable-wp;
 228                 dmas = <&pdma 12>;
 229                 dma-names = "rx-tx";
 230                 fifo-depth = <0x100>;
 231                 mmc-ddr-1_8v;
 232                 non-removable;
 233                 num-slots = <1>;
 234                 pinctrl-names = "default";
 235                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 236                 status = "disabled";
 237         };
 238
 239         i2s: i2s@10220000 {
 240                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 241                 reg = <0x10220000 0x4000>;
 242                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 243                 #address-cells = <1>;
 244                 #size-cells = <0>;
 245                 clock-names = "i2s_clk", "i2s_hclk";
 246                 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 247                 dmas = <&pdma 0>, <&pdma 1>;
 248                 dma-names = "tx", "rx";
 249                 pinctrl-names = "default";
 250                 pinctrl-0 = <&i2s_bus>;
 251                 status = "disabled";
 252         };
 253
 254         cru: clock-controller@20000000 {
 255                 compatible = "rockchip,rk3036-cru";
 256                 reg = <0x20000000 0x1000>;
 257                 rockchip,grf = <&grf>;
 258                 #clock-cells = <1>;
 259                 #reset-cells = <1>;
 260                 assigned-clocks = <&cru PLL_GPLL>;
 261                 assigned-clock-rates = <594000000>;
 262         };
 263
 264         grf: syscon@20008000 {
 265                 compatible = "rockchip,rk3036-grf", "syscon";
 266                 reg = <0x20008000 0x1000>;
 267         };
 268
 269         acodec: acodec-ana@20030000 {
 270                 compatible = "rk3036-codec";
 271                 reg = <0x20030000 0x4000>;
 272                 rockchip,grf = <&grf>;
 273                 clock-names = "acodec_pclk";
 274                 clocks = <&cru PCLK_ACODEC>;
 275                 status = "disabled";
 276         };
 277
 278         timer: timer@20044000 {
 279                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 280                 reg = <0x20044000 0x20>;
 281                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 282                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 283                 clock-names = "timer", "pclk";
 284         };
 285
 286         pwm0: pwm@20050000 {
 287                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 288                 reg = <0x20050000 0x10>;
 289                 #pwm-cells = <3>;
 290                 clocks = <&cru PCLK_PWM>;
 291                 clock-names = "pwm";
 292                 pinctrl-names = "default";
 293                 pinctrl-0 = <&pwm0_pin>;
 294                 status = "disabled";
 295         };
 296
 297         pwm1: pwm@20050010 {
 298                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 299                 reg = <0x20050010 0x10>;
 300                 #pwm-cells = <3>;
 301                 clocks = <&cru PCLK_PWM>;
 302                 clock-names = "pwm";
 303                 pinctrl-names = "default";
 304                 pinctrl-0 = <&pwm1_pin>;
 305                 status = "disabled";
 306         };
 307
 308         pwm2: pwm@20050020 {
 309                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 310                 reg = <0x20050020 0x10>;
 311                 #pwm-cells = <3>;
 312                 clocks = <&cru PCLK_PWM>;
 313                 clock-names = "pwm";
 314                 pinctrl-names = "default";
 315                 pinctrl-0 = <&pwm2_pin>;
 316                 status = "disabled";
 317         };
 318
 319         pwm3: pwm@20050030 {
 320                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 321                 reg = <0x20050030 0x10>;
 322                 #pwm-cells = <2>;
 323                 clocks = <&cru PCLK_PWM>;
 324                 clock-names = "pwm";
 325                 pinctrl-names = "default";
 326                 pinctrl-0 = <&pwm3_pin>;
 327                 status = "disabled";
 328         };
 329
 330         i2c1: i2c@20056000 {
 331                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 332                 reg = <0x20056000 0x1000>;
 333                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 clock-names = "i2c";
 337                 clocks = <&cru PCLK_I2C1>;
 338                 pinctrl-names = "default";
 339                 pinctrl-0 = <&i2c1_xfer>;
 340                 status = "disabled";
 341         };
 342
 343         i2c2: i2c@2005a000 {
 344                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 345                 reg = <0x2005a000 0x1000>;
 346                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 clock-names = "i2c";
 350                 clocks = <&cru PCLK_I2C2>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&i2c2_xfer>;
 353                 status = "disabled";
 354         };
 355
 356         uart0: serial@20060000 {
 357                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 358                 reg = <0x20060000 0x100>;
 359                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 360                 reg-shift = <2>;
 361                 reg-io-width = <4>;
 362                 clock-frequency = <24000000>;
 363                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 364                 clock-names = "baudclk", "apb_pclk";
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 367                 status = "disabled";
 368         };
 369
 370         uart1: serial@20064000 {
 371                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 372                 reg = <0x20064000 0x100>;
 373                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 374                 reg-shift = <2>;
 375                 reg-io-width = <4>;
 376                 clock-frequency = <24000000>;
 377                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 378                 clock-names = "baudclk", "apb_pclk";
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&uart1_xfer>;
 381                 status = "disabled";
 382         };
 383
 384         uart2: serial@20068000 {
 385                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 386                 reg = <0x20068000 0x100>;
 387                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 388                 reg-shift = <2>;
 389                 reg-io-width = <4>;
 390                 clock-frequency = <24000000>;
 391                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 392                 clock-names = "baudclk", "apb_pclk";
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&uart2_xfer>;
 395                 status = "disabled";
 396         };
 397
 398         i2c0: i2c@20072000 {
 399                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 400                 reg = <0x20072000 0x1000>;
 401                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 clock-names = "i2c";
 405                 clocks = <&cru PCLK_I2C0>;
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&i2c0_xfer>;
 408                 status = "disabled";
 409         };
 410
 411         spi: spi@20074000 {
 412                 compatible = "rockchip,rockchip-spi";
 413                 reg = <0x20074000 0x1000>;
 414                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
 416                 clock-names = "apb-pclk","spi_pclk";
 417                 dmas = <&pdma 8>, <&pdma 9>;
 418                 dma-names = "tx", "rx";
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
 421                 #address-cells = <1>;
 422                 #size-cells = <0>;
 423                 status = "disabled";
 424         };
 425
 426         pinctrl: pinctrl {
 427                 compatible = "rockchip,rk3036-pinctrl";
 428                 rockchip,grf = <&grf>;
 429                 #address-cells = <1>;
 430                 #size-cells = <1>;
 431                 ranges;
 432
 433                 gpio0: gpio0@2007c000 {
 434                         compatible = "rockchip,gpio-bank";
 435                         reg = <0x2007c000 0x100>;
 436                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 437                         clocks = <&cru PCLK_GPIO0>;
 438
 439                         gpio-controller;
 440                         #gpio-cells = <2>;
 441
 442                         interrupt-controller;
 443                         #interrupt-cells = <2>;
 444                 };
 445
 446                 gpio1: gpio1@20080000 {
 447                         compatible = "rockchip,gpio-bank";
 448                         reg = <0x20080000 0x100>;
 449                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 450                         clocks = <&cru PCLK_GPIO1>;
 451
 452                         gpio-controller;
 453                         #gpio-cells = <2>;
 454
 455                         interrupt-controller;
 456                         #interrupt-cells = <2>;
 457                 };
 458
 459                 gpio2: gpio2@20084000 {
 460                         compatible = "rockchip,gpio-bank";
 461                         reg = <0x20084000 0x100>;
 462                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 463                         clocks = <&cru PCLK_GPIO2>;
 464
 465                         gpio-controller;
 466                         #gpio-cells = <2>;
 467
 468                         interrupt-controller;
 469                         #interrupt-cells = <2>;
 470                 };
 471
 472                 pcfg_pull_default: pcfg_pull_default {
 473                         bias-pull-pin-default;
 474                 };
 475
 476                 pcfg_pull_none: pcfg-pull-none {
 477                         bias-disable;
 478                 };
 479
 480                 pwm0 {
 481                         pwm0_pin: pwm0-pin {
 482                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
 483                         };
 484                 };
 485
 486                 pwm1 {
 487                         pwm1_pin: pwm1-pin {
 488                                 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
 489                         };
 490                 };
 491
 492                 pwm2 {
 493                         pwm2_pin: pwm2-pin {
 494                                 rockchip,pins = <0 1 2 &pcfg_pull_none>;
 495                         };
 496                 };
 497
 498                 pwm3 {
 499                         pwm3_pin: pwm3-pin {
 500                                 rockchip,pins = <0 27 1 &pcfg_pull_none>;
 501                         };
 502                 };
 503
 504                 sdmmc {
 505                         sdmmc_clk: sdmmc-clk {
 506                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
 507                         };
 508
 509                         sdmmc_cmd: sdmmc-cmd {
 510                                 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
 511                         };
 512
 513                         sdmmc_cd: sdmcc-cd {
 514                                 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
 515                         };
 516
 517                         sdmmc_bus1: sdmmc-bus1 {
 518                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
 519                         };
 520
 521                         sdmmc_bus4: sdmmc-bus4 {
 522                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
 523                                                 <1 19 RK_FUNC_1 &pcfg_pull_default>,
 524                                                 <1 20 RK_FUNC_1 &pcfg_pull_default>,
 525                                                 <1 21 RK_FUNC_1 &pcfg_pull_default>;
 526                         };
 527                 };
 528
 529                 sdio {
 530                         sdio_bus1: sdio-bus1 {
 531                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
 532                         };
 533
 534                         sdio_bus4: sdio-bus4 {
 535                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
 536                                                 <0 12 RK_FUNC_1 &pcfg_pull_default>,
 537                                                 <0 13 RK_FUNC_1 &pcfg_pull_default>,
 538                                                 <0 14 RK_FUNC_1 &pcfg_pull_default>;
 539                         };
 540
 541                         sdio_cmd: sdio-cmd {
 542                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
 543                         };
 544
 545                         sdio_clk: sdio-clk {
 546                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
 547                         };
 548                 };
 549
 550                 emmc {
 551                         /*
 552                          * We run eMMC at max speed; bump up drive strength.
 553                          * We also have external pulls, so disable the internal ones.
 554                          */
 555                         emmc_clk: emmc-clk {
 556                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 557                         };
 558
 559                         emmc_cmd: emmc-cmd {
 560                                 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
 561                         };
 562
 563                         emmc_bus8: emmc-bus8 {
 564                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
 565                                                 <1 25 RK_FUNC_2 &pcfg_pull_default>,
 566                                                 <1 26 RK_FUNC_2 &pcfg_pull_default>,
 567                                                 <1 27 RK_FUNC_2 &pcfg_pull_default>,
 568                                                 <1 28 RK_FUNC_2 &pcfg_pull_default>,
 569                                                 <1 29 RK_FUNC_2 &pcfg_pull_default>,
 570                                                 <1 30 RK_FUNC_2 &pcfg_pull_default>,
 571                                                 <1 31 RK_FUNC_2 &pcfg_pull_default>;
 572                         };
 573                 };
 574
 575                 i2c0 {
 576                         i2c0_xfer: i2c0-xfer {
 577                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 578                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 579                         };
 580                 };
 581
 582                 i2c1 {
 583                         i2c1_xfer: i2c1-xfer {
 584                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 585                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 586                         };
 587                 };
 588
 589                 i2c2 {
 590                         i2c2_xfer: i2c2-xfer {
 591                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 592                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 593                         };
 594                 };
 595
 596                 i2s {
 597                         i2s_bus: i2s-bus {
 598                                 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
 599                                                 <1 1 RK_FUNC_1 &pcfg_pull_default>,
 600                                                 <1 2 RK_FUNC_1 &pcfg_pull_default>,
 601                                                 <1 3 RK_FUNC_1 &pcfg_pull_default>,
 602                                                 <1 4 RK_FUNC_1 &pcfg_pull_default>,
 603                                                 <1 5 RK_FUNC_1 &pcfg_pull_default>;
 604                         };
 605                 };
 606
 607                 uart0 {
 608                         uart0_xfer: uart0-xfer {
 609                                 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
 610                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>;
 611                         };
 612
 613                         uart0_cts: uart0-cts {
 614                                 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
 615                         };
 616
 617                         uart0_rts: uart0-rts {
 618                                 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
 619                         };
 620                 };
 621
 622                 uart1 {
 623                         uart1_xfer: uart1-xfer {
 624                                 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
 625                                                 <2 23 RK_FUNC_1 &pcfg_pull_none>;
 626                         };
 627                         /* no rts / cts for uart1 */
 628                 };
 629
 630                 uart2 {
 631                         uart2_xfer: uart2-xfer {
 632                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
 633                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 634                         };
 635                         /* no rts / cts for uart2 */
 636                 };
 637
 638                 spi {
 639                         spi_txd:spi-txd {
 640                                 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
 641                         };
 642
 643                         spi_rxd:spi-rxd {
 644                                 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
 645                         };
 646
 647                         spi_clk:spi-clk {
 648                                 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
 649                         };
 650
 651                         spi_cs0:spi-cs0 {
 652                                 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
 653
 654                         };
 655
 656                         spi_cs1:spi-cs1 {
 657                                 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
 658
 659                         };
 660                 };
 661         };
 662 };