2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3036-cru.h>
46 #include "skeleton.dtsi"
49 compatible = "rockchip,rk3036";
51 interrupt-parent = <&gic>;
67 device_type = "memory";
68 reg = <0x60000000 0x40000000>;
74 enable-method = "rockchip,rk3036-smp";
78 compatible = "arm,cortex-a7";
80 resets = <&cru SRST_CORE0>;
85 clock-latency = <40000>;
86 clocks = <&cru ARMCLK>;
91 compatible = "arm,cortex-a7";
93 resets = <&cru SRST_CORE1>;
98 compatible = "arm,amba-bus";
103 pdma: pdma@20078000 {
104 compatible = "arm,pl330", "arm,primecell";
105 reg = <0x20078000 0x4000>;
106 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
109 clocks = <&cru ACLK_DMAC2>;
110 clock-names = "apb_pclk";
115 compatible = "arm,cortex-a7-pmu";
116 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
118 interrupt-affinity = <&cpu0>, <&cpu1>;
122 compatible = "rockchip,display-subsystem";
127 compatible = "arm,armv7-timer";
128 arm,cpu-registers-not-fw-configured;
129 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
130 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
131 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
132 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
133 clock-frequency = <24000000>;
137 compatible = "fixed-clock";
138 clock-frequency = <24000000>;
139 clock-output-names = "xin24m";
143 bus_intmem@10080000 {
144 compatible = "mmio-sram";
145 reg = <0x10080000 0x2000>;
146 #address-cells = <1>;
148 ranges = <0 0x10080000 0x2000>;
151 compatible = "rockchip,rk3066-smp-sram";
157 compatible = "rockchip,rk3036-vop";
158 reg = <0x10118000 0x19c>;
159 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
161 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
162 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
163 reset-names = "axi", "ahb", "dclk";
168 #address-cells = <1>;
170 vop_out_hdmi: endpoint@0 {
172 remote-endpoint = <&hdmi_in_vop>;
177 vop_mmu: iommu@10118300 {
178 compatible = "rockchip,iommu";
179 reg = <0x10118300 0x100>;
180 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
181 interrupt-names = "vop_mmu";
186 gic: interrupt-controller@10139000 {
187 compatible = "arm,gic-400";
188 interrupt-controller;
189 #interrupt-cells = <3>;
190 #address-cells = <0>;
192 reg = <0x10139000 0x1000>,
196 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
199 usb_otg: usb@10180000 {
200 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
202 reg = <0x10180000 0x40000>;
203 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&cru HCLK_OTG0>;
207 g-np-tx-fifo-size = <16>;
208 g-rx-fifo-size = <275>;
209 g-tx-fifo-size = <256 128 128 64 64 32>;
214 usb_host: usb@101c0000 {
215 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
217 reg = <0x101c0000 0x40000>;
218 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&cru HCLK_OTG1>;
225 emac: ethernet@10200000 {
226 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
227 reg = <0x10200000 0x4000>;
228 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
229 #address-cells = <1>;
231 rockchip,grf = <&grf>;
232 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
233 clock-names = "hclk", "macref", "macclk";
235 * Fix the emac parent clock is DPLL instead of APLL.
236 * since that will cause some unstable things if the cpufreq
237 * is working. (e.g: the accurate 50MHz what mac_ref need)
239 assigned-clocks = <&cru SCLK_MACPLL>;
240 assigned-clock-parents = <&cru PLL_DPLL>;
246 sdmmc: dwmmc@10214000 {
247 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
248 reg = <0x10214000 0x4000>;
249 clock-frequency = <37500000>;
250 clock-freq-min-max = <400000 37500000>;
251 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
252 clock-names = "biu", "ciu";
253 fifo-depth = <0x100>;
254 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
258 sdio: dwmmc@10218000 {
259 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
260 reg = <0x10218000 0x4000>;
261 clock-freq-min-max = <400000 37500000>;
262 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
263 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
264 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
265 fifo-depth = <0x100>;
266 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
270 emmc: dwmmc@1021c000 {
271 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
272 reg = <0x1021c000 0x4000>;
273 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
277 clock-frequency = <37500000>;
278 clock-freq-min-max = <400000 37500000>;
279 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
280 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
281 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
282 default-sample-phase = <158>;
286 fifo-depth = <0x100>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
296 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
297 reg = <0x10220000 0x4000>;
298 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
299 #address-cells = <1>;
301 clock-names = "i2s_clk", "i2s_hclk";
302 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
303 dmas = <&pdma 0>, <&pdma 1>;
304 dma-names = "tx", "rx";
305 pinctrl-names = "default";
306 pinctrl-0 = <&i2s_bus>;
310 cru: clock-controller@20000000 {
311 compatible = "rockchip,rk3036-cru";
312 reg = <0x20000000 0x1000>;
313 rockchip,grf = <&grf>;
316 assigned-clocks = <&cru PLL_GPLL>;
317 assigned-clock-rates = <594000000>;
320 grf: syscon@20008000 {
321 compatible = "rockchip,rk3036-grf", "syscon";
322 reg = <0x20008000 0x1000>;
325 acodec: acodec-ana@20030000 {
326 compatible = "rk3036-codec";
327 reg = <0x20030000 0x4000>;
328 rockchip,grf = <&grf>;
329 clock-names = "acodec_pclk";
330 clocks = <&cru PCLK_ACODEC>;
334 hdmi: hdmi@20034000 {
335 compatible = "rockchip,rk3036-inno-hdmi";
336 reg = <0x20034000 0x4000>;
337 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cru PCLK_HDMI>;
339 clock-names = "pclk";
340 rockchip,grf = <&grf>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&hdmi_ctl>;
346 #address-cells = <1>;
348 hdmi_in_vop: endpoint@0 {
350 remote-endpoint = <&vop_out_hdmi>;
355 timer: timer@20044000 {
356 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
357 reg = <0x20044000 0x20>;
358 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&xin24m>, <&cru PCLK_TIMER>;
360 clock-names = "timer", "pclk";
364 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
365 reg = <0x20050000 0x10>;
367 clocks = <&cru PCLK_PWM>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pwm0_pin>;
375 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
376 reg = <0x20050010 0x10>;
378 clocks = <&cru PCLK_PWM>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pwm1_pin>;
386 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
387 reg = <0x20050020 0x10>;
389 clocks = <&cru PCLK_PWM>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pwm2_pin>;
397 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
398 reg = <0x20050030 0x10>;
400 clocks = <&cru PCLK_PWM>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pwm3_pin>;
408 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
409 reg = <0x20056000 0x1000>;
410 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
411 #address-cells = <1>;
414 clocks = <&cru PCLK_I2C1>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&i2c1_xfer>;
421 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
422 reg = <0x2005a000 0x1000>;
423 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
424 #address-cells = <1>;
427 clocks = <&cru PCLK_I2C2>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&i2c2_xfer>;
433 uart0: serial@20060000 {
434 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
435 reg = <0x20060000 0x100>;
436 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
439 clock-frequency = <24000000>;
440 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
441 clock-names = "baudclk", "apb_pclk";
442 pinctrl-names = "default";
443 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
447 uart1: serial@20064000 {
448 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
449 reg = <0x20064000 0x100>;
450 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
453 clock-frequency = <24000000>;
454 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
455 clock-names = "baudclk", "apb_pclk";
456 pinctrl-names = "default";
457 pinctrl-0 = <&uart1_xfer>;
461 uart2: serial@20068000 {
462 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
463 reg = <0x20068000 0x100>;
464 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
467 clock-frequency = <24000000>;
468 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
469 clock-names = "baudclk", "apb_pclk";
470 pinctrl-names = "default";
471 pinctrl-0 = <&uart2_xfer>;
476 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
477 reg = <0x20072000 0x1000>;
478 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
479 #address-cells = <1>;
482 clocks = <&cru PCLK_I2C0>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&i2c0_xfer>;
489 compatible = "rockchip,rockchip-spi";
490 reg = <0x20074000 0x1000>;
491 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
492 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
493 clock-names = "apb-pclk","spi_pclk";
494 dmas = <&pdma 8>, <&pdma 9>;
495 dma-names = "tx", "rx";
496 pinctrl-names = "default";
497 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
498 #address-cells = <1>;
504 compatible = "rockchip,rk3036-pinctrl";
505 rockchip,grf = <&grf>;
506 #address-cells = <1>;
510 gpio0: gpio0@2007c000 {
511 compatible = "rockchip,gpio-bank";
512 reg = <0x2007c000 0x100>;
513 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&cru PCLK_GPIO0>;
519 interrupt-controller;
520 #interrupt-cells = <2>;
523 gpio1: gpio1@20080000 {
524 compatible = "rockchip,gpio-bank";
525 reg = <0x20080000 0x100>;
526 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cru PCLK_GPIO1>;
532 interrupt-controller;
533 #interrupt-cells = <2>;
536 gpio2: gpio2@20084000 {
537 compatible = "rockchip,gpio-bank";
538 reg = <0x20084000 0x100>;
539 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&cru PCLK_GPIO2>;
545 interrupt-controller;
546 #interrupt-cells = <2>;
549 pcfg_pull_default: pcfg_pull_default {
550 bias-pull-pin-default;
553 pcfg_pull_none: pcfg-pull-none {
559 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
565 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
571 rockchip,pins = <0 1 2 &pcfg_pull_none>;
577 rockchip,pins = <0 27 1 &pcfg_pull_none>;
582 sdmmc_clk: sdmmc-clk {
583 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
586 sdmmc_cmd: sdmmc-cmd {
587 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
591 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
594 sdmmc_bus1: sdmmc-bus1 {
595 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
598 sdmmc_bus4: sdmmc-bus4 {
599 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
600 <1 19 RK_FUNC_1 &pcfg_pull_default>,
601 <1 20 RK_FUNC_1 &pcfg_pull_default>,
602 <1 21 RK_FUNC_1 &pcfg_pull_default>;
607 sdio_bus1: sdio-bus1 {
608 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
611 sdio_bus4: sdio-bus4 {
612 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
613 <0 12 RK_FUNC_1 &pcfg_pull_default>,
614 <0 13 RK_FUNC_1 &pcfg_pull_default>,
615 <0 14 RK_FUNC_1 &pcfg_pull_default>;
619 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
623 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
629 * We run eMMC at max speed; bump up drive strength.
630 * We also have external pulls, so disable the internal ones.
633 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
637 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
640 emmc_bus8: emmc-bus8 {
641 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
642 <1 25 RK_FUNC_2 &pcfg_pull_default>,
643 <1 26 RK_FUNC_2 &pcfg_pull_default>,
644 <1 27 RK_FUNC_2 &pcfg_pull_default>,
645 <1 28 RK_FUNC_2 &pcfg_pull_default>,
646 <1 29 RK_FUNC_2 &pcfg_pull_default>,
647 <1 30 RK_FUNC_2 &pcfg_pull_default>,
648 <1 31 RK_FUNC_2 &pcfg_pull_default>;
653 emac_xfer: emac-xfer {
654 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
655 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
656 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
657 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
658 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
659 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
660 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
661 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
664 emac_mdio: emac-mdio {
665 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
666 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
671 i2c0_xfer: i2c0-xfer {
672 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
673 <0 1 RK_FUNC_1 &pcfg_pull_none>;
678 i2c1_xfer: i2c1-xfer {
679 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
680 <0 3 RK_FUNC_1 &pcfg_pull_none>;
685 i2c2_xfer: i2c2-xfer {
686 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
687 <2 21 RK_FUNC_1 &pcfg_pull_none>;
693 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
694 <1 1 RK_FUNC_1 &pcfg_pull_default>,
695 <1 2 RK_FUNC_1 &pcfg_pull_default>,
696 <1 3 RK_FUNC_1 &pcfg_pull_default>,
697 <1 4 RK_FUNC_1 &pcfg_pull_default>,
698 <1 5 RK_FUNC_1 &pcfg_pull_default>;
704 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
705 <1 9 RK_FUNC_1 &pcfg_pull_none>,
706 <1 10 RK_FUNC_1 &pcfg_pull_none>,
707 <1 11 RK_FUNC_1 &pcfg_pull_none>;
712 uart0_xfer: uart0-xfer {
713 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
714 <0 17 RK_FUNC_1 &pcfg_pull_none>;
717 uart0_cts: uart0-cts {
718 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
721 uart0_rts: uart0-rts {
722 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
727 uart1_xfer: uart1-xfer {
728 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
729 <2 23 RK_FUNC_1 &pcfg_pull_none>;
731 /* no rts / cts for uart1 */
735 uart2_xfer: uart2-xfer {
736 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
737 <1 19 RK_FUNC_2 &pcfg_pull_none>;
739 /* no rts / cts for uart2 */
744 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
748 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
752 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
756 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
761 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;