1 #include <dt-bindings/interrupt-controller/arm-gic.h>
3 #include "skeleton.dtsi"
4 #include "rk3036-clocks.dtsi"
5 #include "rk3036-pinctrl.dtsi"
6 #include <dt-bindings/suspend/rockchip-pm.h>
9 compatible = "rockchip,rk3036";
10 rockchip,sram = <&sram>;
11 interrupt-parent = <&gic>;
30 compatible = "arm,cortex-a7";
35 compatible = "arm,cortex-a7";
40 gic: interrupt-controller@10139000 {
41 compatible = "arm,cortex-a15-gic";
43 #interrupt-cells = <3>;
45 reg = <0x10139000 0x1000>,
50 compatible = "arm,cortex-a7-pmu";
51 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
55 cpu_axi_bus: cpu_axi_bus {
56 compatible = "rockchip,cpu_axi_bus";
67 reg = <0x1012a000 0x20>;
68 rockchip,priority = <3 2>;
71 reg = <0x1012c000 0x20>;
74 reg = <0x1012d000 0x20>;
77 reg = <0x1012e000 0x20>;
80 reg = <0x1012e080 0x20>;
83 reg = <0x1012f000 0x20>;
84 rockchip,priority = <3 3>;
94 reg = <0x10128000 0x40>;
95 rockchip,read-latency = <0x80>;
100 sram: sram@10080000 {
101 compatible = "mmio-sram";
102 reg = <0x10080000 0x2000>;
107 compatible = "arm,armv7-timer";
108 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
109 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
110 clock-frequency = <24000000>;
114 compatible = "rockchip,timer";
115 reg = <0x20044000 0x20>;
116 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
117 rockchip,broadcast = <1>;
120 watchdog: wdt@2004c000 {
121 compatible = "rockchip,watch dog";
122 reg = <0x2004c000 0x100>;
123 clocks = <&clk_gates7 15>;
124 clock-names = "pclk_wdt";
125 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
127 rockchip,timeout = <60>;
128 rockchip,atboot = <1>;
129 rockchip,debug = <0>;
134 #address-cells = <1>;
136 compatible = "arm,amba-bus";
137 interrupt-parent = <&gic>;
140 pdma: pdma@20078000 {
141 compatible = "arm,pl330", "arm,primecell";
142 reg = <0x20078000 0x4000>;
143 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
149 reset: reset@20000110{
150 compatible = "rockchip,reset";
151 reg = <0x20000110 0x24>;
152 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
156 nandc: nandc@10500000 {
157 compatible = "rockchip,rk-nandc";
158 reg = <0x10500000 0x4000>;
159 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
160 //pinctrl-names = "default";
161 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
163 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 4>;
164 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
167 nandc0reg: nandc0@10500000 {
168 compatible = "rockchip,rk-nandc";
169 reg = <0x10500000 0x4000>;
173 compatible = "rockchip,rockchip-spi";
174 reg = <0x20074000 0x1000>;
175 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
176 #address-cells = <1>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
180 rockchip,spi-src-clk = <0>;
182 clocks =<&clk_spi0>, <&clk_gates2 9>;
183 clock-names = "spi","pclk_spi0";
184 dmas = <&pdma 8>, <&pdma 9>;
186 dma-names = "tx", "rx";
190 uart0: serial@20060000 {
191 compatible = "rockchip,serial";
192 reg = <0x20060000 0x100>;
193 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
194 clock-frequency = <24000000>;
195 clocks = <&clk_uart0>, <&clk_gates8 0>;
196 clock-names = "sclk_uart", "pclk_uart";
199 dmas = <&pdma 2>, <&pdma 3>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
206 uart1: serial@20064000 {
207 compatible = "rockchip,serial";
208 reg = <0x20064000 0x100>;
209 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
210 clock-frequency = <24000000>;
211 clocks = <&clk_uart1>, <&clk_gates8 1>;
212 clock-names = "sclk_uart", "pclk_uart";
215 dmas = <&pdma 4>, <&pdma 5>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&uart1_xfer>;
222 uart2: serial@20068000 {
223 compatible = "rockchip,serial";
224 reg = <0x20068000 0x100>;
225 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
226 clock-frequency = <24000000>;
227 clocks = <&clk_uart2>, <&clk_gates8 2>;
228 clock-names = "sclk_uart", "pclk_uart";
231 dmas = <&pdma 6>, <&pdma 7>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&uart2_xfer>;
239 compatible = "rockchip,fiq-debugger";
240 rockchip,serial-id = <2>;
241 rockchip,signal-irq = <106>;
242 rockchip,wake-irq = <0>;
247 compatible = "rockchip,clocks-init";
248 rockchip,clocks-init-parent =
249 <&clk_core &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
250 <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
251 <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
252 <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
253 <&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>;
254 rockchip,clocks-init-rate =
255 <&clk_core 1200000000>, <&clk_gpll 1188000000>,
256 <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
257 <&pclk_cpu_pre 75000000>, <&aclk_peri_pre 150000000>,
258 <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
259 <&clk_gpu 400000000>, <&aclk_vio_pre 300000000>,
260 <&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
261 <&clk_hevc_core 200000000>, <&clk_mac_pll_div 50000000>,
262 <&clk_mac_ref_div 25000000>;
263 /* rockchip,clocks-uboot-has-init =
268 compatible = "rockchip,clocks-enable";
271 <&clk_gates0 0>, <&clk_gates0 7>,
274 <&clk_gates0 3>, <&clk_gates0 4>,
278 <&clk_gates1 0>, <&clk_gates1 1>,
279 <&clk_gates2 4>, <&clk_gates2 5>,
282 <&clk_gates2 0>, <&hclk_peri_pre>,
283 <&pclk_peri_pre>, <&clk_gates2 1>,
286 <&clk_gates4 12>,/*aclk_intmem*/
287 <&clk_gates4 10>,/*aclk_strc_sys*/
290 <&clk_gates5 6>,/*hclk_rom*/
293 <&clk_gates5 4>,/*pclk_grf*/
294 <&clk_gates5 7>,/*pclk_ddrupctl*/
295 <&clk_gates5 14>,/*pclk_acodec*/
296 <&clk_gates3 8>,/*pclk_hdmi*/
299 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
300 <&clk_gates5 1>,/*aclk_dmac2*/
301 <&clk_gates9 15>,/*aclk_peri_niu*/
302 <&clk_gates4 2>,/*aclk_cpu_peri*/
305 <&clk_gates4 0>,/*hclk_peri_matrix*/
306 <&clk_gates9 13>,/*hclk_usb_peri*/
307 <&clk_gates9 14>,/*hclk_peri_arbi*/
310 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
313 <&clk_gates6 12>,/*hclk_vio_bus*/
314 <&clk_gates9 5>,/*hclk_lcdc*/
317 <&clk_gates6 13>,/*aclk_vio*/
318 <&clk_gates9 6>,/*aclk_lcdc*/
323 <&clk_gates8 2>,/*pclk_uart2*/
328 <&clk_gates1 3>;/*clk_jtag*/
332 compatible = "rockchip,rk30-i2c";
333 reg = <0x20072000 0x1000>;
334 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
335 #address-cells = <1>;
337 pinctrl-names = "default", "gpio";
338 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
339 pinctrl-1 = <&i2c0_gpio>;
340 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
341 clocks = <&clk_gates8 4>;
342 rockchip,check-idle = <1>;
347 compatible = "rockchip,rk30-i2c";
348 reg = <0x20056000 0x1000>;
349 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
350 #address-cells = <1>;
352 pinctrl-names = "default", "gpio";
353 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
354 pinctrl-1 = <&i2c1_gpio>;
355 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
356 clocks = <&clk_gates8 5>;
357 rockchip,check-idle = <1>;
362 compatible = "rockchip,rk30-i2c";
363 reg = <0x2005a000 0x1000>;
364 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
365 #address-cells = <1>;
367 pinctrl-names = "default", "gpio";
368 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
369 pinctrl-1 = <&i2c2_gpio>;
370 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
371 clocks = <&clk_gates8 6>;
372 rockchip,check-idle = <1>;
377 compatible = "rockchip-i2s";
378 reg = <0x10220000 0x1000>;
380 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
381 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
382 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
383 dmas = <&pdma 0>, <&pdma 1>;
385 dma-names = "tx", "rx";
386 //pinctrl-names = "default", "sleep";
387 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
388 //pinctrl-1 = <&i2s_gpio>;
391 codec: codec@20030000 {
392 compatible = "rk3036-codec";
393 reg = <0x20030000 0x1000>;
394 spk_ctl_io = <&gpio1 GPIO_A0 0>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&i2s0_gpio>;
399 pa_enable_time = <1000>;
400 clocks = <&clk_gates5 14>;
401 clock-names = "g_pclk_acodec";
404 spdif: spdif@10204000 {
405 compatible = "rockchip-spdif";
406 reg = <0x10204000 0x1000>;
407 clocks = <&clk_spdif>;
408 clock-names = "spdif_mclk";
409 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&spdif_tx>;
418 compatible = "rockchip,rk-pwm";
419 reg = <0x20050000 0x10>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&pwm0_pin>;
423 clocks = <&clk_gates7 10>;
424 clock-names = "pclk_pwm";
429 compatible = "rockchip,rk-pwm";
430 reg = <0x20050010 0x10>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&pwm1_pin>;
434 clocks = <&clk_gates7 10>;
435 clock-names = "pclk_pwm";
440 compatible = "rockchip,rk-pwm";
441 reg = <0x20050020 0x10>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&pwm2_pin>;
445 clocks = <&clk_gates7 10>;
446 clock-names = "pclk_pwm";
451 compatible = "rockchip,rk-pwm";
452 reg = <0x20050030 0x10>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&pwm3_pin>;
456 clocks = <&clk_gates7 10>;
457 clock-names = "pclk_pwm";
461 remotectl: pwm@20050030 {
462 compatible = "rockchip,remotectl-pwm";
463 reg = <0x20050030 0x10>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pwm3_pin>;
467 clocks = <&clk_gates7 10>;
468 clock-names = "pclk_pwm";
470 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
474 emmc: rksdmmc@1021c000 {
475 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
476 reg = <0x1021c000 0x4000>;
477 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
478 #address-cells = <1>;
480 //pinctrl-names = "default",,"suspend";
481 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
482 clocks = <&clk_emmc>, <&clk_gates7 0>;
483 clock-names = "clk_mmc", "hclk_mmc";
485 dma-names = "dw_mci";
487 fifo-depth = <0x100>;
492 sdmmc: rksdmmc@10214000 {
493 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
494 reg = <0x10214000 0x4000>;
495 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
496 #address-cells = <1>;
498 pinctrl-names = "default", "idle", "udbg";
499 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
500 pinctrl-1 = <&sdmmc0_gpio>;
501 pinctrl-2 = <&uart2_xfer>;
502 cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
503 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
504 clock-names = "clk_mmc", "hclk_mmc";
506 dma-names = "dw_mci";
508 fifo-depth = <0x100>;
512 sdio: rksdmmc@10218000 {
513 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
514 reg = <0x10218000 0x4000>;
515 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
516 #address-cells = <1>;
518 pinctrl-names = "default","idle";
519 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
520 pinctrl-1 = <&sdio0_gpio>;
521 clocks = <&clk_sdio>, <&clk_gates5 11>;
522 clock-names = "clk_mmc", "hclk_mmc";
524 dma-names = "dw_mci";
526 fifo-depth = <0x100>;
530 compatible = "arm,mali400";
531 reg = <0x10091000 0x200>,
536 reg-names = "Mali_L2",
542 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
546 interrupt-names = "Mali_GP_IRQ",
551 dwc_control_usb: dwc-control-usb@20008000 {
552 compatible = "rockchip,rk3036-dwc-control-usb";
553 reg = <0x20008000 0x4>;
554 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
555 interrupt-names = "otg_bvalid";
556 clocks = <&clk_gates9 13>;
557 clock-names = "hclk_usb_peri";
558 rockchip,remote_wakeup;
559 rockchip,usb_irq_wakeup;
560 resets = <&reset RK3036_RST_USBPOR>;
561 reset-names = "usbphy_por";
563 compatible = "rockchip,ctrl";
564 rk_usb,bvalid = <0x14c 8 1>;
565 rk_usb,iddig = <0x14c 11 1>;
566 rk_usb,line = <0x14c 9 2>;
567 rk_usb,softctrl = <0x17c 0 1>;
568 rk_usb,opmode = <0x17c 2 2>;
569 rk_usb,xcvrsel = <0x17c 4 2>;
570 rk_usb,termsel = <0x17c 6 1>;
574 compatible = "rockchip,rk3036_usb20_otg";
575 reg = <0x10180000 0x40000>;
576 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
578 clock-names = "clk_usbphy0", "hclk_usb0";
579 resets = <&reset RK3036_RST_USBOTG0>, <&reset RK3036_RST_UTMI0>,
580 <&reset RK3036_RST_OTGC0>;
581 reset-names = "otg_ahb", "otg_phy", "otg_controller";
582 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
583 rockchip,usb-mode = <0>;
587 compatible = "rockchip,rk3036_usb20_host";
588 reg = <0x101c0000 0x40000>;
589 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
591 clock-names = "clk_usbphy1", "hclk_usb1";
592 resets = <&reset RK3036_RST_USBOTG1>, <&reset RK3036_RST_UTMI1>,
593 <&reset RK3036_RST_OTGC1>;
594 reset-names = "host_ahb", "host_phy", "host_controller";
598 compatible = "rockchip,rk-fb";
599 rockchip,disp-mode = <NO_DUAL>;
600 rockchip,disp-policy = <DISPLAY_POLICY_BOX>;
603 rk_screen: rk_screen{
604 compatible = "rockchip,screen";
607 lcdc: lcdc@10118000 {
608 compatible = "rockchip,rk3036-lcdc";
609 reg = <0x10118000 0x1000>;
610 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
613 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
614 rockchip,iommu-enabled = <1>;
617 hdmi: hdmi@20034000 {
618 compatible = "rockchip,rk3036-hdmi";
619 reg = <0x20034000 0x4000>;
620 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
621 rockchip,hdmi_lcdc_source = <0>;
622 pinctrl-names = "default", "gpio";
623 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
624 pinctrl-1 = <&hdmi_gpio>;
625 clocks = <&clk_gates3 8>;
626 clock-names = "pclk_hdmi";
631 compatible = "rockchip,rk3036-tve";
632 reg = <0x10118200 0x100>;
637 compatible = "rockchip,ion";
638 #address-cells = <1>;
641 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
642 compatible = "rockchip,ion-heap";
643 rockchip,ion_heap = <1>;
644 reg = <0x00000000 0x00000000>; /* 0MB */
646 rockchip,ion-heap@3 { /* VMALLOC HEAP */
647 compatible = "rockchip,ion-heap";
648 rockchip,ion_heap = <3>;
652 vpu: vpu_service@10108000 {
653 compatible = "vpu_service";
655 reg = <0x10108000 0x800>;
656 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
657 interrupt-names = "irq_dec";
658 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>;
659 clock-names = "aclk_vcodec", "hclk_vcodec";
660 name = "vpu_service";
664 hevc: hevc_service@1010c000 {
665 compatible = "rockchip,hevc_service";
667 reg = <0x1010c000 0x400>;
668 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
669 interrupt-names = "irq_dec";
670 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
671 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
672 name = "hevc_service";
678 compatible = "rockchip,vop_mmu";
679 reg = <0x10118300 0x100>;
680 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
681 interrupt-names = "vop_mmu";
686 compatible = "rockchip,hevc_mmu";
687 reg = <0x1010c440 0x40>,
689 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
690 interrupt-names = "hevc_mmu";
695 compatible = "rockchip,vpu_mmu";
696 reg = <0x10108800 0x100>;
697 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
698 interrupt-names = "vpu_mmu";
707 |RKPM_CTR_IDLESRAM_MD
713 //|RKPM_CTR_SYSCLK_DIV
714 //|RKPM_CTR_IDLEAUTO_MD
715 //|RKPM_CTR_ARMOFF_LPMD
716 //|RKPM_CTR_ARMOFF_LOGDP_LPMD
720 rockchip,pmic-suspend_gpios = <
721 RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
723 rockchip,pmic-resume_gpios = <
724 RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
730 compatible = "rockchip,vmac";
731 reg = <0x10200000 0x4000>;
732 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
733 interrupt-names = "macirq";
734 clocks = <&clk_mac_pll>, <&clk_mac_ref>,
735 <&clk_mac_pll_div>, <&clk_mac_ref_div>,
736 <&clk_gates2 6>, <&clk_gates3 5>;
737 clock-names = "clk_mac_pll", "clk_mac_ref",
738 "clk_mac_pll_div", "clk_mac_ref_div",
739 "clk_tx_rx_gate", "hclk_mac";
740 pinctrl-names = "default";
741 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_crs &mac_mdpins>;