2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3036-cru.h>
46 #include <dt-bindings/soc/rockchip_boot-mode.h>
47 #include "skeleton.dtsi"
50 compatible = "rockchip,rk3036";
52 interrupt-parent = <&gic>;
70 enable-method = "rockchip,rk3036-smp";
74 compatible = "arm,cortex-a7";
76 resets = <&cru SRST_CORE0>;
81 clock-latency = <40000>;
82 clocks = <&cru ARMCLK>;
87 compatible = "arm,cortex-a7";
89 resets = <&cru SRST_CORE1>;
94 compatible = "arm,amba-bus";
100 compatible = "arm,pl330", "arm,primecell";
101 reg = <0x20078000 0x4000>;
102 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
105 arm,pl330-broken-no-flushp;
106 peripherals-req-type-burst;
107 clocks = <&cru ACLK_DMAC2>;
108 clock-names = "apb_pclk";
113 compatible = "arm,cortex-a7-pmu";
114 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
116 interrupt-affinity = <&cpu0>, <&cpu1>;
120 compatible = "rockchip,display-subsystem";
125 compatible = "arm,armv7-timer";
126 arm,cpu-registers-not-fw-configured;
127 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
128 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
129 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
130 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
131 clock-frequency = <24000000>;
135 compatible = "fixed-clock";
136 clock-frequency = <24000000>;
137 clock-output-names = "xin24m";
141 bus_intmem@10080000 {
142 compatible = "mmio-sram";
143 reg = <0x10080000 0x2000>;
144 #address-cells = <1>;
146 ranges = <0 0x10080000 0x2000>;
149 compatible = "rockchip,rk3066-smp-sram";
155 compatible = "arm,mali400";
157 reg = <0x10091000 0x200>,
163 reg-names = "Mali_L2",
169 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
173 interrupt-names = "Mali_GP_IRQ",
178 clocks = <&cru SCLK_GPU>;
179 clock-names = "clk_mali";
184 vpu: video-codec@10108000 {
185 compatible = "rockchip,rk3036-vpu", "rockchip,rk3288-vpu";
186 reg = <0x10108000 0x800>;
187 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
189 interrupt-names = "vepu", "vdpu";
190 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
191 clock-names = "aclk", "hclk";
194 * 3036's vpu could not run higher than 300M
196 assigned-clocks = <&cru ACLK_VCODEC>;
197 assigned-clock-rates = <297000000>;
198 assigned-clock-parents = <&cru PLL_GPLL>;
202 vpu_mmu: iommu@10108800 {
203 compatible = "rockchip,iommu";
204 reg = <0x10108800 0x100>;
205 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
206 interrupt-names = "vpu_mmu";
211 compatible = "rockchip,rk3036-vop";
212 reg = <0x10118000 0x19c>;
213 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
215 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
216 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
217 reset-names = "axi", "ahb", "dclk";
222 #address-cells = <1>;
224 vop_out_hdmi: endpoint@0 {
226 remote-endpoint = <&hdmi_in_vop>;
231 vop_mmu: iommu@10118300 {
232 compatible = "rockchip,iommu";
233 reg = <0x10118300 0x100>;
234 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
235 interrupt-names = "vop_mmu";
240 gic: interrupt-controller@10139000 {
241 compatible = "arm,gic-400";
242 interrupt-controller;
243 #interrupt-cells = <3>;
244 #address-cells = <0>;
246 reg = <0x10139000 0x1000>,
250 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
253 usb_otg: usb@10180000 {
254 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
256 reg = <0x10180000 0x40000>;
257 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cru HCLK_OTG0>;
261 g-np-tx-fifo-size = <16>;
262 g-rx-fifo-size = <275>;
263 g-tx-fifo-size = <256 128 128 64 64 32>;
268 usb_host: usb@101c0000 {
269 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
271 reg = <0x101c0000 0x40000>;
272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&cru HCLK_OTG1>;
279 emac: ethernet@10200000 {
280 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
281 reg = <0x10200000 0x4000>;
282 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
283 #address-cells = <1>;
285 rockchip,grf = <&grf>;
286 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
287 clock-names = "hclk", "macref", "macclk";
289 * Fix the emac parent clock is DPLL instead of APLL.
290 * since that will cause some unstable things if the cpufreq
291 * is working. (e.g: the accurate 50MHz what mac_ref need)
293 assigned-clocks = <&cru SCLK_MACPLL>;
294 assigned-clock-parents = <&cru PLL_DPLL>;
300 sdmmc: dwmmc@10214000 {
301 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
302 reg = <0x10214000 0x4000>;
303 clock-frequency = <37500000>;
304 clock-freq-min-max = <400000 37500000>;
305 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
306 clock-names = "biu", "ciu";
307 fifo-depth = <0x100>;
308 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
312 sdio: dwmmc@10218000 {
313 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
314 reg = <0x10218000 0x4000>;
315 clock-freq-min-max = <400000 37500000>;
316 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
317 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
318 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
319 fifo-depth = <0x100>;
320 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
324 emmc: dwmmc@1021c000 {
325 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
326 reg = <0x1021c000 0x4000>;
327 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
330 clock-frequency = <37500000>;
331 clock-freq-min-max = <400000 37500000>;
332 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
333 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
334 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
335 default-sample-phase = <158>;
339 fifo-depth = <0x100>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
350 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
351 reg = <0x10220000 0x4000>;
352 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
355 clock-names = "i2s_clk", "i2s_hclk";
356 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
357 dmas = <&pdma 0>, <&pdma 1>;
358 dma-names = "tx", "rx";
359 pinctrl-names = "default";
360 pinctrl-0 = <&i2s_bus>;
364 cru: clock-controller@20000000 {
365 compatible = "rockchip,rk3036-cru";
366 reg = <0x20000000 0x1000>;
367 rockchip,grf = <&grf>;
370 assigned-clocks = <&cru PLL_GPLL>;
371 assigned-clock-rates = <594000000>;
374 grf: syscon@20008000 {
375 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
376 reg = <0x20008000 0x1000>;
378 compatible = "syscon-reboot-mode";
380 mode-normal = <BOOT_NORMAL>;
381 mode-recovery = <BOOT_RECOVERY>;
382 mode-bootloader = <BOOT_FASTBOOT>;
383 mode-loader = <BOOT_LOADER>;
384 mode-ums = <BOOT_UMS>;
388 acodec: acodec-ana@20030000 {
389 compatible = "rk3036-codec";
390 reg = <0x20030000 0x4000>;
391 rockchip,grf = <&grf>;
392 clock-names = "acodec_pclk";
393 clocks = <&cru PCLK_ACODEC>;
397 hdmi: hdmi@20034000 {
398 compatible = "rockchip,rk3036-inno-hdmi";
399 reg = <0x20034000 0x4000>;
400 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&cru PCLK_HDMI>;
402 clock-names = "pclk";
403 rockchip,grf = <&grf>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&hdmi_ctl>;
406 #address-cells = <1>;
408 #sound-dai-cells = <0>;
412 #address-cells = <1>;
414 hdmi_in_vop: endpoint@0 {
416 remote-endpoint = <&vop_out_hdmi>;
421 hdmi_sound: hdmi-sound {
422 compatible = "simple-audio-card";
423 simple-audio-card,name = "rockchip,hdmi";
424 simple-audio-card,widgets = "Headphone", "Out Jack",
428 simple-audio-card,dai-link {
440 timer: timer@20044000 {
441 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
442 reg = <0x20044000 0x20>;
443 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&xin24m>, <&cru PCLK_TIMER>;
445 clock-names = "timer", "pclk";
449 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
450 reg = <0x20050000 0x10>;
452 clocks = <&cru PCLK_PWM>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&pwm0_pin>;
460 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
461 reg = <0x20050010 0x10>;
463 clocks = <&cru PCLK_PWM>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pwm1_pin>;
471 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
472 reg = <0x20050020 0x10>;
474 clocks = <&cru PCLK_PWM>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&pwm2_pin>;
482 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
483 reg = <0x20050030 0x10>;
485 clocks = <&cru PCLK_PWM>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&pwm3_pin>;
493 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
494 reg = <0x20056000 0x1000>;
495 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
496 #address-cells = <1>;
499 clocks = <&cru PCLK_I2C1>;
500 pinctrl-names = "default";
501 pinctrl-0 = <&i2c1_xfer>;
506 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
507 reg = <0x2005a000 0x1000>;
508 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
509 #address-cells = <1>;
512 clocks = <&cru PCLK_I2C2>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&i2c2_xfer>;
518 uart0: serial@20060000 {
519 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
520 reg = <0x20060000 0x100>;
521 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
524 clock-frequency = <24000000>;
525 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
526 clock-names = "baudclk", "apb_pclk";
527 pinctrl-names = "default";
528 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
532 uart1: serial@20064000 {
533 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
534 reg = <0x20064000 0x100>;
535 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
538 clock-frequency = <24000000>;
539 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
540 clock-names = "baudclk", "apb_pclk";
541 pinctrl-names = "default";
542 pinctrl-0 = <&uart1_xfer>;
546 uart2: serial@20068000 {
547 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
548 reg = <0x20068000 0x100>;
549 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
552 clock-frequency = <24000000>;
553 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
554 clock-names = "baudclk", "apb_pclk";
555 pinctrl-names = "default";
556 pinctrl-0 = <&uart2_xfer>;
561 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
562 reg = <0x20072000 0x1000>;
563 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
564 #address-cells = <1>;
567 clocks = <&cru PCLK_I2C0>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&i2c0_xfer>;
574 compatible = "rockchip,rockchip-spi";
575 reg = <0x20074000 0x1000>;
576 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
577 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
578 clock-names = "apb-pclk","spi_pclk";
579 dmas = <&pdma 8>, <&pdma 9>;
580 dma-names = "tx", "rx";
581 pinctrl-names = "default";
582 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
583 #address-cells = <1>;
589 compatible = "rockchip,rk3036-pinctrl";
590 rockchip,grf = <&grf>;
591 #address-cells = <1>;
595 gpio0: gpio0@2007c000 {
596 compatible = "rockchip,gpio-bank";
597 reg = <0x2007c000 0x100>;
598 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&cru PCLK_GPIO0>;
604 interrupt-controller;
605 #interrupt-cells = <2>;
608 gpio1: gpio1@20080000 {
609 compatible = "rockchip,gpio-bank";
610 reg = <0x20080000 0x100>;
611 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&cru PCLK_GPIO1>;
617 interrupt-controller;
618 #interrupt-cells = <2>;
621 gpio2: gpio2@20084000 {
622 compatible = "rockchip,gpio-bank";
623 reg = <0x20084000 0x100>;
624 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&cru PCLK_GPIO2>;
630 interrupt-controller;
631 #interrupt-cells = <2>;
634 pcfg_pull_default: pcfg_pull_default {
635 bias-pull-pin-default;
638 pcfg_pull_none: pcfg-pull-none {
644 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
650 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
656 rockchip,pins = <0 1 2 &pcfg_pull_none>;
662 rockchip,pins = <0 27 1 &pcfg_pull_none>;
667 sdmmc_clk: sdmmc-clk {
668 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
671 sdmmc_cmd: sdmmc-cmd {
672 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
676 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
679 sdmmc_bus1: sdmmc-bus1 {
680 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
683 sdmmc_bus4: sdmmc-bus4 {
684 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
685 <1 19 RK_FUNC_1 &pcfg_pull_default>,
686 <1 20 RK_FUNC_1 &pcfg_pull_default>,
687 <1 21 RK_FUNC_1 &pcfg_pull_default>;
692 sdio_bus1: sdio-bus1 {
693 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
696 sdio_bus4: sdio-bus4 {
697 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
698 <0 12 RK_FUNC_1 &pcfg_pull_default>,
699 <0 13 RK_FUNC_1 &pcfg_pull_default>,
700 <0 14 RK_FUNC_1 &pcfg_pull_default>;
704 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
708 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
714 * We run eMMC at max speed; bump up drive strength.
715 * We also have external pulls, so disable the internal ones.
718 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
722 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
725 emmc_bus8: emmc-bus8 {
726 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
727 <1 25 RK_FUNC_2 &pcfg_pull_default>,
728 <1 26 RK_FUNC_2 &pcfg_pull_default>,
729 <1 27 RK_FUNC_2 &pcfg_pull_default>,
730 <1 28 RK_FUNC_2 &pcfg_pull_default>,
731 <1 29 RK_FUNC_2 &pcfg_pull_default>,
732 <1 30 RK_FUNC_2 &pcfg_pull_default>,
733 <1 31 RK_FUNC_2 &pcfg_pull_default>;
738 emac_xfer: emac-xfer {
739 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
740 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
741 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
742 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
743 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
744 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
745 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
746 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
749 emac_mdio: emac-mdio {
750 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
751 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
756 i2c0_xfer: i2c0-xfer {
757 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
758 <0 1 RK_FUNC_1 &pcfg_pull_none>;
763 i2c1_xfer: i2c1-xfer {
764 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
765 <0 3 RK_FUNC_1 &pcfg_pull_none>;
770 i2c2_xfer: i2c2-xfer {
771 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
772 <2 21 RK_FUNC_1 &pcfg_pull_none>;
778 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
779 <1 1 RK_FUNC_1 &pcfg_pull_default>,
780 <1 2 RK_FUNC_1 &pcfg_pull_default>,
781 <1 3 RK_FUNC_1 &pcfg_pull_default>,
782 <1 4 RK_FUNC_1 &pcfg_pull_default>,
783 <1 5 RK_FUNC_1 &pcfg_pull_default>;
789 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
790 <1 9 RK_FUNC_1 &pcfg_pull_none>,
791 <1 10 RK_FUNC_1 &pcfg_pull_none>,
792 <1 11 RK_FUNC_1 &pcfg_pull_none>;
797 uart0_xfer: uart0-xfer {
798 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
799 <0 17 RK_FUNC_1 &pcfg_pull_none>;
802 uart0_cts: uart0-cts {
803 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
806 uart0_rts: uart0-rts {
807 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
812 uart1_xfer: uart1-xfer {
813 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
814 <2 23 RK_FUNC_1 &pcfg_pull_none>;
816 /* no rts / cts for uart1 */
820 uart2_xfer: uart2-xfer {
821 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
822 <1 19 RK_FUNC_2 &pcfg_pull_none>;
824 /* no rts / cts for uart2 */
829 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
833 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
837 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
841 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
846 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;