2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/rockchip.h>
18 #include <dt-bindings/clock/rk3066a-cru.h>
19 #include "rk3xxx.dtsi"
22 compatible = "rockchip,rk3066a";
27 enable-method = "rockchip,rk3066-smp";
31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
44 compatible = "mmio-sram";
45 reg = <0x10080000 0x10000>;
48 ranges = <0 0x10080000 0x10000>;
51 compatible = "rockchip,rk3066-smp-sram";
56 cru: clock-controller@20000000 {
57 compatible = "rockchip,rk3066a-cru";
58 reg = <0x20000000 0x1000>;
59 rockchip,grf = <&grf>;
66 compatible = "snps,dw-apb-timer-osc";
67 reg = <0x2000e000 0x100>;
68 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
69 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
70 clock-names = "timer", "pclk";
74 compatible = "snps,dw-apb-timer-osc";
75 reg = <0x20038000 0x100>;
76 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
78 clock-names = "timer", "pclk";
82 compatible = "snps,dw-apb-timer-osc";
83 reg = <0x2003a000 0x100>;
84 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
86 clock-names = "timer", "pclk";
90 compatible = "rockchip,rk3066a-pinctrl";
91 rockchip,grf = <&grf>;
96 gpio0: gpio0@20034000 {
97 compatible = "rockchip,gpio-bank";
98 reg = <0x20034000 0x100>;
99 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&cru PCLK_GPIO0>;
105 interrupt-controller;
106 #interrupt-cells = <2>;
109 gpio1: gpio1@2003c000 {
110 compatible = "rockchip,gpio-bank";
111 reg = <0x2003c000 0x100>;
112 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&cru PCLK_GPIO1>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
122 gpio2: gpio2@2003e000 {
123 compatible = "rockchip,gpio-bank";
124 reg = <0x2003e000 0x100>;
125 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&cru PCLK_GPIO2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
135 gpio3: gpio3@20080000 {
136 compatible = "rockchip,gpio-bank";
137 reg = <0x20080000 0x100>;
138 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&cru PCLK_GPIO3>;
144 interrupt-controller;
145 #interrupt-cells = <2>;
148 gpio4: gpio4@20084000 {
149 compatible = "rockchip,gpio-bank";
150 reg = <0x20084000 0x100>;
151 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&cru PCLK_GPIO4>;
157 interrupt-controller;
158 #interrupt-cells = <2>;
161 gpio6: gpio6@2000a000 {
162 compatible = "rockchip,gpio-bank";
163 reg = <0x2000a000 0x100>;
164 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&cru PCLK_GPIO6>;
170 interrupt-controller;
171 #interrupt-cells = <2>;
174 pcfg_pull_default: pcfg_pull_default {
175 bias-pull-pin-default;
178 pcfg_pull_none: pcfg_pull_none {
184 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
188 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
192 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
196 * The data pins are shared between nandc and emmc and
197 * not accessible through pinctrl. Also they should've
198 * been already set correctly by firmware, as
199 * flash/emmc is the boot-device.
204 i2c0_xfer: i2c0-xfer {
205 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
206 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
211 i2c1_xfer: i2c1-xfer {
212 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
213 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
218 i2c2_xfer: i2c2-xfer {
219 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
220 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
225 i2c3_xfer: i2c3-xfer {
226 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
227 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
232 i2c4_xfer: i2c4-xfer {
233 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
234 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
240 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
246 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
252 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
258 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
264 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
267 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
270 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
273 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
276 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
282 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
285 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
288 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
291 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
294 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
299 uart0_xfer: uart0-xfer {
300 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
301 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
304 uart0_cts: uart0-cts {
305 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
308 uart0_rts: uart0-rts {
309 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
314 uart1_xfer: uart1-xfer {
315 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
316 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
319 uart1_cts: uart1-cts {
320 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
323 uart1_rts: uart1-rts {
324 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
329 uart2_xfer: uart2-xfer {
330 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
331 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
333 /* no rts / cts for uart2 */
337 uart3_xfer: uart3-xfer {
338 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
339 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
342 uart3_cts: uart3-cts {
343 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
346 uart3_rts: uart3-rts {
347 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
353 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
357 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
361 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
365 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
368 sd0_bus1: sd0-bus-width1 {
369 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
372 sd0_bus4: sd0-bus-width4 {
373 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
374 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
375 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
376 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
382 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
386 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
390 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
394 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
397 sd1_bus1: sd1-bus-width1 {
398 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
401 sd1_bus4: sd1-bus-width4 {
402 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
403 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
404 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
405 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&i2c0_xfer>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&i2c1_xfer>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&i2c2_xfer>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&i2c3_xfer>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&i2c4_xfer>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&pwm0_out>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pwm1_out>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&pwm2_out>;
462 pinctrl-names = "default";
463 pinctrl-0 = <&pwm3_out>;
467 pinctrl-names = "default";
468 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
472 pinctrl-names = "default";
473 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&uart0_xfer>;
482 pinctrl-names = "default";
483 pinctrl-0 = <&uart1_xfer>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&uart2_xfer>;
492 pinctrl-names = "default";
493 pinctrl-0 = <&uart3_xfer>;
497 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";