arch/arm/boot/dts/rk312x.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/soc/rockchip,boot-mode.h>
  46 #include <dt-bindings/clock/rk3128-cru.h>
  47
  48 / {
  49         interrupt-parent = <&gic>;
  50         #address-cells = <1>;
  51         #size-cells = <1>;
  52
  53         aliases {
  54                 serial0 = &uart0;
  55                 serial1 = &uart1;
  56                 serial2 = &uart2;
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61         };
  62
  63         cpus {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66
  67                 cpu0: cpu@f00 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a7";
  70                         reg = <0xf00>;
  71                 };
  72                 cpu1: cpu@f01 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a7";
  75                         reg = <0xf01>;
  76                 };
  77                 cpu2: cpu@f02 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a7";
  80                         reg = <0xf02>;
  81                 };
  82                 cpu3: cpu@f03 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a7";
  85                         reg = <0xf03>;
  86                 };
  87         };
  88
  89         amba {
  90                 compatible = "simple-bus";
  91                 #address-cells = <1>;
  92                 #size-cells = <1>;
  93                 ranges;
  94
  95                 pdma: pdma@20078000 {
  96                         compatible = "arm,pl330", "arm,primecell";
  97                         reg = <0x20078000 0x4000>;
  98                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  99                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 100                         #dma-cells = <1>;
 101                         arm,pl330-broken-no-flushp;
 102                         peripherals-req-type-burst;
 103                         clocks = <&cru ACLK_DMAC>;
 104                         clock-names = "apb_pclk";
 105                 };
 106         };
 107
 108         arm-pmu {
 109                 compatible = "arm,cortex-a7-pmu";
 110                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 111                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 112                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 113                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 114                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 115         };
 116
 117         timer {
 118                 compatible = "arm,armv7-timer";
 119                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 120                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 121                 clock-frequency = <24000000>;
 122         };
 123
 124         xin24m: oscillator {
 125                 compatible = "fixed-clock";
 126                 clock-frequency = <24000000>;
 127                 clock-output-names = "xin24m";
 128                 #clock-cells = <0>;
 129         };
 130
 131         gpu: gpu@0x10091000 {
 132                 compatible = "arm,mali400";
 133                 reg = <0x10091000 0x200>,
 134                       <0x10090000 0x100>,
 135                       <0x10093000 0x100>,
 136                       <0x10098000 0x1100>,
 137                       <0x10094000 0x100>,
 138                       <0x1009A000 0x1100>,
 139                       <0x10095000 0x100>;
 140
 141                 reg-names = "Mali_L2",
 142                             "Mali_GP",
 143                             "Mali_GP_MMU",
 144                             "Mali_PP0",
 145                             "Mali_PP0_MMU",
 146                             "Mali_PP1",
 147                             "Mali_PP1_MMU";
 148
 149                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 151                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 152                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 153                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 155
 156                 interrupt-names = "Mali_GP_IRQ",
 157                                   "Mali_GP_MMU_IRQ",
 158                                   "Mali_PP0_IRQ",
 159                                   "Mali_PP0_MMU_IRQ",
 160                                   "Mali_PP1_IRQ",
 161                                   "Mali_PP1_MMU_IRQ";
 162                 clocks = <&cru ACLK_GPU>;
 163                 #cooling-cells = <2>; /* min followed by max */
 164                 clock-names = "clk_mali";
 165                 operating-points-v2 = <&gpu_opp_table>;
 166                 status = "disabled";
 167
 168                 gpu_power_model: power_model {
 169                         compatible = "arm,mali-simple-power-model";
 170                         voltage = <900>;
 171                         frequency = <500>;
 172                         static-power = <300>;
 173                         dynamic-power = <396>;
 174                         ts = <32000 4700 (-80) 2>;
 175                         thermal-zone = "soc-thermal";
 176                 };
 177         };
 178
 179         gpu_opp_table: opp-table2 {
 180                 compatible = "operating-points-v2";
 181
 182                 opp-200000000 {
 183                         opp-hz = /bits/ 64 <200000000>;
 184                         opp-microvolt = <1000000>;
 185                 };
 186                 opp-300000000 {
 187                         opp-hz = /bits/ 64 <300000000>;
 188                         opp-microvolt = <1025000>;
 189                 };
 190                 opp-400000000 {
 191                         opp-hz = /bits/ 64 <500000000>;
 192                         opp-microvolt = <1125000>;
 193                 };
 194         };
 195
 196         gic: interrupt-controller@10139000 {
 197                 compatible = "arm,cortex-a7-gic";
 198                 interrupt-controller;
 199                 #interrupt-cells = <3>;
 200                 #address-cells = <0>;
 201
 202                 reg = <0x10139000 0x1000>,
 203                       <0x1013a000 0x1000>,
 204                       <0x1013c000 0x2000>,
 205                       <0x1013e000 0x2000>;
 206                 interrupts = <GIC_PPI 9 0xf04>;
 207         };
 208
 209
 210         grf: syscon@20008000 {
 211                 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
 212                 reg = <0x20008000 0x1000>;
 213         };
 214
 215         timer@20044000 {
 216                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 217                 reg = <0x20044000 0x20>;
 218                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 220                 clock-names = "timer", "pclk";
 221         };
 222
 223         pwm0: pwm@20050000 {
 224                 compatible = "rockchip,rk3288-pwm";
 225                 reg = <0x20050000 0x10>;
 226                 #pwm-cells = <3>;
 227                 pinctrl-names = "default";
 228                 pinctrl-0 = <&pwm0_pin>;
 229                 clocks = <&cru PCLK_PWM>;
 230                 clock-names = "pwm";
 231                 status = "disabled";
 232         };
 233
 234         pwm1: pwm@20050010 {
 235                 compatible = "rockchip,rk3288-pwm";
 236                 reg = <0x20050010 0x10>;
 237                 #pwm-cells = <3>;
 238                 pinctrl-names = "default";
 239                 pinctrl-0 = <&pwm1_pin>;
 240                 clocks = <&cru PCLK_PWM>;
 241                 clock-names = "pwm";
 242                 status = "disabled";
 243         };
 244
 245         pwm2: pwm@20050020 {
 246                 compatible = "rockchip,rk3288-pwm";
 247                 reg = <0x20050020 0x10>;
 248                 #pwm-cells = <3>;
 249                 pinctrl-names = "default";
 250                 pinctrl-0 = <&pwm2_pin>;
 251                 clocks = <&cru PCLK_PWM>;
 252                 clock-names = "pwm";
 253                 status = "disabled";
 254         };
 255
 256         pwm3: pwm@20050030 {
 257                 compatible = "rockchip,rk3288-pwm";
 258                 reg = <0x20050030 0x10>;
 259                 #pwm-cells = <3>;
 260                 pinctrl-names = "default";
 261                 pinctrl-0 = <&pwm3_pin>;
 262                 clocks = <&cru PCLK_PWM>;
 263                 clock-names = "pwm";
 264                 status = "disabled";
 265         };
 266
 267         i2c1: i2c@20054000 {
 268                 compatible = "rockchip,rk3288-i2c";
 269                 reg = <0x20054000 0x1000>;
 270                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 271                 #address-cells = <1>;
 272                 #size-cells = <0>;
 273                 clock-names = "i2c";
 274                 clocks = <&cru PCLK_I2C1>;
 275                 pinctrl-names = "default";
 276                 pinctrl-0 = <&i2c1_xfer>;
 277                 status = "disabled";
 278         };
 279
 280         i2c2: i2c@20058000 {
 281                 compatible = "rockchip,rk3288-i2c";
 282                 reg = <0x20058000 0x1000>;
 283                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 284                 #address-cells = <1>;
 285                 #size-cells = <0>;
 286                 clock-names = "i2c";
 287                 clocks = <&cru PCLK_I2C2>;
 288                 pinctrl-names = "default";
 289                 pinctrl-0 = <&i2c2_xfer>;
 290                 status = "disabled";
 291         };
 292
 293         i2c3: i2c@2005c000 {
 294                 compatible = "rockchip,rk3288-i2c";
 295                 reg = <0x2005c000 0x1000>;
 296                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 297                 #address-cells = <1>;
 298                 #size-cells = <0>;
 299                 clock-names = "i2c";
 300                 clocks = <&cru PCLK_I2C3>;
 301                 pinctrl-names = "default";
 302                 pinctrl-0 = <&i2c3_xfer>;
 303                 status = "disabled";
 304         };
 305
 306         uart0: serial@20060000 {
 307                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 308                 reg = <0x20060000 0x100>;
 309                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 310                 clock-frequency = <24000000>;
 311                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 312                 clock-names = "baudclk", "apb_pclk";
 313                 reg-shift = <2>;
 314                 reg-io-width = <4>;
 315                 pinctrl-names = "default";
 316                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 317                 status = "disabled";
 318         };
 319
 320         uart1: serial@20064000 {
 321                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 322                 reg = <0x20064000 0x100>;
 323                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 324                 clock-frequency = <24000000>;
 325                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 326                 clock-names = "baudclk", "apb_pclk";
 327                 reg-shift = <2>;
 328                 reg-io-width = <4>;
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 331                 status = "disabled";
 332         };
 333
 334         uart2: serial@20068000 {
 335                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 336                 reg = <0x20068000 0x100>;
 337                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 338                 clock-frequency = <24000000>;
 339                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 340                 clock-names = "baudclk", "apb_pclk";
 341                 reg-shift = <2>;
 342                 reg-io-width = <4>;
 343                 pinctrl-names = "default";
 344                 pinctrl-0 = <&uart2_xfer>;
 345                 status = "disabled";
 346         };
 347
 348         saradc: saradc@2006c000 {
 349                 compatible = "rockchip,saradc";
 350                 reg = <0x2006c000 0x100>;
 351                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 352                 #io-channel-cells = <1>;
 353                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 354                 clock-names = "saradc", "apb_pclk";
 355                 resets = <&cru SRST_SARADC>;
 356                 reset-names = "saradc-apb";
 357                 status = "disabled";
 358         };
 359
 360         i2c0: i2c@20070000 {
 361                 compatible = "rockchip,rk3288-i2c";
 362                 reg = <0x20070000 0x1000>;
 363                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 clock-names = "i2c";
 367                 clocks = <&cru PCLK_I2C0>;
 368                 pinctrl-names = "default";
 369                 pinctrl-0 = <&i2c0_xfer>;
 370                 status = "disabled";
 371         };
 372
 373         spi0: spi@20074000 {
 374                 compatible = "rockchip,rk3288-spi";
 375                 reg = <0x20074000 0x1000>;
 376                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
 379                 clock-names = "spiclk", "apb_pclk";
 380                 dmas = <&pdma 8>, <&pdma 9>;
 381                 dma-names = "tx", "rx";
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 status = "disabled";
 385         };
 386
 387         pinctrl: pinctrl {
 388                 compatible = "rockchip,rk3128-pinctrl";
 389                 rockchip,grf = <&grf>;
 390                 #address-cells = <1>;
 391                 #size-cells = <1>;
 392                 ranges;
 393
 394                 gpio0: gpio0@2007c000 {
 395                         compatible = "rockchip,gpio-bank";
 396                         reg = <0x2007c000 0x100>;
 397                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 398                         clocks = <&cru PCLK_GPIO0>;
 399
 400                         gpio-controller;
 401                         #gpio-cells = <2>;
 402
 403                         interrupt-controller;
 404                         #interrupt-cells = <2>;
 405                 };
 406
 407                 gpio1: gpio1@20080000 {
 408                         compatible = "rockchip,gpio-bank";
 409                         reg = <0x20080000 0x100>;
 410                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 411                         clocks = <&cru PCLK_GPIO1>;
 412
 413                         gpio-controller;
 414                         #gpio-cells = <2>;
 415
 416                         interrupt-controller;
 417                         #interrupt-cells = <2>;
 418                 };
 419
 420                 gpio2: gpio2@20084000 {
 421                         compatible = "rockchip,gpio-bank";
 422                         reg = <0x20084000 0x100>;
 423                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 424                         clocks = <&cru PCLK_GPIO2>;
 425
 426                         gpio-controller;
 427                         #gpio-cells = <2>;
 428
 429                         interrupt-controller;
 430                         #interrupt-cells = <2>;
 431                 };
 432
 433                 gpio3: gpio3@20088000 {
 434                         compatible = "rockchip,gpio-bank";
 435                         reg = <0x20088000 0x100>;
 436                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 437                         clocks = <&cru PCLK_GPIO3>;
 438
 439                         gpio-controller;
 440                         #gpio-cells = <2>;
 441
 442                         interrupt-controller;
 443                         #interrupt-cells = <2>;
 444                 };
 445
 446                 pcfg_pull_up: pcfg-pull-up {
 447                         bias-pull-up;
 448                 };
 449
 450                 pcfg_pull_down: pcfg-pull-down {
 451                         bias-pull-down;
 452                 };
 453
 454                 pcfg_pull_none: pcfg-pull-none {
 455                         bias-disable;
 456                 };
 457
 458                 emmc {
 459                         emmc_clk: emmc-clk {
 460                                 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
 461                         };
 462
 463                         emmc_cmd: emmc-cmd {
 464                                 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_up>;
 465                         };
 466
 467                         emmc_cmd1: emmc-cmd1 {
 468                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_up>;
 469                         };
 470
 471                         emmc_pwr: emmc-pwr {
 472                                 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_up>;
 473                         };
 474
 475                         emmc_bus1: emmc-bus1 {
 476                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
 477                         };
 478
 479                         emmc_bus4: emmc-bus4 {
 480                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>,
 481                                                 <1 RK_PD1 2 &pcfg_pull_up>,
 482                                                 <1 RK_PD2 2 &pcfg_pull_up>,
 483                                                 <1 RK_PD3 2 &pcfg_pull_up>;
 484                         };
 485
 486                         emmc_bus8: emmc-bus8 {
 487                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>,
 488                                                 <1 RK_PD1 2 &pcfg_pull_up>,
 489                                                 <1 RK_PD2 2 &pcfg_pull_up>,
 490                                                 <1 RK_PD3 2 &pcfg_pull_up>,
 491                                                 <1 RK_PD4 2 &pcfg_pull_up>,
 492                                                 <1 RK_PD5 2 &pcfg_pull_up>,
 493                                                 <1 RK_PD6 2 &pcfg_pull_up>,
 494                                                 <1 RK_PD7 2 &pcfg_pull_up>;
 495                         };
 496                 };
 497
 498                 i2c0 {
 499                         i2c0_xfer: i2c0-xfer {
 500                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
 501                                                 <0 RK_PA1 1 &pcfg_pull_none>;
 502                         };
 503                 };
 504
 505                 i2c1 {
 506                         i2c1_xfer: i2c1-xfer {
 507                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
 508                                                 <0 RK_PA3 1 &pcfg_pull_none>;
 509                         };
 510                 };
 511
 512                 i2c2 {
 513                         i2c2_xfer: i2c2-xfer {
 514                                 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
 515                                                 <2 RK_PC5 3 &pcfg_pull_none>;
 516                         };
 517                 };
 518
 519                 i2c3 {
 520                         i2c3_xfer: i2c3-xfer {
 521                                 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
 522                                                 <0 RK_PA7 1 &pcfg_pull_none>;
 523                         };
 524                 };
 525
 526                 uart0 {
 527                         uart0_xfer: uart0-xfer {
 528                                 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_up>,
 529                                                 <2 RK_PD3 2 &pcfg_pull_none>;
 530                         };
 531
 532                         uart0_cts: uart0-cts {
 533                                 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
 534                         };
 535
 536                         uart0_rts: uart0-rts {
 537                                 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
 538                         };
 539                 };
 540
 541                 uart1 {
 542                         uart1_xfer: uart1-xfer {
 543                                 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_up>,
 544                                                 <1 RK_PB2 2 &pcfg_pull_none>;
 545                         };
 546
 547                         uart1_cts: uart1-cts {
 548                                 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
 549                         };
 550
 551                         uart1_rts: uart1-rts {
 552                                 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
 553                         };
 554                 };
 555
 556                 uart2 {
 557                         uart2_xfer: uart2-xfer {
 558                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
 559                                                 <1 RK_PC3 2 &pcfg_pull_none>;
 560                         };
 561
 562                         uart2_cts: uart2-cts {
 563                                 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
 564                         };
 565
 566                         uart2_rts: uart2-rts {
 567                                 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
 568                         };
 569                 };
 570
 571                 sdmmc {
 572                         sdmmc_clk: sdmmc-clk {
 573                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
 574                         };
 575
 576                         sdmmc_cmd: sdmmc-cmd {
 577                                 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>;
 578                         };
 579
 580                         sdmmc_wp: sdmmc-wp {
 581                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>;
 582                         };
 583
 584                         sdmmc_pwren: sdmmc-pwren {
 585                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>;
 586                         };
 587
 588                         sdmmc_bus4: sdmmc-bus4 {
 589                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>,
 590                                                 <1 RK_PC3 1 &pcfg_pull_up>,
 591                                                 <1 RK_PC4 1 &pcfg_pull_up>,
 592                                                 <1 RK_PC5 1 &pcfg_pull_up>;
 593                         };
 594                 };
 595
 596                 sdio {
 597                         sdio_clk: sdio-clk {
 598                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
 599                         };
 600
 601                         sdio_cmd: sdio-cmd {
 602                                 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_up>;
 603                         };
 604
 605                         sdio_pwren: sdio-pwren {
 606                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>;
 607                         };
 608
 609                         sdio_bus4: sdio-bus4 {
 610                                 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_up>,
 611                                                 <1 RK_PA2 2 &pcfg_pull_up>,
 612                                                 <1 RK_PA4 2 &pcfg_pull_up>,
 613                                                 <1 RK_PA5 2 &pcfg_pull_up>;
 614                         };
 615                 };
 616
 617                 hdmi {
 618                         hdmii2c_xfer: hdmii2c-xfer {
 619                                 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
 620                                                 <0 RK_PA7 2 &pcfg_pull_none>;
 621                         };
 622                 };
 623
 624                 i2s {
 625                         i2s_bus: i2s-bus {
 626                                 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
 627                                                 <0 RK_PB1 1 &pcfg_pull_none>,
 628                                                 <0 RK_PB3 1 &pcfg_pull_none>,
 629                                                 <0 RK_PB4 1 &pcfg_pull_none>,
 630                                                 <0 RK_PB5 1 &pcfg_pull_none>,
 631                                                 <0 RK_PB6 1 &pcfg_pull_none>;
 632                         };
 633
 634                         i2s1_bus: i2s1-bus {
 635                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
 636                                                 <1 RK_PA1 1 &pcfg_pull_none>,
 637                                                 <1 RK_PA2 1 &pcfg_pull_none>,
 638                                                 <1 RK_PA3 1 &pcfg_pull_none>,
 639                                                 <1 RK_PA4 1 &pcfg_pull_none>,
 640                                                 <1 RK_PA5 1 &pcfg_pull_none>;
 641                         };
 642                 };
 643
 644                 pwm0 {
 645                         pwm0_pin: pwm0-pin {
 646                                 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
 647                         };
 648                 };
 649
 650                 pwm1 {
 651                         pwm1_pin: pwm1-pin {
 652                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
 653                         };
 654                 };
 655
 656                 pwm2 {
 657                         pwm2_pin: pwm2-pin {
 658                                 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
 659                         };
 660                 };
 661
 662                 pwm3 {
 663                         pwm3_pin: pwm3-pin {
 664                                 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
 665                         };
 666                 };
 667
 668                 spi {
 669                         spi0_clk: spi0-clk {
 670                                 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>;
 671                         };
 672
 673                         spi0_cs0: spi0-cs0 {
 674                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_up>;
 675                         };
 676
 677                         spi0_tx: spi0-tx {
 678                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>;
 679                         };
 680
 681                         spi0_rx: spi0-rx {
 682                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>;
 683                         };
 684
 685                         spi0_cs1: spi0-cs1 {
 686                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
 687                         };
 688
 689                         spi1_clk: spi1-clk {
 690                                 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
 691                         };
 692
 693                         spi1_cs0: spi1-cs0 {
 694                                 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_up>;
 695                         };
 696
 697                         spi1_tx: spi1-tx {
 698                                 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_up>;
 699                         };
 700
 701                         spi1_rx: spi1-rx {
 702                                 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_up>;
 703                         };
 704
 705                         spi1_cs1: spi1-cs1 {
 706                                 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_up>;
 707                         };
 708
 709                         spi2_clk: spi2-clk {
 710                                 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
 711                         };
 712
 713                         spi2_cs0: spi2-cs0 {
 714                                 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
 715                         };
 716
 717                         spi2_tx: spi2-tx {
 718                                 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
 719                         };
 720
 721                         spi2_rx: spi2-rx {
 722                                 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
 723                         };
 724                 };
 725         };
 726 };