arch/arm/boot/dts/rk312x.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/sensor-dev.h>
   4 #include <dt-bindings/clock/rk_system_status.h>
   5 #include <dt-bindings/rkfb/rk_fb.h>
   6
   7 #include "skeleton.dtsi"
   8 #include "rk312x-clocks.dtsi"
   9 #include "rk312x-pinctrl.dtsi"
  10
  11 / {
  12         compatible = "rockchip,rk312x";
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 serial0 = &uart0;
  18                 serial1 = &uart1;
  19                 serial2 = &uart2;
  20                 i2c0 = &i2c0;
  21                 i2c1 = &i2c1;
  22                 i2c2 = &i2c2;
  23                 i2c3 = &i2c3;
  24                 lcdc = &lcdc;
  25         //      spi0 = &spi0;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a7";
  35                         reg = <0xf00>;
  36                 };
  37                 cpu@1 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a7";
  40                         reg = <0xf01>;
  41                 };
  42                 cpu@2 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a7";
  45                         reg = <0xf02>;
  46                 };
  47                 cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a7";
  50                         reg = <0xf03>;
  51                 };
  52         };
  53
  54         gic: interrupt-controller@10139000 {
  55                 compatible = "arm,cortex-a15-gic";
  56                 interrupt-controller;
  57                 #interrupt-cells = <3>;
  58                 #address-cells = <0>;
  59                 reg = <0x10139000 0x1000>,
  60                       <0x1013a000 0x1000>;
  61         };
  62
  63         arm-pmu {
  64                 compatible = "arm,cortex-a7-pmu";
  65                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  66                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  67                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  68                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  69         };
  70
  71         cpu_axi_bus: cpu_axi_bus {
  72                 compatible = "rockchip,cpu_axi_bus";
  73                 #address-cells = <1>;
  74                 #size-cells = <1>;
  75                 ranges;
  76
  77                 qos {
  78                         #address-cells = <1>;
  79                         #size-cells = <1>;
  80                         ranges;
  81
  82                         crypto {
  83                                 reg = <0x10128080 0x20>;
  84                         };
  85                         core {
  86                                 reg = <0x1012a000 0x20>;
  87                         };
  88                         peri {
  89                                 reg = <0x1012c000 0x20>;
  90                         };
  91                         gpu {
  92                                 reg = <0x1012d000 0x20>;
  93                         };
  94                         vpu {
  95                                 reg = <0x1012e000 0x20>;
  96                         };
  97                         rga {
  98                                 reg = <0x1012f000 0x20>;
  99                         };
 100                         ebc {
 101                                 reg = <0x1012f080 0x20>;
 102                         };
 103                         iep {
 104                                 reg = <0x1012f100 0x20>;
 105                         };
 106                         lcdc {
 107                                 reg = <0x1012f180 0x20>;
 108                                 rockchip,priority = <3 3>;
 109                         };
 110                         vip {
 111                                 reg = <0x1012f200 0x20>;
 112                                 rockchip,priority = <3 3>;
 113                         };
 114                 };
 115
 116                 msch {
 117                         #address-cells = <1>;
 118                         #size-cells = <1>;
 119                         ranges;
 120
 121                         msch@10128000 {
 122                                 reg = <0x10128000 0x20>;
 123                                 rockchip,read-latency = <0x3f>;
 124                         };
 125                 };
 126         };
 127
 128         sram: sram@10080000 {
 129                 compatible = "mmio-sram";
 130                 reg = <0x10080000 0x2000>;
 131                 map-exec;
 132                 map-cacheable;
 133         };
 134
 135         timer {
 136                 compatible = "arm,armv7-timer";
 137                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 138                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 139                 clock-frequency = <24000000>;
 140         };
 141
 142         timer@20044000 {
 143                 compatible = "rockchip,timer";
 144                 reg = <0x20044000 0x20>;
 145                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 146                 rockchip,broadcast = <1>;
 147         };
 148
 149         watchdog: wdt@2004c000 {
 150                 compatible = "rockchip,watch dog";
 151                 reg = <0x2004c000 0x100>;
 152         //      clocks = <&clk_gates7 15>;
 153                 clock-names = "pclk_wdt";
 154                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 155                 rockchip,irq = <1>;
 156                 rockchip,timeout = <60>;
 157                 rockchip,atboot = <1>;
 158                 rockchip,debug = <0>;
 159                 status = "disabled";
 160         };
 161
 162         amba {
 163                 #address-cells = <1>;
 164                 #size-cells = <1>;
 165                 compatible = "arm,amba-bus";
 166                 interrupt-parent = <&gic>;
 167                 ranges;
 168
 169                 pdma: pdma@20078000 {
 170                         compatible = "arm,pl330", "arm,primecell";
 171                         reg = <0x20078000 0x4000>;
 172                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 173                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 174                         #dma-cells = <1>;
 175                 };
 176         };
 177
 178         reset: reset@20000110 {
 179                 compatible = "rockchip,reset";
 180                 reg = <0x20000110 0x24>;
 181                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 182                 #reset-cells = <1>;
 183         };
 184
 185         nandc: nandc@10500000 {
 186                 compatible = "rockchip,rk-nandc";
 187                 reg = <0x10500000 0x4000>;
 188                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 189                 //pinctrl-names = "default";
 190                 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
 191                 nandc_id = <0>;
 192                 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 15>;
 193                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 194         };
 195
 196         nandc0reg: nandc0@10500000 {
 197                 compatible = "rockchip,rk-nandc";
 198                 reg = <0x10500000 0x4000>;
 199         };
 200         uart0: serial@20060000 {
 201                 compatible = "rockchip,serial";
 202                 reg = <0x20060000 0x100>;
 203                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 204                 clock-frequency = <24000000>;
 205                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 206                 clock-names = "sclk_uart", "pclk_uart";
 207                 reg-shift = <2>;
 208                 reg-io-width = <4>;
 209                 dmas = <&pdma 2>, <&pdma 3>;
 210                 #dma-cells = <2>;
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 213                 status = "disabled";
 214         };
 215
 216         uart1: serial@20064000 {
 217                 compatible = "rockchip,serial";
 218                 reg = <0x20064000 0x100>;
 219                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 220                 clock-frequency = <24000000>;
 221                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 222                 clock-names = "sclk_uart", "pclk_uart";
 223                 reg-shift = <2>;
 224                 reg-io-width = <4>;
 225                 dmas = <&pdma 4>, <&pdma 5>;
 226                 #dma-cells = <2>;
 227                 pinctrl-names = "default";
 228                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 229                 status = "disabled";
 230         };
 231
 232         uart2: serial@20068000 {
 233                 compatible = "rockchip,serial";
 234                 reg = <0x20068000 0x100>;
 235                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 236                 clock-frequency = <24000000>;
 237                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 238                 clock-names = "sclk_uart", "pclk_uart";
 239                 reg-shift = <2>;
 240                 reg-io-width = <4>;
 241                 dmas = <&pdma 6>, <&pdma 7>;
 242                 #dma-cells = <2>;
 243                 pinctrl-names = "default";
 244                 pinctrl-0 = <&uart2_xfer>;
 245                 status = "disabled";
 246         };
 247
 248         gmac: eth@2008c000 {
 249                 compatible = "rockchip,rk312x-gmac";
 250                 reg = <0x2008c000 0x4000>;
 251                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;  /*irq=88*/
 252                 interrupt-names = "macirq";
 253                 clocks = <&clk_mac_ref>, <&clk_gates2 6>,
 254                         <&clk_gates2 7>, <&clk_gates2 4>,
 255                         <&clk_gates2 5>, <&clk_gates10 10>,
 256                         <&clk_gates10 11>;
 257                 clock-names = "clk_mac", "mac_clk_rx",
 258                         "mac_clk_tx", "clk_mac_ref",
 259                         "clk_mac_refout", "aclk_mac",
 260                         "pclk_mac";
 261                 phy-mode = "rgmii";
 262                 pinctrl-names = "default";
 263                 pinctrl-0 = <&gmac_rxdv &gmac_txclk &gmac_crs &gmac_rxclk &gmac_mdio &gmac_txen &gmac_clk &gmac_rxer &gmac_rxd1 &gmac_rxd0 &gmac_txd1 &gmac_txd0 &gmac_rxd3 &gmac_rxd2 &gmac_txd2 &gmac_txd3 &gmac_col_gpio &gmac_mdc>;
 264         };
 265
 266         fiq-debugger {
 267                 compatible = "rockchip,fiq-debugger";
 268                 rockchip,serial-id = <2>;
 269                 rockchip,signal-irq = <106>;
 270                 rockchip,wake-irq = <0>;
 271                 status = "disabled";
 272         };
 273
 274         clocks-init{
 275                 compatible = "rockchip,clocks-init";
 276                 rockchip,clocks-init-parent =
 277                         <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll_div2>,
 278                         <&aclk_peri &clk_gpll_div2>, <&clk_uart0_pll &clk_gpll>,
 279                         <&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
 280                         <&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 281                         <&clk_vepu &clk_gpll_div2>, <&clk_vdpu &clk_gpll_div2>,
 282                         <&clk_hevc_core &clk_gpll>, <&aclk_vio0_pre &clk_gpll_div2>,
 283                         <&aclk_vio1_pre &clk_gpll_div2>, <&hclk_vio_pre &clk_gpll_div2>,
 284                         <&sclk_lcdc0 &clk_cpll>, <&clk_gpu &clk_gpll_div2>,
 285                         <&clk_cif_pll &clk_gpll_div2>, <&dclk_ebc &clk_gpll_div2>,
 286                         <&clk_emmc &clk_gpll_div2>, <&clk_sdio &clk_gpll_div2>,
 287                         <&clk_sfc &clk_gpll_div2>, <&clk_sdmmc0 &clk_gpll_div2>,
 288                         <&clk_tsp &clk_gpll_div2>, <&clk_nandc &clk_gpll_div2>,
 289                         <&clk_mac_pll &clk_cpll>;
 290                 rockchip,clocks-init-rate =
 291                         <&clk_core 816000000>, <&clk_gpll 594000000>,
 292                         <&clk_cpll 400000000>, <&aclk_cpu 300000000>,
 293                         <&hclk_cpu_pre 150000000>, <&pclk_cpu_pre 75000000>,
 294                         <&aclk_peri 300000000>, <&hclk_peri_pre 150000000>,
 295                         <&pclk_peri_pre 75000000>, <&clk_gpu 300000000>,
 296                         <&aclk_vio0_pre 300000000>, <&hclk_vio_pre 150000000>,
 297                         <&aclk_vio1_pre 300000000>, <&clk_vepu 300000000>,
 298                         <&clk_vdpu 300000000>, <&clk_hevc_core 200000000>,
 299                         <&clk_mac_ref 125000000>;
 300         /*      rockchip,clocks-uboot-has-init =
 301                         <&aclk_vio1>;*/
 302         };
 303         gpu {
 304                 compatible = "arm,mali400";
 305                 reg = <0x10091000 0x200>,
 306                       <0x10090000 0x100>,
 307                       <0x10093000 0x100>,
 308                       <0x10098000 0x1100>,
 309                       <0x10094000 0x100>,
 310                       <0x1009A000 0x1100>,
 311                       <0x10095000 0x100>;
 312
 313                 reg-names = "Mali_L2",
 314                             "Mali_GP",
 315                             "Mali_GP_MMU",
 316                             "Mali_PP0",
 317                             "Mali_PP0_MMU",
 318                             "Mali_PP1",
 319                             "Mali_PP1_MMU";
 320
 321                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 322                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 323                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 324                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 325                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 326                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 327
 328                 interrupt-names = "Mali_GP_IRQ",
 329                                   "Mali_GP_MMU_IRQ",
 330                                   "Mali_PP0_IRQ",
 331                                   "Mali_PP0_MMU_IRQ",
 332                                   "Mali_PP1_IRQ",
 333                                   "Mali_PP1_MMU_IRQ";
 334           };
 335
 336         clocks-enable {
 337                 compatible = "rockchip,clocks-enable";
 338                 clocks =
 339                                 /*PD_CORE*/
 340                                 <&clk_gates0 6>,<&clk_gates0 0>,
 341                                 <&clk_gates0 7>,
 342
 343                                 /*PD_CPU*/
 344                                 <&clk_gates0 1>, <&clk_gates0 3>,
 345                                 <&clk_gates0 4>, <&clk_gates0 5>,
 346                                 <&clk_gates0 12>,
 347
 348                                 /*TIMER*/
 349                                 <&clk_gates10 3>, <&clk_gates10 4>,
 350                                 <&clk_gates10 5>, <&clk_gates10 6>,
 351                                 <&clk_gates10 7>, <&clk_gates10 8>,
 352
 353                                 /*PD_PERI*/
 354                                 <&clk_gates2 0>, <&hclk_peri_pre>,
 355                                 <&pclk_peri_pre>, <&clk_gates2 1>,
 356
 357                                 /*aclk_cpu_pre*/
 358                                 <&clk_gates4 12>,/*aclk_intmem*/
 359                                 <&clk_gates4 10>,/*aclk_strc_sys*/
 360
 361                                 /*hclk_cpu_pre*/
 362                                 //<&clk_gates5 6>,/*hclk_rom*/
 363                                 <&clk_gates3 5>,/*hclk_crypto*/
 364
 365                                 /*pclk_cpu_pre*/
 366                                 <&clk_gates5 4>,/*pclk_grf*/
 367                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
 368                                 //<&clk_gates5 14>,/*pclk_acodec*/
 369                                 //<&clk_gates3 8>,/*pclk_hdmi*/
 370
 371                                 /*aclk_peri_pre*/
 372                                 //<&clk_gates10 10>,/*aclk_gmac*/
 373                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
 374                                 <&clk_gates5 1>,/*aclk_dmac2*/
 375                                 <&clk_gates9 15>,/*aclk_peri_niu*/
 376                                 <&clk_gates9 2>,/*g_pclk_pmu*/
 377                                 <&clk_gates9 3>,/*g_pclk_pmu_noc*/
 378                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
 379
 380                                 /*hclk_peri_pre*/
 381                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
 382                                 //<&clk_gates9 13>,/*hclk_usb_peri*/
 383                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
 384
 385                                 /*pclk_peri_pre*/
 386                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
 387
 388                                 /*hclk_vio_pre*/
 389                                 //<&clk_gates6 12>,/*hclk_vio_niu*/
 390                                 //<&clk_gates6 1>,/*hclk_lcdc*/
 391
 392                                 /*aclk_vio0_pre*/
 393                                 //<&clk_gates6 13>,/*aclk_vio*/
 394                                 //<&clk_gates6 0>,/*aclk_lcdc*/
 395
 396                                 /*aclk_vio1_pre*/
 397                                 //<&clk_gates9 10>,/*aclk_vio1_niu*/
 398
 399                                 /*UART*/
 400                                 <&clk_gates1 12>,
 401                                 <&clk_gates1 13>,
 402                                 <&clk_gates8 2>,/*pclk_uart2*/
 403
 404                                 //<&clk_gpu>,
 405
 406                                 /*jtag*/
 407                                 //<&clk_gates1 3>,/*clk_jtag*/
 408
 409                                 /*pmu*/
 410                                 <&clk_gates1 0>;/*pclk_pmu_pre*/
 411         };
 412
 413         i2c0: i2c@20072000 {
 414                 compatible = "rockchip,rk30-i2c";
 415                 reg = <0x20072000 0x1000>;
 416                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 pinctrl-names = "default", "gpio";
 420                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 421                 pinctrl-1 = <&i2c0_gpio>;
 422                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 423                 clocks = <&clk_gates8 4>;
 424                 rockchip,check-idle = <1>;
 425                 status = "disabled";
 426         };
 427
 428         i2c1: i2c@20056000 {
 429                 compatible = "rockchip,rk30-i2c";
 430                 reg = <0x20056000 0x1000>;
 431                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 432                 #address-cells = <1>;
 433                 #size-cells = <0>;
 434                 pinctrl-names = "default", "gpio";
 435                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 436                 pinctrl-1 = <&i2c1_gpio>;
 437                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 438                 clocks = <&clk_gates8 5>;
 439                 rockchip,check-idle = <1>;
 440                 status = "disabled";
 441         };
 442
 443         i2c2: i2c@2005a000 {
 444                 compatible = "rockchip,rk30-i2c";
 445                 reg = <0x2005a000 0x1000>;
 446                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 pinctrl-names = "default", "gpio";
 450                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 451                 pinctrl-1 = <&i2c2_gpio>;
 452                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 453                 clocks = <&clk_gates8 6>;
 454                 rockchip,check-idle = <1>;
 455                 status = "disabled";
 456         };
 457
 458         i2c3: i2c@2005e000 {
 459                 compatible = "rockchip,rk30-i2c";
 460                 reg = <0x2005e000 0x1000>;
 461                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 462                 #address-cells = <1>;
 463                 #size-cells = <0>;
 464                 pinctrl-names = "default", "gpio";
 465                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 466                 pinctrl-1 = <&i2c3_gpio>;
 467                 gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>;
 468                 clocks = <&clk_gates8 7>;
 469                 rockchip,check-idle = <1>;
 470                 status = "disabled";
 471         };
 472
 473         i2s0: i2s@10220000 {
 474                 compatible = "rockchip-i2s";
 475                 reg = <0x10220000 0x1000>;
 476                 i2s-id = <0>;
 477                 clocks = <&clk_i2s_2ch>, <&clk_i2s_2ch_out>, <&clk_gates7 2>;
 478                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 479                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 480                 dmas = <&pdma 0>, <&pdma 1>;
 481                 //#dma-cells = <2>;
 482                 dma-names = "tx", "rx";
 483                 //pinctrl-names = "default", "sleep";
 484                 //pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 485                 //pinctrl-1 = <&i2s0_gpio>;
 486                 status = "disabled";
 487         };
 488
 489         i2s1: i2s@10200000 {
 490                 compatible = "rockchip-i2s";
 491                 reg = <0x10200000 0x1000>;
 492                 i2s-id = <1>;
 493                 clocks = <&clk_i2s_8ch>, <&clk_gates7 4>;
 494                 clock-names = "i2s_clk", "i2s_hclk";
 495                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 496                 dmas = <&pdma 14>, <&pdma 15>;
 497                 //#dma-cells = <2>;
 498                 dma-names = "tx", "rx";
 499         };
 500
 501         spdif: spdif@10204000 {
 502                 compatible = "rockchip-spdif";
 503                 reg = <0x10204000 0x1000>;
 504                 clocks = <&clk_spdif>, <&clk_gates10 9>;
 505                 clock-names = "spdif_mclk", "spdif_hclk";
 506                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 507                 dmas = <&pdma 13>;
 508                 //#dma-cells = <1>;
 509                 dma-names = "tx";
 510                 pinctrl-names = "default";
 511                 pinctrl-0 = <&spdif_tx>;
 512         };
 513
 514         dsihost0: mipi@10110000{
 515                 compatible = "rockchip,rk32-dsi";
 516                 rockchip,prop = <0>;
 517                 reg = <0x10110000 0x4000>, <0x20038000 0x4000>;
 518                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 519                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 520                 clocks = <&clk_gates2 15>, <&clk_gates5 0> ;//, <&pd_mipidsi>;
 521                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi";//, "pd_mipi_dsi";
 522                 status = "okay";
 523         };
 524
 525         emmc: rksdmmc@1021c000 {
 526                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 527                 reg = <0x1021c000 0x4000>;
 528                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 529                 #address-cells = <1>;
 530                 #size-cells = <0>;
 531                 //pinctrl-names = "default",,"suspend";
 532                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 533                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 534                 clock-names = "clk_mmc", "hclk_mmc";
 535                 dmas = <&pdma 12>;
 536                 dma-names = "dw_mci";
 537                 num-slots = <1>;
 538                 fifo-depth = <0x100>;
 539                 bus-width = <8>;
 540         };
 541
 542
 543         sdmmc: rksdmmc@10214000 {
 544                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 545                 reg = <0x10214000 0x4000>;
 546                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 547                 #address-cells = <1>;
 548                 #size-cells = <0>;
 549                 pinctrl-names = "default", "idle";
 550                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd  &sdmmc0_dectn &sdmmc0_bus4>;
 551                 pinctrl-1 = <&sdmmc0_gpio>;
 552                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 553                 clock-names = "clk_mmc", "hclk_mmc";
 554                 dmas = <&pdma 10>;
 555                 dma-names = "dw_mci";
 556                 num-slots = <1>;
 557                 fifo-depth = <0x100>;
 558                 bus-width = <4>;
 559         };
 560
 561         sdio: rksdmmc@10218000 {
 562                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 563                 reg = <0x10218000 0x4000>;
 564                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 pinctrl-names = "default","idle";
 568                 pinctrl-0 = <&sdio0_pwren &sdio0_cmd &sdio0_clk &sdio0_bus4>;
 569                 pinctrl-1 = <&sdio0_gpio>;
 570                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 571                 clock-names = "clk_mmc", "hclk_mmc";
 572                 dmas = <&pdma 11>;
 573                 dma-names = "dw_mci";
 574                 num-slots = <1>;
 575                 fifo-depth = <0x100>;
 576                 bus-width = <4>;
 577         };
 578
 579         adc: adc@2006c000 {
 580                 compatible = "rockchip,saradc";
 581                 reg = <0x2006c000 0x100>;
 582                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 583                 #io-channel-cells = <1>;
 584                 io-channel-ranges;
 585                 rockchip,adc-vref = <1800>;
 586                 clock-frequency = <1000000>;
 587                 clocks = <&clk_saradc>, <&clk_gates7 14>;
 588                 clock-names = "saradc", "pclk_saradc";
 589                 status = "disabled";
 590         };
 591
 592         pwm0: pwm@20050000 {
 593                 compatible = "rockchip,rk-pwm";
 594                 reg = <0x20050000 0x10>;
 595                 #pwm-cells = <2>;
 596                 pinctrl-names = "default";
 597                 pinctrl-0 = <&pwm0_pin>;
 598                 clocks = <&clk_gates7 10>;
 599                 clock-names = "pclk_pwm";
 600                 status = "disabled";
 601         };
 602
 603         pwm1: pwm@20050010 {
 604                 compatible = "rockchip,rk-pwm";
 605                 reg = <0x20050010 0x10>;
 606                 #pwm-cells = <2>;
 607                 pinctrl-names = "default";
 608                 pinctrl-0 = <&pwm1_pin>;
 609                 clocks = <&clk_gates7 10>;
 610                 clock-names = "pclk_pwm";
 611                 status = "disabled";
 612         };
 613
 614         pwm2: pwm@20050020 {
 615                 compatible = "rockchip,rk-pwm";
 616                 reg = <0x20050020 0x10>;
 617                 #pwm-cells = <2>;
 618                 pinctrl-names = "default";
 619                 pinctrl-0 = <&pwm2_pin>;
 620                 clocks = <&clk_gates7 10>;
 621                 clock-names = "pclk_pwm";
 622                 status = "disabled";
 623         };
 624
 625         pwm3: pwm@20050030 {
 626                 compatible = "rockchip,rk-pwm";
 627                 reg = <0x20050030 0x10>;
 628                 #pwm-cells = <2>;
 629                 pinctrl-names = "default";
 630                 pinctrl-0 = <&pwm3_pin>;
 631                 clocks = <&clk_gates7 10>;
 632                 clock-names = "pclk_pwm";
 633                 status = "disabled";
 634         };
 635
 636         remotectl: pwm@20050030 {
 637                 compatible = "rockchip,remotectl-pwm";
 638                 reg = <0x20050030 0x10>;
 639                 #pwm-cells = <2>;
 640                 pinctrl-names = "default";
 641                 pinctrl-0 = <&pwm3_pin>;
 642                 clocks = <&clk_gates7 10>;
 643                 clock-names = "pclk_pwm";
 644                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 645                 status = "okay";
 646         };
 647         dwc_control_usb: dwc-control-usb@20008000 {
 648                 compatible = "rockchip,rk3126-dwc-control-usb";
 649                 reg = <0x20008000 0x4>;
 650                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 651                 interrupt-names = "otg_bvalid";
 652                 clocks = <&clk_gates9 13>;
 653                 clock-names = "hclk_usb_peri";
 654                 rockchip,remote_wakeup;
 655                 rockchip,usb_irq_wakeup;
 656                 resets = <&reset RK3128_RST_USBPOR>;
 657                 reset-names = "usbphy_por";
 658                 usb_bc{
 659                         compatible = "inno,phy";
 660                         regbase = &dwc_control_usb;
 661                 };
 662         };
 663
 664         usb0: usb@10180000 {
 665                 compatible = "rockchip,rk3126_usb20_otg";
 666                 reg = <0x10180000 0x40000>;
 667                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 668                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 669                 clock-names = "clk_usbphy0", "hclk_usb0";
 670                 resets = <&reset RK3128_RST_USBOTG0>, <&reset RK3128_RST_USBOTG0>,
 671                                 <&reset RK3128_RST_OTGC0>;
 672                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
 673                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 674                 rockchip,usb-mode = <0>;
 675         };
 676
 677         usb1: usb@101c0000 {
 678                 compatible = "rockchip,rk3126_usb20_host";
 679                 reg = <0x101c0000 0x40000>;
 680                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 681                 clocks = <&clk_gates1 6>, <&clk_gates10 14>;
 682                 clock-names = "clk_usbphy1", "hclk_usb1";
 683                 resets = <&reset RK3128_RST_USBOTG1>, <&reset RK3128_RST_UTMI1>,
 684                                 <&reset RK3128_RST_OTGC1>;
 685                 reset-names = "host_ahb", "host_phy", "host_controller";
 686         };
 687
 688         fb: fb{
 689                 compatible = "rockchip,rk-fb";
 690                 rockchip,disp-mode = <ONE_DUAL>;
 691         };
 692
 693         rk_screen: rk_screen{
 694                 compatible = "rockchip,screen";
 695         };
 696
 697         lvds: lvds@20038000 {
 698                 compatible = "rockchip,rk31xx-lvds";
 699                 reg = <0x20038000 0x4000>;
 700                 clocks = <&clk_gates5 0>;
 701                 clock-names = "pclk_lvds";
 702         };
 703
 704         lcdc: lcdc@1010e000 {
 705                 compatible = "rockchip,rk312x-lcdc";
 706                 rockchip,prop = <PRMRY>;
 707                 reg = <0x1010e000 0x1000>;
 708                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 709                 clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>, <&pd_vop>, <&clk_cpll>;
 710                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_lcdc", "pd_lcdc", "sclk_pll";
 711                 rockchip,iommu-enabled = <1>;
 712                 status = "disabled";
 713         };
 714
 715         hdmi: hdmi@20034000 {
 716                 compatible = "rockchip,rk312x-hdmi";
 717                 reg = <0x20034000 0x4000>;
 718                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 719                 rockchip,hdmi_lcdc_source = <0>;
 720                 pinctrl-names = "default", "gpio";
 721                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 722                 pinctrl-1 = <&hdmi_gpio>;
 723                 clocks = <&clk_gates3 8>, <&pd_hdmi>;
 724                 clock-names = "pclk_hdmi", "pd_hdmi";
 725                 status = "disabled";
 726         };
 727
 728         tve: tve{
 729                 compatible = "rockchip,rk312x-tve";
 730                 reg = <0x1010e200 0x100>;
 731                 status = "disabled";
 732         };
 733
 734         vpu: vpu_service@10106000 {
 735                 compatible = "vpu_service";
 736                 iommu_enabled = <1>;
 737                 reg = <0x10106000 0x800>;
 738                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 739                 interrupt-names = "irq_enc", "irq_dec";
 740                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 741                 clock-names = "aclk_vcodec", "hclk_vcodec";
 742                 name = "vpu_service";
 743                 status = "okay";
 744         };
 745
 746         hevc: hevc_service@10104000 {
 747                 compatible = "rockchip,hevc_service";
 748                 iommu_enabled = <1>;
 749                 reg = <0x10104000 0x400>;
 750                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 751                 interrupt-names = "irq_dec";
 752                 clocks = <&clk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>;
 753                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
 754                 name = "hevc_service";
 755                 status = "okay";
 756         };
 757
 758         iep: iep@10108000 {
 759                 compatible = "rockchip,iep";
 760                 iommu_enabled = <1>;
 761                 reg = <0x10108000 0x800>;
 762                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 763                 clocks = <&clk_gates9 8>, <&clk_gates9 7>;
 764                 clock-names = "aclk_iep", "hclk_iep";
 765                 status = "okay";
 766         };
 767
 768         rga: rga@1010c000 {
 769                 compatible = "rockchip,rk312x-rga";
 770                 reg = <0x1010c000 0x1000>;
 771                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 772                 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
 773                 clock-names = "hclk_rga", "aclk_rga";
 774                 status = "okay";
 775         };
 776
 777   vop_mmu {
 778                 dbgname = "vop";
 779                 compatible = "rockchip,vop_mmu";
 780                 reg = <0x1010e300 0x100>;
 781                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 782                 interrupt-names = "vop_mmu";
 783           };
 784
 785           hevc_mmu {
 786                 dbgname = "hevc";
 787                 compatible = "rockchip,hevc_mmu";
 788                 reg = <0x10104440 0x40>,
 789                       <0x10104480 0x40>;
 790                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 791                 interrupt-names = "hevc_mmu";
 792           };
 793
 794           vpu_mmu {
 795                 dbgname = "vpu";
 796                 compatible = "rockchip,vpu_mmu";
 797                 reg = <0x10106800 0x100>;
 798                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 799                 interrupt-names = "vpu_mmu";
 800           };
 801
 802           iep_mmu {
 803                 dbgname = "iep";
 804                 compatible = "rockchip,iep_mmu";
 805                 reg = <0x10108800 0x100>;
 806                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 807                 interrupt-names = "iep_mmu";
 808           };
 809
 810           dvfs {
 811                 temp-limit-enable = <0>;
 812                 target-temp = <80>;
 813
 814                 vd_arm: vd_arm {
 815                         regulator_name = "vdd_arm";
 816                         pd_core {
 817                                 clk_core_dvfs_table: clk_core {
 818                                         operating-points = <
 819                                                 /* KHz    uV */
 820                                                 312000 1100000
 821                                                 504000 1100000
 822                                                 816000 1100000
 823                                                 1008000 1100000
 824                                                 >;
 825                                         temp-channel = <1>;
 826                                         normal-temp-limit = <
 827                                         /*delta-temp    delta-freq*/
 828                                                 3       96000
 829                                                 6       144000
 830                                                 9       192000
 831                                                 15      384000
 832                                                 >;
 833                                         performance-temp-limit = <
 834                                                 /*temp    freq*/
 835                                                 110     816000
 836                                                 >;
 837                                         status = "okay";
 838                                         regu-mode-table = <
 839                                                 /*freq     mode*/
 840                                                 1008000    4
 841                                                 0          3
 842                                         >;
 843                                         regu-mode-en = <0>;
 844                                 };
 845                         };
 846                 };
 847
 848                 vd_logic: vd_logic {
 849                         regulator_name = "vdd_logic";
 850                         pd_ddr {
 851                                 clk_ddr_dvfs_table: clk_ddr {
 852                                         operating-points = <
 853                                                 /* KHz    uV */
 854                                                 200000 1200000
 855                                                 300000 1200000
 856                                                 400000 1200000
 857                                                 >;
 858                                         status = "disabled";
 859                                 };
 860                         };
 861
 862                         pd_gpu {
 863                                 clk_gpu_dvfs_table: clk_gpu {
 864                                         operating-points = <
 865                                                 /* KHz    uV */
 866                                                 200000 1200000
 867                                                 300000 1200000
 868                                                 400000 1200000
 869                                                 >;
 870                                         status = "okay";
 871                                         regu-mode-table = <
 872                                                 /*freq     mode*/
 873                                                 200000     4
 874                                                 0          3
 875                                         >;
 876                                         regu-mode-en = <0>;
 877                                 };
 878                         };
 879                 };
 880         };
 881         ion {
 882                 compatible = "rockchip,ion";
 883                 #address-cells = <1>;
 884                 #size-cells = <0>;
 885
 886                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 887                         compatible = "rockchip,ion-reserve";
 888                         rockchip,ion_heap = <1>;
 889                         reg = <0x00000000 0x800000>; /* 8MB */
 890                 };
 891                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 892                         rockchip,ion_heap = <3>;
 893                 };
 894         };
 895         cif: cif@1010a000 {
 896              compatible = "rockchip,cif";
 897              reg = <0x1010a000 0x2000>;
 898              interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 899              clocks = <&pd_vip>,<&clk_gates6 5>,<&clk_gates6 4>,<&clk_cif0_in>,<&clk_cif_out>;
 900              clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
 901              status = "okay";
 902              };
 903
 904         codec_hdmi_spdif: codec-hdmi-spdif {
 905                 compatible = "hdmi-spdif";
 906         };
 907
 908         rockchip-hdmi-spdif {
 909                 compatible = "rockchip-hdmi-spdif";
 910                 dais {
 911                         dai0 {
 912                                 audio-codec = <&codec_hdmi_spdif>;
 913                                 i2s-controller = <&spdif>;
 914                         };
 915                 };
 916         };
 917         codec: codec@20030000 {
 918                 compatible = "rk312x-codec";
 919                 reg = <0x20030000 0x4000>;
 920                 //pinctrl-names = "default";
 921                 //pinctrl-0 = <&i2s_gpio>;
 922                 boot_depop = <1>;
 923                 pa_enable_time = <1000>;
 924                 clocks = <&clk_gates5 14>;
 925                 clock-names = "g_pclk_acodec";
 926         };
 927         rockchip-audio {
 928                 compatible = "audio-rk312x";
 929                 dais {
 930                         dai0 {
 931                                 audio-codec = <&codec>;
 932                                 i2s-controller = <&i2s1>;
 933                                 format = "i2s";
 934                                 //continuous-clock;
 935                                 //bitclock-inversion;
 936                                 //frame-inversion;
 937                                 //bitclock-master;
 938                                 //frame-master;
 939                         };
 940                         dai1 {
 941                                 audio-codec = <&codec>;
 942                                 i2s-controller = <&i2s1>;
 943                                 format = "i2s";
 944                                 //continuous-clock;
 945                                 //bitclock-inversion;
 946                                 //frame-inversion;
 947                                 //bitclock-master;
 948                                 //frame-master;
 949                         };
 950                 };
 951         };
 952         rockchip_suspend {
 953                 rockchip,ctrbits = <
 954                         (0
 955                         |RKPM_CTR_PWR_DMNS
 956                         |RKPM_CTR_GTCLKS
 957                         |RKPM_CTR_PLLS
 958                         |RKPM_CTR_ARMOFF_LPMD
 959                         )
 960                 >;
 961                 rockchip,pmic-suspend_gpios = <
 962                        GPIO1_A1
 963                         >;
 964         };
 965 };