arch/arm/boot/dts/rk312x.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/sensor-dev.h>
   4 #include <dt-bindings/clock/rk_system_status.h>
   5 #include <dt-bindings/rkfb/rk_fb.h>
   6
   7 #include "skeleton.dtsi"
   8 #include "rk312x-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk312x";
  12         rockchip,sram = <&sram>;
  13         interrupt-parent = <&gic>;
  14
  15         aliases {
  16                 serial0 = &uart0;
  17                 serial1 = &uart1;
  18                 serial2 = &uart2;
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 i2c3 = &i2c3;
  23                 lcdc = &lcdc;
  24         //      spi0 = &spi0;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a7";
  34                         reg = <0xf00>;
  35                 };
  36                 cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a7";
  39                         reg = <0xf01>;
  40                 };
  41                 cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a7";
  44                         reg = <0xf02>;
  45                 };
  46                 cpu@3 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a7";
  49                         reg = <0xf03>;
  50                 };
  51         };
  52
  53         gic: interrupt-controller@10139000 {
  54                 compatible = "arm,cortex-a15-gic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <3>;
  57                 #address-cells = <0>;
  58                 reg = <0x10139000 0x1000>,
  59                       <0x1013a000 0x1000>;
  60         };
  61
  62         arm-pmu {
  63                 compatible = "arm,cortex-a7-pmu";
  64                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  65                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  66                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  67                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  68         };
  69
  70         sram: sram@10080000 {
  71                 compatible = "mmio-sram";
  72                 reg = <0x10080000 0x2000>;
  73                 map-exec;
  74         };
  75
  76         timer {
  77                 compatible = "arm,armv7-timer";
  78                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  79                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  80                 clock-frequency = <24000000>;
  81         };
  82
  83         watchdog: wdt@2004c000 {
  84                 compatible = "rockchip,watch dog";
  85                 reg = <0x2004c000 0x100>;
  86         //      clocks = <&clk_gates7 15>;
  87                 clock-names = "pclk_wdt";
  88                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  89                 rockchip,irq = <1>;
  90                 rockchip,timeout = <60>;
  91                 rockchip,atboot = <1>;
  92                 rockchip,debug = <0>;
  93                 status = "disabled";
  94         };
  95
  96         amba {
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 compatible = "arm,amba-bus";
 100                 interrupt-parent = <&gic>;
 101                 ranges;
 102
 103                 pdma: pdma@20078000 {
 104                         compatible = "arm,pl330", "arm,primecell";
 105                         reg = <0x20078000 0x4000>;
 106                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 107                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 108                         #dma-cells = <1>;
 109                 };
 110         };
 111
 112         reset: reset@20000110 {
 113                 compatible = "rockchip,reset";
 114                 reg = <0x20000110 0x24>;
 115                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 116                 #reset-cells = <1>;
 117         };
 118
 119         nandc: nandc@10500000 {
 120                 compatible = "rockchip,rk-nandc";
 121                 reg = <0x10500000 0x4000>;
 122                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 123                 //pinctrl-names = "default";
 124                 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
 125                 nandc_id = <0>;
 126                 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 15>;
 127                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 128         };
 129
 130         nandc0reg: nandc0@10500000 {
 131                 compatible = "rockchip,rk-nandc";
 132                 reg = <0x10500000 0x4000>;
 133         };
 134         uart0: serial@20060000 {
 135                 compatible = "rockchip,serial";
 136                 reg = <0x20060000 0x100>;
 137                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 138                 clock-frequency = <24000000>;
 139         //      clocks = <&clk_uart0>, <&clk_gates8 0>;
 140                 clock-names = "sclk_uart", "pclk_uart";
 141                 reg-shift = <2>;
 142                 reg-io-width = <4>;
 143                 dmas = <&pdma 2>, <&pdma 3>;
 144                 #dma-cells = <2>;
 145                 pinctrl-names = "default";
 146         //      pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 147                 status = "disabled";
 148         };
 149
 150         uart1: serial@20064000 {
 151                 compatible = "rockchip,serial";
 152                 reg = <0x20064000 0x100>;
 153                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 154                 clock-frequency = <24000000>;
 155         //      clocks = <&clk_uart1>, <&clk_gates8 1>;
 156                 clock-names = "sclk_uart", "pclk_uart";
 157                 reg-shift = <2>;
 158                 reg-io-width = <4>;
 159                 dmas = <&pdma 4>, <&pdma 5>;
 160                 #dma-cells = <2>;
 161                 pinctrl-names = "default";
 162         //      pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 163                 status = "disabled";
 164         };
 165
 166         uart2: serial@20068000 {
 167                 compatible = "rockchip,serial";
 168                 reg = <0x20068000 0x100>;
 169                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 170                 clock-frequency = <24000000>;
 171         //      clocks = <&clk_uart2>, <&clk_gates8 2>;
 172                 clock-names = "sclk_uart", "pclk_uart";
 173                 reg-shift = <2>;
 174                 reg-io-width = <4>;
 175                 dmas = <&pdma 6>, <&pdma 7>;
 176                 #dma-cells = <2>;
 177                 pinctrl-names = "default";
 178         //      pinctrl-0 = <&uart2_xfer>;
 179                 status = "disabled";
 180         };
 181
 182         fiq-debugger {
 183                 compatible = "rockchip,fiq-debugger";
 184                 rockchip,serial-id = <2>;
 185                 rockchip,signal-irq = <106>;
 186                 rockchip,wake-irq = <0>;
 187                 status = "disabled";
 188         };
 189
 190         clocks-init{
 191                 compatible = "rockchip,clocks-init";
 192                 rockchip,clocks-init-parent =
 193                         <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll_div2>,
 194                         <&aclk_peri &clk_gpll_div2>, <&clk_uart0_pll &clk_gpll>,
 195                         <&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
 196                         <&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 197                         <&clk_vepu &clk_gpll_div2>, <&clk_vdpu &clk_gpll_div2>,
 198                         <&clk_hevc_core &clk_gpll>, <&aclk_vio0_pre &clk_gpll_div2>,
 199                         <&aclk_vio1_pre &clk_gpll_div2>, <&hclk_vio_pre &clk_gpll_div2>,
 200                         <&sclk_lcdc0 &clk_cpll>, <&clk_gpu_pre &clk_gpll_div2>,
 201                         <&clk_cif_pll &clk_gpll_div2>, <&dclk_ebc &clk_gpll_div2>,
 202                         <&clk_emmc &clk_gpll_div2>, <&clk_sdio &clk_gpll_div2>,
 203                         <&clk_sfc &clk_gpll_div2>, <&clk_sdmmc0 &clk_gpll_div2>,
 204                         <&clk_tsp &clk_gpll_div2>, <&clk_nandc &clk_gpll_div2>,
 205                         <&clk_mac_pll &clk_cpll>;
 206                 rockchip,clocks-init-rate =
 207                         <&clk_core 816000000>, <&clk_gpll 594000000>,
 208                         <&clk_cpll 400000000>, <&aclk_cpu 300000000>,
 209                         <&hclk_cpu_pre 150000000>, <&pclk_cpu_pre 75000000>,
 210                         <&aclk_peri 300000000>, <&hclk_peri_pre 150000000>,
 211                         <&pclk_peri_pre 75000000>, <&clk_gpu_pre 300000000>,
 212                         <&aclk_vio0_pre 300000000>, <&hclk_vio_pre 150000000>,
 213                         <&aclk_vio1_pre 300000000>, <&clk_vepu 300000000>,
 214                         <&clk_vdpu 300000000>, <&clk_hevc_core 200000000>,
 215                         <&clk_mac_ref 50000000>;
 216         /*      rockchip,clocks-uboot-has-init =
 217                         <&aclk_vio1>;*/
 218         };
 219         gpu {
 220                 compatible = "arm,mali400";
 221                 reg = <0x10091000 0x200>,
 222                       <0x10090000 0x100>,
 223                       <0x10093000 0x100>,
 224                       <0x10098000 0x1100>,
 225                       <0x10094000 0x100>,
 226                       <0x1009A000 0x1100>,
 227                       <0x10095000 0x100>;
 228
 229                 reg-names = "Mali_L2",
 230                             "Mali_GP",
 231                             "Mali_GP_MMU",
 232                             "Mali_PP0",
 233                             "Mali_PP0_MMU",
 234                             "Mali_PP1",
 235                             "Mali_PP1_MMU";
 236
 237                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 241                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 243
 244                 interrupt-names = "Mali_GP_IRQ",
 245                                   "Mali_GP_MMU_IRQ",
 246                                   "Mali_PP0_IRQ",
 247                                   "Mali_PP0_MMU_IRQ",
 248                                   "Mali_PP1_IRQ",
 249                                   "Mali_PP1_MMU_IRQ";
 250           };
 251
 252         clocks-enable {
 253                 compatible = "rockchip,clocks-enable";
 254                 clocks =
 255                                 /*PD_CORE*/
 256                                 <&clk_gates0 6>,<&clk_gates0 0>,
 257                                 <&clk_gates0 7>,
 258
 259                                 /*PD_CPU*/
 260                                 <&clk_gates0 1>, <&clk_gates0 3>,
 261                                 <&clk_gates0 4>, <&clk_gates0 5>,
 262                                 <&clk_gates0 12>,
 263
 264                                 /*TIMER*/
 265                                 <&clk_gates10 3>, <&clk_gates10 4>,
 266                                 <&clk_gates10 5>, <&clk_gates10 6>,
 267                                 <&clk_gates10 7>, <&clk_gates10 8>,
 268
 269                                 /*PD_PERI*/
 270                                 <&clk_gates2 0>, <&hclk_peri_pre>,
 271                                 <&pclk_peri_pre>, <&clk_gates2 1>,
 272
 273                                 /*aclk_cpu_pre*/
 274                                 <&clk_gates4 12>,/*aclk_intmem*/
 275                                 <&clk_gates4 10>,/*aclk_strc_sys*/
 276
 277                                 /*hclk_cpu_pre*/
 278                                 <&clk_gates5 6>,/*hclk_rom*/
 279                                 <&clk_gates3 5>,/*hclk_crypto*/
 280
 281                                 /*pclk_cpu_pre*/
 282                                 <&clk_gates5 4>,/*pclk_grf*/
 283                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
 284                                 <&clk_gates5 14>,/*pclk_acodec*/
 285                                 <&clk_gates3 8>,/*pclk_hdmi*/
 286
 287                                 /*aclk_peri_pre*/
 288                                 <&clk_gates10 10>,/*aclk_gmac*/
 289                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
 290                                 <&clk_gates5 1>,/*aclk_dmac2*/
 291                                 <&clk_gates9 15>,/*aclk_peri_niu*/
 292                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
 293
 294                                 /*hclk_peri_pre*/
 295                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
 296                                 <&clk_gates9 13>,/*hclk_usb_peri*/
 297                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
 298
 299                                 /*pclk_peri_pre*/
 300                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
 301
 302                                 /*hclk_vio_pre*/
 303                                 <&clk_gates6 12>,/*hclk_vio_niu*/
 304                                 <&clk_gates6 1>,/*hclk_lcdc*/
 305
 306                                 /*aclk_vio0_pre*/
 307                                 <&clk_gates6 13>,/*aclk_vio*/
 308                                 <&clk_gates6 0>,/*aclk_lcdc*/
 309
 310                                 /*aclk_vio1_pre*/
 311                                 <&clk_gates9 10>,/*aclk_vio1_niu*/
 312
 313                                 /*UART*/
 314                                 <&clk_gates1 12>,
 315                                 <&clk_gates1 13>,
 316                                 <&clk_gates8 2>,/*pclk_uart2*/
 317
 318                                 <&clk_gpu_pre>,
 319
 320                                 /*jtag*/
 321                                 <&clk_gates1 3>,/*clk_jtag*/
 322
 323                                 /*pmu*/
 324                                 <&clk_gates1 0>;/*pclk_pmu_pre*/
 325         };
 326
 327         i2c0: i2c@20070000 {
 328                 compatible = "rockchip,rk30-i2c";
 329                 reg = <0x20070000 0x1000>;
 330                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333         //      pinctrl-names = "default", "gpio";
 334         //      pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 335         //      pinctrl-1 = <&i2c0_gpio>;
 336         //      gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 337         //      clocks = <&clk_gates8 4>;
 338                 rockchip,check-idle = <1>;
 339                 status = "disabled";
 340         };
 341
 342         i2c1: i2c@20054000 {
 343                 compatible = "rockchip,rk30-i2c";
 344                 reg = <0x20054000 0x1000>;
 345                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348         //      pinctrl-names = "default", "gpio";
 349         //      pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 350         //      pinctrl-1 = <&i2c1_gpio>;
 351         //      gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 352         //      clocks = <&clk_gates8 5>;
 353                 rockchip,check-idle = <1>;
 354                 status = "disabled";
 355         };
 356
 357         i2c2: i2c@20058000 {
 358                 compatible = "rockchip,rk30-i2c";
 359                 reg = <0x20058000 0x1000>;
 360                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363         //      pinctrl-names = "default", "gpio";
 364         //      pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 365         //      pinctrl-1 = <&i2c2_gpio>;
 366         //      gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 367         //      clocks = <&clk_gates8 6>;
 368                 rockchip,check-idle = <1>;
 369                 status = "disabled";
 370         };
 371
 372         i2c3: i2c@2005c000 {
 373                 compatible = "rockchip,rk30-i2c";
 374                 reg = <0x2005C000 0x1000>;
 375                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378         //      pinctrl-names = "default", "gpio";
 379         //      pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 380         //      pinctrl-1 = <&i2c2_gpio>;
 381         //      gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 382         //      clocks = <&clk_gates8 6>;
 383                 rockchip,check-idle = <1>;
 384                 status = "disabled";
 385         };
 386
 387         i2s0: i2s@10220000 {
 388                 compatible = "rockchip-i2s";
 389                 reg = <0x10220000 0x1000>;
 390                 i2s-id = <0>;
 391                 clocks = <&clk_i2s_2ch>, <&clk_i2s_2ch_out>, <&clk_gates7 2>;
 392                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 393                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 394                 dmas = <&pdma 0>, <&pdma 1>;
 395                 //#dma-cells = <2>;
 396                 dma-names = "tx", "rx";
 397                 //pinctrl-names = "default", "sleep";
 398                 //pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 399                 //pinctrl-1 = <&i2s0_gpio>;
 400         };
 401
 402         i2s1: i2s@10200000 {
 403                 compatible = "rockchip-i2s";
 404                 reg = <0x10200000 0x1000>;
 405                 i2s-id = <1>;
 406                 clocks = <&clk_i2s_8ch>, <&clk_gates7 4>;
 407                 clock-names = "i2s_clk", "i2s_hclk";
 408                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 409                 dmas = <&pdma 14>, <&pdma 15>;
 410                 //#dma-cells = <2>;
 411                 dma-names = "tx", "rx";
 412         };
 413
 414         spdif: spdif@10204000 {
 415                 compatible = "rockchip-spdif";
 416                 reg = <0x10204000 0x1000>;
 417                 clocks = <&clk_spdif>, <&clk_gates10 8>;
 418                 clock-names = "spdif_8ch_mclk", "spdif_hclk";
 419                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 420                 dmas = <&pdma 13>;
 421                 //#dma-cells = <1>;
 422                 dma-names = "tx";
 423                 //pinctrl-names = "default";
 424                 //pinctrl-0 = <&spdif_tx>;
 425         };
 426
 427         dsihost0: mipi@10110000{
 428                 compatible = "rockchip,rk32-dsi";
 429                 rockchip,prop = <0>;
 430                 reg = <0x10110000 0x4000>, <0x20038000 0x4000>;
 431                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 432                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 433                 clocks = <&clk_gates2 15>, <&clk_gates5 0> ;//, <&pd_mipidsi>;
 434                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi";//, "pd_mipi_dsi";
 435                 status = "okay";
 436         };
 437
 438         emmc: rksdmmc@1021c000 {
 439                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 440                 reg = <0x1021c000 0x4000>;
 441                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 442                 #address-cells = <1>;
 443                 #size-cells = <0>;
 444                 //pinctrl-names = "default",,"suspend";
 445                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 446                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 447                 clock-names = "clk_mmc", "hclk_mmc";
 448                 dmas = <&pdma 12>;
 449                 dma-names = "dw_mci";
 450                 num-slots = <1>;
 451                 fifo-depth = <0x100>;
 452                 bus-width = <8>;
 453         };
 454
 455
 456         sdmmc: rksdmmc@10214000 {
 457                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 458                 reg = <0x10214000 0x4000>;
 459                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 pinctrl-names = "default", "idle";
 463                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 464                 pinctrl-1 = <&sdmmc0_gpio>;
 465                 //cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 466                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 467                 clock-names = "clk_mmc", "hclk_mmc";
 468                 dmas = <&pdma 10>;
 469                 dma-names = "dw_mci";
 470                 num-slots = <1>;
 471                 fifo-depth = <0x100>;
 472                 bus-width = <4>;
 473         };
 474
 475         sdio: rksdmmc@10218000 {
 476                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 477                 reg = <0x10218000 0x4000>;
 478                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 479                 #address-cells = <1>;
 480                 #size-cells = <0>;
 481                 pinctrl-names = "default","idle";
 482                 pinctrl-0 = <&sdio0_pwren &sdio0_cmd>;
 483                 pinctrl-1 = <&sdio0_gpio>;
 484                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 485                 clock-names = "clk_mmc", "hclk_mmc";
 486                 dmas = <&pdma 11>;
 487                 dma-names = "dw_mci";
 488                 num-slots = <1>;
 489                 fifo-depth = <0x100>;
 490                 bus-width = <4>;
 491         };
 492
 493         adc: adc@2006c000 {
 494                 compatible = "rockchip,saradc";
 495                 reg = <0x2006c000 0x100>;
 496                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 497                 #io-channel-cells = <1>;
 498                 io-channel-ranges;
 499                 rockchip,adc-vref = <1800>;
 500                 clock-frequency = <1000000>;
 501                 //clocks = <&clk_saradc>, <&clk_gates7 1>;
 502                 //clock-names = "saradc", "pclk_saradc";
 503                 status = "disabled";
 504         };
 505
 506         pwm0: pwm@20050000 {
 507                 compatible = "rockchip,rk-pwm";
 508                 reg = <0x20050000 0x10>;
 509                 #pwm-cells = <2>;
 510                 pinctrl-names = "default";
 511                 pinctrl-0 = <&pwm0_pin>;
 512                 clocks = <&clk_gates7 10>;
 513                 clock-names = "pclk_pwm";
 514                 status = "disabled";
 515         };
 516
 517         pwm1: pwm@20050010 {
 518                 compatible = "rockchip,rk-pwm";
 519                 reg = <0x20050010 0x10>;
 520                 #pwm-cells = <2>;
 521                 pinctrl-names = "default";
 522                 pinctrl-0 = <&pwm1_pin>;
 523                 clocks = <&clk_gates7 10>;
 524                 clock-names = "pclk_pwm";
 525                 status = "disabled";
 526         };
 527
 528         pwm2: pwm@20050020 {
 529                 compatible = "rockchip,rk-pwm";
 530                 reg = <0x20050020 0x10>;
 531                 #pwm-cells = <2>;
 532                 pinctrl-names = "default";
 533                 pinctrl-0 = <&pwm2_pin>;
 534                 clocks = <&clk_gates7 10>;
 535                 clock-names = "pclk_pwm";
 536                 status = "disabled";
 537         };
 538
 539         pwm3: pwm@20050030 {
 540                 compatible = "rockchip,rk-pwm";
 541                 reg = <0x20050030 0x10>;
 542                 #pwm-cells = <2>;
 543                 pinctrl-names = "default";
 544                 pinctrl-0 = <&pwm3_pin>;
 545                 clocks = <&clk_gates7 10>;
 546                 clock-names = "pclk_pwm";
 547                 status = "disabled";
 548         };
 549
 550         dwc_control_usb: dwc-control-usb@20008000 {
 551                 compatible = "rockchip,rk3126-dwc-control-usb";
 552                 reg = <0x20008000 0x4>;
 553                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 554                 interrupt-names = "otg_bvalid";
 555                 clocks = <&clk_gates9 13>;
 556                 clock-names = "hclk_usb_peri";
 557                 rockchip,remote_wakeup;
 558                 rockchip,usb_irq_wakeup;
 559                 resets = <&reset RK3128_RST_USBPOR>;
 560                 reset-names = "usbphy_por";
 561                 usb_bc{
 562                         compatible = "inno,phy";
 563                         regbase = &dwc_control_usb;
 564                 };
 565         };
 566
 567         usb0: usb@10180000 {
 568                 compatible = "rockchip,rk3126_usb20_otg";
 569                 reg = <0x10180000 0x40000>;
 570                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 571                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 572                 clock-names = "clk_usbphy0", "hclk_usb0";
 573                 resets = <&reset RK3128_RST_USBOTG0>, <&reset RK3128_RST_USBOTG0>,
 574                                 <&reset RK3128_RST_OTGC0>;
 575                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
 576                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 577                 rockchip,usb-mode = <0>;
 578         };
 579
 580         usb1: usb@101c0000 {
 581                 compatible = "rockchip,rk3126_usb20_host";
 582                 reg = <0x101c0000 0x40000>;
 583                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 584                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 585                 clock-names = "clk_usbphy1", "hclk_usb1";
 586                 resets = <&reset RK3128_RST_USBOTG1>, <&reset RK3128_RST_UTMI1>,
 587                                 <&reset RK3128_RST_OTGC1>;
 588                 reset-names = "host_ahb", "host_phy", "host_controller";
 589         };
 590
 591         fb: fb{
 592                 compatible = "rockchip,rk-fb";
 593                 rockchip,disp-mode = <ONE_DUAL>;
 594         };
 595
 596         rk_screen: rk_screen{
 597                 compatible = "rockchip,screen";
 598         };
 599
 600         lvds: lvds@20038000 {
 601                 compatible = "rockchip,rk31xx-lvds";
 602                 reg = <0x20038000 0x4000>;
 603                 clocks = <&clk_gates5 0>;
 604                 clock-names = "pclk_lvds";
 605         };
 606
 607         lcdc: lcdc@1010e000 {
 608                 compatible = "rockchip,rk312x-lcdc";
 609                 rockchip,prop = <PRMRY>;
 610                 reg = <0x1010e000 0x2000>;
 611                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 612                 pinctrl-names = "default", "gpio";
 613                 pinctrl-0 = <&lcdc0_lcdc>;
 614                 pinctrl-1 = <&lcdc0_gpio>;
 615                 clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>;
 616                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk";
 617                 rockchip,iommu-enabled = <1>;
 618                 status = "disabled";
 619         };
 620
 621         hdmi: hdmi@20034000 {
 622                 compatible = "rockchip,rk3036-hdmi";
 623                 reg = <0x20034000 0x4000>;
 624                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 625                 rockchip,hdmi_lcdc_source = <0>;
 626                 pinctrl-names = "default", "gpio";
 627                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 628                 pinctrl-1 = <&hdmi_gpio>;
 629                 clocks = <&clk_gates3 8>;
 630                 clock-names = "pclk_hdmi";
 631                 status = "disabled";
 632         };
 633
 634         vpu: vpu_service@10104000 {
 635                 compatible = "vpu_service";
 636                 reg = <0x10104000 0x800>;
 637                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 638                 interrupt-names = "irq_enc", "irq_dec";
 639                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 640                 clock-names = "aclk_vcodec", "hclk_vcodec";
 641                 name = "vpu_service";
 642                 status = "disabled";
 643         };
 644
 645         hevc: hevc_service@10104000 {
 646                 compatible = "rockchip,hevc_service";
 647                 reg = <0x10104000 0x400>;
 648                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 649                 interrupt-names = "irq_dec";
 650                 clocks = <&clk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>;
 651                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
 652                 name = "hevc_service";
 653                 status = "disabled";
 654         };
 655
 656         iep: iep@10108000 {
 657                 compatible = "rockchip,iep";
 658                 reg = <0x10108000 0x800>;
 659                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 660                 clocks = <&clk_gates9 8>, <&clk_gates9 7>;
 661                 clock-names = "aclk_iep", "hclk_iep";
 662                 status = "okay";
 663         };
 664
 665         vop_mmu {
 666                 dbgname = "vop";
 667                 compatible = "iommu,vop_mmu";
 668                 reg = <0x1010e300 0x100>;
 669                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 670                 interrupt-names = "vop_mmu";
 671           };
 672
 673           hevc_mmu {
 674                 dbgname = "hevc";
 675                 compatible = "iommu,hevc_mmu";
 676                 reg = <0x10104440 0x100>,
 677                       <0x10104480 0x100>;
 678                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 679                 interrupt-names = "hevc_mmu";
 680           };
 681
 682           vpu_mmu {
 683                 dbgname = "vpu";
 684                 compatible = "iommu,vpu_mmu";
 685                 reg = <0x10104800 0x100>;
 686                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 687                 interrupt-names = "vpu_mmu";
 688           };
 689
 690           iep_mmu {
 691                 dbgname = "iep";
 692                 compatible = "iommu,iep_mmu";
 693                 reg = <0x10108800 0x100>;
 694                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 695                 interrupt-names = "iep_mmu";
 696           };
 697
 698           dvfs {
 699                 temp-limit-enable = <0>;
 700                 target-temp = <80>;
 701
 702                 vd_arm: vd_arm {
 703                         regulator_name = "vdd_arm";
 704                         pd_core {
 705                                 clk_core_dvfs_table: clk_core {
 706                                         operating-points = <
 707                                                 /* KHz    uV */
 708                                                 312000 1100000
 709                                                 504000 1100000
 710                                                 816000 1100000
 711                                                 1008000 1100000
 712                                                 >;
 713                                         temp-channel = <1>;
 714                                         normal-temp-limit = <
 715                                         /*delta-temp    delta-freq*/
 716                                                 3       96000
 717                                                 6       144000
 718                                                 9       192000
 719                                                 15      384000
 720                                                 >;
 721                                         performance-temp-limit = <
 722                                                 /*temp    freq*/
 723                                                 110     816000
 724                                                 >;
 725                                         status = "okay";
 726                                         regu-mode-table = <
 727                                                 /*freq     mode*/
 728                                                 1008000    4
 729                                                 0          3
 730                                         >;
 731                                         regu-mode-en = <0>;
 732                                 };
 733                         };
 734                 };
 735
 736                 vd_logic: vd_logic {
 737                         regulator_name = "vdd_logic";
 738                         pd_ddr {
 739                                 clk_ddr_dvfs_table: clk_ddr {
 740                                         operating-points = <
 741                                                 /* KHz    uV */
 742                                                 200000 1200000
 743                                                 300000 1200000
 744                                                 400000 1200000
 745                                                 >;
 746                                         status = "disabled";
 747                                 };
 748                         };
 749
 750                         pd_gpu {
 751                                 clk_gpu_dvfs_table: clk_gpu {
 752                                         operating-points = <
 753                                                 /* KHz    uV */
 754                                                 200000 1200000
 755                                                 300000 1200000
 756                                                 400000 1200000
 757                                                 >;
 758                                         status = "okay";
 759                                         regu-mode-table = <
 760                                                 /*freq     mode*/
 761                                                 200000     4
 762                                                 0          3
 763                                         >;
 764                                         regu-mode-en = <0>;
 765                                 };
 766                         };
 767                 };
 768         };
 769         ion {
 770                 compatible = "rockchip,ion";
 771                 #address-cells = <1>;
 772                 #size-cells = <0>;
 773
 774                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 775                         compatible = "rockchip,ion-reserve";
 776                         rockchip,ion_heap = <1>;
 777                         reg = <0x00000000 0x10000000>; /* 256MB */
 778                 };
 779                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 780                         rockchip,ion_heap = <3>;
 781                 };
 782         };
 783 };