1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-pm.h>
3 #include <dt-bindings/sensor-dev.h>
4 #include <dt-bindings/clock/rk_system_status.h>
5 #include <dt-bindings/rkfb/rk_fb.h>
7 #include "skeleton.dtsi"
8 #include "rk312x-clocks.dtsi"
9 #include "rk312x-pinctrl.dtsi"
12 compatible = "rockchip,rk312x";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
34 compatible = "arm,cortex-a7";
39 compatible = "arm,cortex-a7";
44 compatible = "arm,cortex-a7";
49 compatible = "arm,cortex-a7";
54 gic: interrupt-controller@10139000 {
55 compatible = "arm,cortex-a15-gic";
57 #interrupt-cells = <3>;
59 reg = <0x10139000 0x1000>,
64 compatible = "arm,cortex-a7-pmu";
65 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
71 cpu_axi_bus: cpu_axi_bus {
72 compatible = "rockchip,cpu_axi_bus";
83 reg = <0x10128080 0x20>;
86 reg = <0x1012a000 0x20>;
87 rockchip,priority = <3 2>;
90 reg = <0x1012c000 0x20>;
93 reg = <0x1012d000 0x20>;
96 reg = <0x1012e000 0x20>;
99 reg = <0x1012f000 0x20>;
102 reg = <0x1012f080 0x20>;
105 reg = <0x1012f100 0x20>;
108 reg = <0x1012f180 0x20>;
109 rockchip,priority = <3 3>;
112 reg = <0x1012f200 0x20>;
117 #address-cells = <1>;
122 reg = <0x10128000 0x20>;
123 rockchip,read-latency = <0x3f>;
128 sram: sram@10080000 {
129 compatible = "mmio-sram";
130 reg = <0x10080000 0x2000>;
135 compatible = "arm,armv7-timer";
136 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
137 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
138 clock-frequency = <24000000>;
142 compatible = "rockchip,timer";
143 reg = <0x20044000 0x20>;
144 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
145 rockchip,broadcast = <1>;
148 watchdog: wdt@2004c000 {
149 compatible = "rockchip,watch dog";
150 reg = <0x2004c000 0x100>;
151 // clocks = <&clk_gates7 15>;
152 clock-names = "pclk_wdt";
153 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
155 rockchip,timeout = <60>;
156 rockchip,atboot = <1>;
157 rockchip,debug = <0>;
162 #address-cells = <1>;
164 compatible = "arm,amba-bus";
165 interrupt-parent = <&gic>;
168 pdma: pdma@20078000 {
169 compatible = "arm,pl330", "arm,primecell";
170 reg = <0x20078000 0x4000>;
171 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
177 reset: reset@20000110 {
178 compatible = "rockchip,reset";
179 reg = <0x20000110 0x24>;
180 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
184 nandc: nandc@10500000 {
185 compatible = "rockchip,rk-nandc";
186 reg = <0x10500000 0x4000>;
187 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
188 //pinctrl-names = "default";
189 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
191 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 15>;
192 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
195 nandc0reg: nandc0@10500000 {
196 compatible = "rockchip,rk-nandc";
197 reg = <0x10500000 0x4000>;
199 uart0: serial@20060000 {
200 compatible = "rockchip,serial";
201 reg = <0x20060000 0x100>;
202 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
203 clock-frequency = <24000000>;
204 clocks = <&clk_uart0>, <&clk_gates8 0>;
205 clock-names = "sclk_uart", "pclk_uart";
208 dmas = <&pdma 2>, <&pdma 3>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
215 uart1: serial@20064000 {
216 compatible = "rockchip,serial";
217 reg = <0x20064000 0x100>;
218 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
219 clock-frequency = <24000000>;
220 clocks = <&clk_uart1>, <&clk_gates8 1>;
221 clock-names = "sclk_uart", "pclk_uart";
224 dmas = <&pdma 4>, <&pdma 5>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
231 uart2: serial@20068000 {
232 compatible = "rockchip,serial";
233 reg = <0x20068000 0x100>;
234 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
235 clock-frequency = <24000000>;
236 clocks = <&clk_uart2>, <&clk_gates8 2>;
237 clock-names = "sclk_uart", "pclk_uart";
240 dmas = <&pdma 6>, <&pdma 7>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&uart2_xfer>;
248 compatible = "rockchip,rk312x-gmac";
249 reg = <0x2008c000 0x4000>;
250 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; /*irq=88*/
251 interrupt-names = "macirq";
252 clocks = <&clk_mac_ref>, <&clk_gates2 6>,
253 <&clk_gates2 7>, <&clk_gates2 4>,
256 clock-names = "clk_mac", "mac_clk_rx",
257 "mac_clk_tx", "clk_mac_ref",
261 pinctrl-names = "default";
262 pinctrl-0 = <&gmac_rxdv &gmac_txclk &gmac_crs &gmac_rxclk &gmac_mdio &gmac_txen &gmac_clk &gmac_rxer &gmac_rxd1 &gmac_rxd0 &gmac_txd1 &gmac_txd0 &gmac_rxd3 &gmac_rxd2 &gmac_txd2 &gmac_txd3 &gmac_col_gpio &gmac_mdc>;
266 compatible = "rockchip,fiq-debugger";
267 rockchip,serial-id = <2>;
268 rockchip,signal-irq = <106>;
269 rockchip,wake-irq = <0>;
274 compatible = "rockchip,clocks-init";
275 rockchip,clocks-init-parent =
276 <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll_div2>,
277 <&aclk_peri &clk_gpll_div2>, <&clk_uart0_pll &clk_gpll>,
278 <&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
279 <&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
280 <&clk_vepu &clk_gpll_div2>, <&clk_vdpu &clk_gpll_div2>,
281 <&clk_hevc_core &clk_gpll>, <&aclk_vio0_pre &clk_gpll_div2>,
282 <&aclk_vio1_pre &clk_gpll_div2>, <&hclk_vio_pre &clk_gpll_div2>,
283 <&sclk_lcdc0 &clk_cpll>, <&clk_gpu &clk_gpll_div2>,
284 <&clk_cif_pll &clk_gpll_div2>, <&dclk_ebc &clk_gpll_div2>,
285 <&clk_emmc &clk_gpll_div2>, <&clk_sdio &clk_gpll_div2>,
286 <&clk_sfc &clk_gpll_div2>, <&clk_sdmmc0 &clk_gpll_div2>,
287 <&clk_tsp &clk_gpll_div2>, <&clk_nandc &clk_gpll_div2>,
288 <&clk_mac_pll &clk_cpll>;
289 rockchip,clocks-init-rate =
290 <&clk_core 816000000>, <&clk_gpll 594000000>,
291 <&clk_cpll 400000000>, <&aclk_cpu 300000000>,
292 <&hclk_cpu_pre 150000000>, <&pclk_cpu_pre 75000000>,
293 <&aclk_peri 300000000>, <&hclk_peri_pre 150000000>,
294 <&pclk_peri_pre 75000000>, <&clk_gpu 300000000>,
295 <&aclk_vio0_pre 300000000>, <&hclk_vio_pre 150000000>,
296 <&aclk_vio1_pre 300000000>, <&clk_vepu 300000000>,
297 <&clk_vdpu 300000000>, <&clk_hevc_core 200000000>,
298 <&clk_mac_ref 125000000>;
299 /* rockchip,clocks-uboot-has-init =
303 compatible = "arm,mali400";
304 reg = <0x10091000 0x200>,
312 reg-names = "Mali_L2",
320 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
327 interrupt-names = "Mali_GP_IRQ",
336 compatible = "rockchip,clocks-enable";
339 <&clk_gates0 6>,<&clk_gates0 0>,
343 <&clk_gates0 1>, <&clk_gates0 3>,
344 <&clk_gates0 4>, <&clk_gates0 5>,
348 <&clk_gates10 3>, <&clk_gates10 4>,
349 <&clk_gates10 5>, <&clk_gates10 6>,
350 <&clk_gates10 7>, <&clk_gates10 8>,
353 <&clk_gates2 0>, <&hclk_peri_pre>,
354 <&pclk_peri_pre>, <&clk_gates2 1>,
357 <&clk_gates4 12>,/*aclk_intmem*/
358 <&clk_gates4 10>,/*aclk_strc_sys*/
361 <&clk_gates5 6>,/*hclk_rom*/
362 <&clk_gates3 5>,/*hclk_crypto*/
365 <&clk_gates5 4>,/*pclk_grf*/
366 <&clk_gates5 7>,/*pclk_ddrupctl*/
367 <&clk_gates5 14>,/*pclk_acodec*/
368 <&clk_gates3 8>,/*pclk_hdmi*/
371 <&clk_gates10 10>,/*aclk_gmac*/
372 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
373 <&clk_gates5 1>,/*aclk_dmac2*/
374 <&clk_gates9 15>,/*aclk_peri_niu*/
375 <&clk_gates4 2>,/*aclk_cpu_peri*/
378 <&clk_gates4 0>,/*hclk_peri_matrix*/
379 <&clk_gates9 13>,/*hclk_usb_peri*/
380 <&clk_gates9 14>,/*hclk_peri_arbi*/
383 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
386 <&clk_gates6 12>,/*hclk_vio_niu*/
387 <&clk_gates6 1>,/*hclk_lcdc*/
390 <&clk_gates6 13>,/*aclk_vio*/
391 <&clk_gates6 0>,/*aclk_lcdc*/
394 <&clk_gates9 10>,/*aclk_vio1_niu*/
399 <&clk_gates8 2>,/*pclk_uart2*/
404 <&clk_gates1 3>,/*clk_jtag*/
407 <&clk_gates1 0>;/*pclk_pmu_pre*/
411 compatible = "rockchip,rk30-i2c";
412 reg = <0x20072000 0x1000>;
413 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
414 #address-cells = <1>;
416 pinctrl-names = "default", "gpio";
417 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
418 pinctrl-1 = <&i2c0_gpio>;
419 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
420 clocks = <&clk_gates8 4>;
421 rockchip,check-idle = <1>;
426 compatible = "rockchip,rk30-i2c";
427 reg = <0x20056000 0x1000>;
428 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
429 #address-cells = <1>;
431 pinctrl-names = "default", "gpio";
432 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
433 pinctrl-1 = <&i2c1_gpio>;
434 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
435 clocks = <&clk_gates8 5>;
436 rockchip,check-idle = <1>;
441 compatible = "rockchip,rk30-i2c";
442 reg = <0x2005a000 0x1000>;
443 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
444 #address-cells = <1>;
446 pinctrl-names = "default", "gpio";
447 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
448 pinctrl-1 = <&i2c2_gpio>;
449 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
450 clocks = <&clk_gates8 6>;
451 rockchip,check-idle = <1>;
456 compatible = "rockchip,rk30-i2c";
457 reg = <0x2005e000 0x1000>;
458 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
459 #address-cells = <1>;
461 pinctrl-names = "default", "gpio";
462 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
463 pinctrl-1 = <&i2c3_gpio>;
464 gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>;
465 clocks = <&clk_gates8 7>;
466 rockchip,check-idle = <1>;
471 compatible = "rockchip-i2s";
472 reg = <0x10220000 0x1000>;
474 clocks = <&clk_i2s_2ch>, <&clk_i2s_2ch_out>, <&clk_gates7 2>;
475 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
476 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
477 dmas = <&pdma 0>, <&pdma 1>;
479 dma-names = "tx", "rx";
480 //pinctrl-names = "default", "sleep";
481 //pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
482 //pinctrl-1 = <&i2s0_gpio>;
486 compatible = "rockchip-i2s";
487 reg = <0x10200000 0x1000>;
489 clocks = <&clk_i2s_8ch>, <&clk_gates7 4>;
490 clock-names = "i2s_clk", "i2s_hclk";
491 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
492 dmas = <&pdma 14>, <&pdma 15>;
494 dma-names = "tx", "rx";
497 spdif: spdif@10204000 {
498 compatible = "rockchip-spdif";
499 reg = <0x10204000 0x1000>;
500 clocks = <&clk_spdif>, <&clk_gates10 9>;
501 clock-names = "spdif_mclk", "spdif_hclk";
502 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
506 pinctrl-names = "default";
507 pinctrl-0 = <&spdif_tx>;
510 dsihost0: mipi@10110000{
511 compatible = "rockchip,rk32-dsi";
513 reg = <0x10110000 0x4000>, <0x20038000 0x4000>;
514 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
515 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&clk_gates2 15>, <&clk_gates5 0> ;//, <&pd_mipidsi>;
517 clock-names = "clk_mipi_24m", "pclk_mipi_dsi";//, "pd_mipi_dsi";
521 emmc: rksdmmc@1021c000 {
522 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
523 reg = <0x1021c000 0x4000>;
524 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
525 #address-cells = <1>;
527 //pinctrl-names = "default",,"suspend";
528 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
529 clocks = <&clk_emmc>, <&clk_gates7 0>;
530 clock-names = "clk_mmc", "hclk_mmc";
532 dma-names = "dw_mci";
534 fifo-depth = <0x100>;
539 sdmmc: rksdmmc@10214000 {
540 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
541 reg = <0x10214000 0x4000>;
542 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
543 #address-cells = <1>;
545 pinctrl-names = "default", "idle";
546 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
547 pinctrl-1 = <&sdmmc0_gpio>;
548 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
549 clock-names = "clk_mmc", "hclk_mmc";
551 dma-names = "dw_mci";
553 fifo-depth = <0x100>;
557 sdio: rksdmmc@10218000 {
558 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
559 reg = <0x10218000 0x4000>;
560 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
561 #address-cells = <1>;
563 pinctrl-names = "default","idle";
564 pinctrl-0 = <&sdio0_pwren &sdio0_cmd &sdio0_clk &sdio0_bus4>;
565 pinctrl-1 = <&sdio0_gpio>;
566 clocks = <&clk_sdio>, <&clk_gates5 11>;
567 clock-names = "clk_mmc", "hclk_mmc";
569 dma-names = "dw_mci";
571 fifo-depth = <0x100>;
576 compatible = "rockchip,saradc";
577 reg = <0x2006c000 0x100>;
578 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
579 #io-channel-cells = <1>;
581 rockchip,adc-vref = <1800>;
582 clock-frequency = <1000000>;
583 clocks = <&clk_saradc>, <&clk_gates7 14>;
584 clock-names = "saradc", "pclk_saradc";
589 compatible = "rockchip,rk-pwm";
590 reg = <0x20050000 0x10>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&pwm0_pin>;
594 clocks = <&clk_gates7 10>;
595 clock-names = "pclk_pwm";
600 compatible = "rockchip,rk-pwm";
601 reg = <0x20050010 0x10>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&pwm1_pin>;
605 clocks = <&clk_gates7 10>;
606 clock-names = "pclk_pwm";
611 compatible = "rockchip,rk-pwm";
612 reg = <0x20050020 0x10>;
614 pinctrl-names = "default";
615 pinctrl-0 = <&pwm2_pin>;
616 clocks = <&clk_gates7 10>;
617 clock-names = "pclk_pwm";
622 compatible = "rockchip,rk-pwm";
623 reg = <0x20050030 0x10>;
625 pinctrl-names = "default";
626 pinctrl-0 = <&pwm3_pin>;
627 clocks = <&clk_gates7 10>;
628 clock-names = "pclk_pwm";
632 remotectl: pwm@20050030 {
633 compatible = "rockchip,remotectl-pwm";
634 reg = <0x20050030 0x10>;
636 pinctrl-names = "default";
637 pinctrl-0 = <&pwm3_pin>;
638 clocks = <&clk_gates7 10>;
639 clock-names = "pclk_pwm";
640 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
643 dwc_control_usb: dwc-control-usb@20008000 {
644 compatible = "rockchip,rk3126-dwc-control-usb";
645 reg = <0x20008000 0x4>;
646 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
647 interrupt-names = "otg_bvalid";
648 clocks = <&clk_gates9 13>;
649 clock-names = "hclk_usb_peri";
650 rockchip,remote_wakeup;
651 rockchip,usb_irq_wakeup;
652 resets = <&reset RK3128_RST_USBPOR>;
653 reset-names = "usbphy_por";
655 compatible = "inno,phy";
656 regbase = &dwc_control_usb;
661 compatible = "rockchip,rk3126_usb20_otg";
662 reg = <0x10180000 0x40000>;
663 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
665 clock-names = "clk_usbphy0", "hclk_usb0";
666 resets = <&reset RK3128_RST_USBOTG0>, <&reset RK3128_RST_USBOTG0>,
667 <&reset RK3128_RST_OTGC0>;
668 reset-names = "otg_ahb", "otg_phy", "otg_controller";
669 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
670 rockchip,usb-mode = <0>;
674 compatible = "rockchip,rk3126_usb20_host";
675 reg = <0x101c0000 0x40000>;
676 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
678 clock-names = "clk_usbphy1", "hclk_usb1";
679 resets = <&reset RK3128_RST_USBOTG1>, <&reset RK3128_RST_UTMI1>,
680 <&reset RK3128_RST_OTGC1>;
681 reset-names = "host_ahb", "host_phy", "host_controller";
685 compatible = "rockchip,rk-fb";
686 rockchip,disp-mode = <ONE_DUAL>;
689 rk_screen: rk_screen{
690 compatible = "rockchip,screen";
693 lvds: lvds@20038000 {
694 compatible = "rockchip,rk31xx-lvds";
695 reg = <0x20038000 0x4000>;
696 clocks = <&clk_gates5 0>;
697 clock-names = "pclk_lvds";
700 lcdc: lcdc@1010e000 {
701 compatible = "rockchip,rk312x-lcdc";
702 rockchip,prop = <PRMRY>;
703 reg = <0x1010e000 0x2000>;
704 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>;
706 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_lcdc";
707 rockchip,iommu-enabled = <1>;
711 hdmi: hdmi@20034000 {
712 compatible = "rockchip,rk312x-hdmi";
713 reg = <0x20034000 0x4000>;
714 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
715 rockchip,hdmi_lcdc_source = <0>;
716 pinctrl-names = "default", "gpio";
717 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
718 pinctrl-1 = <&hdmi_gpio>;
719 clocks = <&clk_gates3 8>;
720 clock-names = "pclk_hdmi";
725 compatible = "rockchip,rk312x-tve";
726 reg = <0x1010e200 0x100>;
730 vpu: vpu_service@10106000 {
731 compatible = "vpu_service";
733 reg = <0x10106000 0x800>;
734 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
735 interrupt-names = "irq_enc", "irq_dec";
736 clocks = <&clk_vdpu>, <&hclk_vdpu>;
737 clock-names = "aclk_vcodec", "hclk_vcodec";
738 name = "vpu_service";
742 hevc: hevc_service@10104000 {
743 compatible = "rockchip,hevc_service";
745 reg = <0x10104000 0x400>;
746 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
747 interrupt-names = "irq_dec";
748 clocks = <&clk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>;
749 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
750 name = "hevc_service";
755 compatible = "rockchip,iep";
757 reg = <0x10108000 0x800>;
758 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&clk_gates9 8>, <&clk_gates9 7>;
760 clock-names = "aclk_iep", "hclk_iep";
765 compatible = "rockchip,rk312x-rga";
766 reg = <0x1010c000 0x1000>;
767 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&clk_gates0 11>, <&clk_gates1 4>;
769 clock-names = "hclk_rga", "aclk_rga";
775 compatible = "rockchip,vop_mmu";
776 reg = <0x1010e300 0x100>;
777 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
778 interrupt-names = "vop_mmu";
783 compatible = "rockchip,hevc_mmu";
784 reg = <0x10104440 0x100>,
786 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
787 interrupt-names = "hevc_mmu";
792 compatible = "rockchip,vpu_mmu";
793 reg = <0x10104800 0x100>;
794 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
795 interrupt-names = "vpu_mmu";
800 compatible = "rockchip,iep_mmu";
801 reg = <0x10108800 0x100>;
802 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
803 interrupt-names = "iep_mmu";
807 temp-limit-enable = <0>;
811 regulator_name = "vdd_arm";
813 clk_core_dvfs_table: clk_core {
822 normal-temp-limit = <
823 /*delta-temp delta-freq*/
829 performance-temp-limit = <
845 regulator_name = "vdd_logic";
847 clk_ddr_dvfs_table: clk_ddr {
859 clk_gpu_dvfs_table: clk_gpu {
878 compatible = "rockchip,ion";
879 #address-cells = <1>;
882 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
883 compatible = "rockchip,ion-reserve";
884 rockchip,ion_heap = <1>;
885 reg = <0x00000000 0x10000000>; /* 256MB */
887 rockchip,ion-heap@3 { /* VMALLOC HEAP */
888 rockchip,ion_heap = <3>;
892 compatible = "rockchip,cif";
893 reg = <0x1010a000 0x2000>;
894 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
895 clocks = <&clk_gates3 3>,<&clk_gates6 5>,<&clk_gates6 4>,<&clk_cif0_in>,<&clk_cif_out>;
896 clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
900 codec_hdmi_spdif: codec-hdmi-spdif {
901 compatible = "hdmi-spdif";
904 rockchip-hdmi-spdif {
905 compatible = "rockchip-hdmi-spdif";
908 audio-codec = <&codec_hdmi_spdif>;
909 i2s-controller = <&spdif>;
913 codec: codec@20030000 {
914 compatible = "rk312x-codec";
915 reg = <0x20030000 0x4000>;
916 //pinctrl-names = "default";
917 //pinctrl-0 = <&i2s_gpio>;
919 pa_enable_time = <1000>;
920 clocks = <&clk_gates5 14>;
921 clock-names = "g_pclk_acodec";
924 compatible = "audio-rk312x";
927 audio-codec = <&codec>;
928 i2s-controller = <&i2s1>;
931 //bitclock-inversion;
937 audio-codec = <&codec>;
938 i2s-controller = <&i2s1>;
941 //bitclock-inversion;
954 |RKPM_CTR_ARMOFF_LPMD
957 rockchip,pmic-suspend_gpios = <