1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-pm.h>
3 #include <dt-bindings/sensor-dev.h>
4 #include <dt-bindings/clock/rk_system_status.h>
5 #include <dt-bindings/rkfb/rk_fb.h>
7 #include "skeleton.dtsi"
8 #include "rk312x-clocks.dtsi"
9 #include "rk312x-pinctrl.dtsi"
12 compatible = "rockchip,rk312x";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
34 compatible = "arm,cortex-a7";
39 compatible = "arm,cortex-a7";
44 compatible = "arm,cortex-a7";
49 compatible = "arm,cortex-a7";
55 compatible = "arm,psci";
57 cpu_suspend = <0x84000001>;
58 cpu_off = <0x84000002>;
59 cpu_on = <0x84000003>;
60 migrate = <0x84000005>;
63 gic: interrupt-controller@10139000 {
64 compatible = "arm,cortex-a15-gic";
66 #interrupt-cells = <3>;
68 reg = <0x10139000 0x1000>,
73 compatible = "arm,cortex-a7-pmu";
74 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
80 cpu_axi_bus: cpu_axi_bus {
81 compatible = "rockchip,cpu_axi_bus";
92 reg = <0x10128080 0x20>;
95 reg = <0x1012a000 0x20>;
98 reg = <0x1012c000 0x20>;
101 reg = <0x1012d000 0x20>;
104 reg = <0x1012e000 0x20>;
107 reg = <0x1012f000 0x20>;
110 reg = <0x1012f080 0x20>;
113 reg = <0x1012f100 0x20>;
116 reg = <0x1012f180 0x20>;
117 rockchip,priority = <3 3>;
120 reg = <0x1012f200 0x20>;
121 rockchip,priority = <3 3>;
126 #address-cells = <1>;
131 reg = <0x10128000 0x20>;
132 rockchip,read-latency = <0x3f>;
137 sram: sram@10080400 {
138 compatible = "mmio-sram";
139 reg = <0x10080400 0x1C00>;
145 compatible = "arm,armv7-timer";
146 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
148 clock-frequency = <24000000>;
152 compatible = "rockchip,timer";
153 reg = <0x20044000 0x20>;
154 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
155 rockchip,broadcast = <1>;
158 watchdog: wdt@2004c000 {
159 compatible = "rockchip,watch dog";
160 reg = <0x2004c000 0x100>;
161 // clocks = <&clk_gates7 15>;
162 clock-names = "pclk_wdt";
163 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
165 rockchip,timeout = <60>;
166 rockchip,atboot = <1>;
167 rockchip,debug = <0>;
172 #address-cells = <1>;
174 compatible = "arm,amba-bus";
175 interrupt-parent = <&gic>;
178 pdma: pdma@20078000 {
179 compatible = "arm,pl330", "arm,primecell";
180 reg = <0x20078000 0x4000>;
181 clocks = <&clk_gates5 1>;
182 clock-names = "apb_pclk";
183 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
189 reset: reset@20000110 {
190 compatible = "rockchip,reset";
191 reg = <0x20000110 0x24>;
192 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
196 nandc: nandc@10500000 {
197 compatible = "rockchip,rk-nandc";
198 reg = <0x10500000 0x4000>;
199 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
200 //pinctrl-names = "default";
201 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
203 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 15>;
204 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
207 nandc0reg: nandc0@10500000 {
208 compatible = "rockchip,rk-nandc";
209 reg = <0x10500000 0x4000>;
211 uart0: serial@20060000 {
212 compatible = "rockchip,serial";
213 reg = <0x20060000 0x100>;
214 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
215 clock-frequency = <24000000>;
216 clocks = <&clk_uart0>, <&clk_gates8 0>;
217 clock-names = "sclk_uart", "pclk_uart";
220 dmas = <&pdma 2>, <&pdma 3>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
227 uart1: serial@20064000 {
228 compatible = "rockchip,serial";
229 reg = <0x20064000 0x100>;
230 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
231 clock-frequency = <24000000>;
232 clocks = <&clk_uart1>, <&clk_gates8 1>;
233 clock-names = "sclk_uart", "pclk_uart";
236 dmas = <&pdma 4>, <&pdma 5>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
243 uart2: serial@20068000 {
244 compatible = "rockchip,serial";
245 reg = <0x20068000 0x100>;
246 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
247 clock-frequency = <24000000>;
248 clocks = <&clk_uart2>, <&clk_gates8 2>;
249 clock-names = "sclk_uart", "pclk_uart";
252 dmas = <&pdma 6>, <&pdma 7>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&uart2_xfer>;
260 compatible = "rockchip,rk312x-gmac";
261 reg = <0x2008c000 0x4000>;
262 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; /*irq=88*/
263 interrupt-names = "macirq";
264 clocks = <&clk_mac_ref>, <&clk_gates2 6>,
265 <&clk_gates2 7>, <&clk_gates2 4>,
266 <&clk_gates2 5>, <&clk_gates10 10>,
268 clock-names = "clk_mac", "mac_clk_rx",
269 "mac_clk_tx", "clk_mac_ref",
270 "clk_mac_refout", "aclk_mac",
273 pinctrl-names = "default";
274 pinctrl-0 = <&gmac_rxdv &gmac_txclk &gmac_crs &gmac_rxclk &gmac_mdio &gmac_txen &gmac_clk &gmac_rxer &gmac_rxd1 &gmac_rxd0 &gmac_txd1 &gmac_txd0 &gmac_rxd3 &gmac_rxd2 &gmac_txd2 &gmac_txd3 &gmac_col_gpio &gmac_mdc>;
278 compatible = "rockchip,fiq-debugger";
279 rockchip,serial-id = <2>;
280 rockchip,signal-irq = <106>;
281 rockchip,wake-irq = <0>;
285 rockchip_clocks_init: clocks-init{
286 compatible = "rockchip,clocks-init";
287 rockchip,clocks-init-parent =
288 <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll_div2>,
289 <&aclk_peri &clk_gpll_div2>, <&clk_uart0_pll &clk_gpll>,
290 <&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
291 <&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
292 <&clk_vepu &clk_gpll_div2>, <&clk_vdpu &clk_gpll_div2>,
293 <&clk_hevc_core &clk_gpll>, <&aclk_vio0_pre &clk_gpll_div2>,
294 <&aclk_vio1_pre &clk_gpll_div2>, <&hclk_vio_pre &clk_gpll_div2>,
295 <&sclk_lcdc0 &clk_cpll>, <&clk_gpu &clk_gpll_div2>,
296 <&clk_cif_pll &clk_gpll_div2>, <&dclk_ebc &clk_gpll_div2>,
297 <&clk_emmc &clk_gpll_div2>, <&clk_sdio &clk_gpll_div2>,
298 <&clk_sfc &clk_gpll_div2>, <&clk_sdmmc0 &clk_gpll_div2>,
299 <&clk_tsp &clk_gpll_div2>, <&clk_nandc &clk_gpll_div2>,
300 <&clk_mac_pll &clk_cpll>;
301 rockchip,clocks-init-rate =
302 <&clk_core 600000000>, <&clk_gpll 594000000>,
303 <&clk_cpll 400000000>, <&aclk_cpu 300000000>,
304 <&hclk_cpu_pre 150000000>, <&pclk_cpu_pre 75000000>,
305 <&aclk_peri 300000000>, <&hclk_peri_pre 150000000>,
306 <&pclk_peri_pre 75000000>, <&clk_gpu 300000000>,
307 <&aclk_vio0_pre 300000000>, <&hclk_vio_pre 150000000>,
308 <&aclk_vio1_pre 300000000>, <&clk_vepu 300000000>,
309 <&clk_vdpu 300000000>, <&clk_hevc_core 200000000>,
310 <&clk_mac_ref 125000000>;
311 /* rockchip,clocks-uboot-has-init =
315 compatible = "arm,mali400";
316 reg = <0x10091000 0x200>,
324 reg-names = "Mali_L2",
332 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
339 interrupt-names = "Mali_GP_IRQ",
348 compatible = "rockchip,clocks-enable";
351 <&clk_gates0 6>,<&clk_gates0 0>,
355 <&clk_gates0 1>, <&clk_gates0 3>,
356 <&clk_gates0 4>, <&clk_gates0 5>,
360 <&clk_gates10 3>, <&clk_gates10 4>,
361 <&clk_gates10 5>, <&clk_gates10 6>,
362 <&clk_gates10 7>, <&clk_gates10 8>,
365 <&clk_gates2 0>, <&hclk_peri_pre>,
366 <&pclk_peri_pre>, <&clk_gates2 1>,
369 <&clk_gates4 12>,/*aclk_intmem*/
370 <&clk_gates4 10>,/*aclk_strc_sys*/
373 //<&clk_gates5 6>,/*hclk_rom*/
374 <&clk_gates3 5>,/*hclk_crypto*/
377 <&clk_gates5 4>,/*pclk_grf*/
378 <&clk_gates5 7>,/*pclk_ddrupctl*/
379 //<&clk_gates5 14>,/*pclk_acodec*/
380 //<&clk_gates3 8>,/*pclk_hdmi*/
383 //<&clk_gates10 10>,/*aclk_gmac*/
384 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
385 //<&clk_gates5 1>,/*aclk_dmac2*/
386 <&clk_gates9 15>,/*aclk_peri_niu*/
387 <&clk_gates9 2>,/*g_pclk_pmu*/
388 <&clk_gates9 3>,/*g_pclk_pmu_noc*/
389 <&clk_gates4 2>,/*aclk_cpu_peri*/
392 <&clk_gates4 0>,/*hclk_peri_matrix*/
393 //<&clk_gates9 13>,/*hclk_usb_peri*/
394 <&clk_gates9 14>,/*hclk_peri_arbi*/
397 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
400 //<&clk_gates6 12>,/*hclk_vio_niu*/
401 //<&clk_gates6 1>,/*hclk_lcdc*/
404 //<&clk_gates6 13>,/*aclk_vio*/
405 //<&clk_gates6 0>,/*aclk_lcdc*/
408 //<&clk_gates9 10>,/*aclk_vio1_niu*/
413 <&clk_gates8 2>,/*pclk_uart2*/
418 //<&clk_gates1 3>,/*clk_jtag*/
421 <&clk_gates1 0>;/*pclk_pmu_pre*/
425 compatible = "rockchip,rk30-i2c";
426 reg = <0x20072000 0x1000>;
427 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
428 #address-cells = <1>;
430 pinctrl-names = "default", "gpio";
431 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
432 pinctrl-1 = <&i2c0_gpio>;
433 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
434 clocks = <&clk_gates8 4>;
435 rockchip,check-idle = <1>;
440 compatible = "rockchip,rk30-i2c";
441 reg = <0x20056000 0x1000>;
442 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
445 pinctrl-names = "default", "gpio";
446 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
447 pinctrl-1 = <&i2c1_gpio>;
448 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
449 clocks = <&clk_gates8 5>;
450 rockchip,check-idle = <1>;
455 compatible = "rockchip,rk30-i2c";
456 reg = <0x2005a000 0x1000>;
457 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
458 #address-cells = <1>;
460 pinctrl-names = "default", "gpio";
461 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
462 pinctrl-1 = <&i2c2_gpio>;
463 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
464 clocks = <&clk_gates8 6>;
465 rockchip,check-idle = <1>;
470 compatible = "rockchip,rk30-i2c";
471 reg = <0x2005e000 0x1000>;
472 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
473 #address-cells = <1>;
475 pinctrl-names = "default", "gpio";
476 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
477 pinctrl-1 = <&i2c3_gpio>;
478 gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>;
479 clocks = <&clk_gates8 7>;
480 rockchip,check-idle = <1>;
484 i2s0: i2s0@10220000 {
485 compatible = "rockchip-i2s";
486 reg = <0x10220000 0x1000>;
488 clocks = <&clk_i2s_2ch>, <&clk_i2s_2ch_out>, <&clk_gates7 2>;
489 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
490 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
491 dmas = <&pdma 0>, <&pdma 1>;
493 dma-names = "tx", "rx";
494 //pinctrl-names = "default", "sleep";
495 //pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
496 //pinctrl-1 = <&i2s0_gpio>;
500 i2s1: i2s1@10200000 {
501 compatible = "rockchip-i2s";
502 reg = <0x10200000 0x1000>;
504 clocks = <&clk_i2s_8ch>, <&clk_gates7 4>;
505 clock-names = "i2s_clk", "i2s_hclk";
506 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
507 dmas = <&pdma 14>, <&pdma 15>;
509 dma-names = "tx", "rx";
512 spdif: spdif@10204000 {
513 compatible = "rockchip-spdif";
514 reg = <0x10204000 0x1000>;
515 clocks = <&clk_spdif>, <&clk_gates10 9>;
516 clock-names = "spdif_mclk", "spdif_hclk";
517 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&spdif_tx>;
525 dsihost0: mipi@10110000{
526 compatible = "rockchip,rk312x-dsi";
528 reg = <0x10110000 0x4000>, <0x20038000 0x4000>;
529 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
530 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&clk_gates2 15>, <&clk_gates5 0>, <&clk_gates9 6>, <&clk_gates9 5>, <&pd_mipidsi>;
532 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "hclk_vio_h2p", "pd_mipi_dsi";
536 emmc: rksdmmc@1021c000 {
537 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
538 reg = <0x1021c000 0x4000>;
539 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
540 #address-cells = <1>;
542 //pinctrl-names = "default",,"suspend";
543 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
544 clocks = <&clk_emmc>, <&clk_gates7 0>;
545 clock-names = "clk_mmc", "hclk_mmc";
547 dma-names = "dw_mci";
549 fifo-depth = <0x100>;
551 cru_regsbase = <0x124>;
552 cru_reset_offset = <3>;
556 sdmmc: rksdmmc@10214000 {
557 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
558 reg = <0x10214000 0x4000>;
559 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
560 #address-cells = <1>;
562 pinctrl-names = "default", "idle", "udbg";
563 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
564 pinctrl-1 = <&sdmmc0_gpio>;
565 pinctrl-2 = <&uart2_xfer &sdmmc0_dectn>;
566 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
567 clock-names = "clk_mmc", "hclk_mmc";
569 dma-names = "dw_mci";
571 fifo-depth = <0x100>;
573 cru_regsbase = <0x124>;
574 cru_reset_offset = <1>;
577 sdio: rksdmmc@10218000 {
578 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
579 reg = <0x10218000 0x4000>;
580 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
581 #address-cells = <1>;
583 pinctrl-names = "default","idle";
584 pinctrl-0 = <&sdio0_pwren &sdio0_cmd &sdio0_clk &sdio0_bus4>;
585 pinctrl-1 = <&sdio0_gpio>;
586 clocks = <&clk_sdio>, <&clk_gates5 11>;
587 clock-names = "clk_mmc", "hclk_mmc";
589 dma-names = "dw_mci";
591 fifo-depth = <0x100>;
593 cru_regsbase = <0x124>;
594 cru_reset_offset = <2>;
598 compatible = "rockchip,rockchip-spi";
599 reg = <0x20074000 0x1000>;
600 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
601 #address-cells = <1>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
605 //pinctrl-0 = <&spi0_txd_mux1 &spi0_rxd_mux1 &spi0_clk_mux1 &spi0_cs0_mux1 &spi0_cs1_mux1>;
606 //pinctrl-0 = <&spi0_txd_mux2 &spi0_rxd_mux2 &spi0_clk_mux2 &spi0_cs0_mux2>;
607 rockchip,spi-src-clk = <0>;
609 clocks =<&clk_spi0>, <&clk_gates7 12>;
610 clock-names = "spi","pclk_spi0";
611 dmas = <&pdma 8>, <&pdma 9>;
613 dma-names = "tx", "rx";
618 compatible = "rockchip,saradc";
619 reg = <0x2006c000 0x100>;
620 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
621 #io-channel-cells = <1>;
623 rockchip,adc-vref = <1800>;
624 clock-frequency = <1000000>;
625 clocks = <&clk_saradc>, <&clk_gates7 14>;
626 clock-names = "saradc", "pclk_saradc";
631 compatible = "rockchip,rk-pwm";
632 reg = <0x20050000 0x10>;
634 pinctrl-names = "default";
635 pinctrl-0 = <&pwm0_pin>;
636 clocks = <&clk_gates7 10>;
637 clock-names = "pclk_pwm";
642 compatible = "rockchip,rk-pwm";
643 reg = <0x20050010 0x10>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&pwm1_pin>;
647 clocks = <&clk_gates7 10>;
648 clock-names = "pclk_pwm";
653 compatible = "rockchip,rk-pwm";
654 reg = <0x20050020 0x10>;
656 pinctrl-names = "default";
657 pinctrl-0 = <&pwm2_pin>;
658 clocks = <&clk_gates7 10>;
659 clock-names = "pclk_pwm";
664 compatible = "rockchip,rk-pwm";
665 reg = <0x20050030 0x10>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&pwm3_pin>;
669 clocks = <&clk_gates7 10>;
670 clock-names = "pclk_pwm";
674 remotectl: pwm@20050030 {
675 compatible = "rockchip,remotectl-pwm";
676 reg = <0x20050030 0x10>;
678 pinctrl-names = "default";
679 pinctrl-0 = <&pwm3_pin>;
680 clocks = <&clk_gates7 10>;
681 clock-names = "pclk_pwm";
683 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
686 dwc_control_usb: dwc-control-usb@20008000 {
687 compatible = "rockchip,rk3126-dwc-control-usb";
688 reg = <0x20008000 0x4>;
689 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
692 interrupt-names = "otg_bvalid",
695 clocks = <&clk_gates9 13>;
696 clock-names = "hclk_usb_peri";
697 rockchip,remote_wakeup;
698 rockchip,usb_irq_wakeup;
699 resets = <&reset RK3128_RST_USBPOR>;
700 reset-names = "usbphy_por";
702 compatible = "inno,phy";
703 regbase = &dwc_control_usb;
704 rk_usb,bvalid = <0x14c 5 1>;
705 rk_usb,iddig = <0x14c 8 1>;
706 rk_usb,vdmsrcen = <0x184 12 1>;
707 rk_usb,vdpsrcen = <0x184 11 1>;
708 rk_usb,rdmpden = <0x184 10 1>;
709 rk_usb,idpsrcen = <0x184 9 1>;
710 rk_usb,idmsinken = <0x184 8 1>;
711 rk_usb,idpsinken = <0x184 7 1>;
712 rk_usb,dpattach = <0x2c0 7 1>;
713 rk_usb,cpdet = <0x2c0 6 1>;
714 rk_usb,dcpattach = <0x2c0 5 1>;
719 compatible = "rockchip,rk3126_usb20_otg";
720 reg = <0x10180000 0x40000>;
721 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
723 clock-names = "clk_usbphy0", "hclk_usb0";
724 resets = <&reset RK3128_RST_USBOTG0>, <&reset RK3128_RST_UTMI0>,
725 <&reset RK3128_RST_OTGC0>;
726 reset-names = "otg_ahb", "otg_phy", "otg_controller";
727 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
728 rockchip,usb-mode = <0>;
732 compatible = "rockchip,rk3126_ehci";
733 reg = <0x101c0000 0x20000>;
734 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
736 clock-names = "clk_usbphy1", "hclk_host0";
737 resets = <&reset RK3128_RST_USBOTG1>, <&reset RK3128_RST_UTMI1>,
738 <&reset RK3128_RST_OTGC1>;
739 reset-names = "host_ahb", "host_phy", "host_controller";
743 compatible = "rockchip,rk3126_ohci";
744 reg = <0x101e0000 0x20000>;
745 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
749 compatible = "rockchip,rk-fb";
750 rockchip,disp-mode = <ONE_DUAL>;
753 rk_screen: rk_screen{
754 compatible = "rockchip,screen";
757 lvds: lvds@20038000 {
758 compatible = "rockchip,rk31xx-lvds";
759 reg = <0x20038000 0x4000>, <0x101100b0 0x01>;
760 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
761 clocks = <&clk_gates5 0>, <&clk_gates9 6>, <&clk_gates9 5>;
762 clock-names = "pclk_lvds", "pclk_lvds_ctl", "hclk_vio_h2p";
766 lcdc: lcdc@1010e000 {
767 compatible = "rockchip,rk312x-lcdc";
768 rockchip,prop = <PRMRY>;
769 reg = <0x1010e000 0x1000>;
770 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>, <&pd_vop>, <&clk_cpll>;
772 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_lcdc", "pd_lcdc", "sclk_pll";
773 rockchip,iommu-enabled = <1>;
777 hdmi: hdmi@20034000 {
778 compatible = "rockchip,rk312x-hdmi";
779 reg = <0x20034000 0x4000>;
780 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
781 rockchip,hdmi_lcdc_source = <0>;
782 pinctrl-names = "default", "gpio";
783 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
784 pinctrl-1 = <&hdmi_gpio>;
785 clocks = <&clk_gates3 8>, <&pd_hdmi>;
786 clock-names = "pclk_hdmi", "pd_hdmi";
787 rockchip,hdcp_enable = <0>;
788 rockchip,cec_enable = <0>;
793 compatible = "rockchip,rk312x-tve";
794 reg = <0x1010e200 0x100>;
795 saturation = <0x002b4d3c>;
796 brightcontrast = <0x00007700>;
797 adjtiming = <0xa6c00880>;
798 lumafilter0 = <0x02ff0000>;
799 lumafilter1 = <0xf40202fd>;
800 lumafilter2 = <0xf332d919>;
806 compatible = "rockchip,vpu_sub";
808 reg = <0x10106000 0x800>;
809 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
811 interrupt-names = "irq_enc", "irq_dec";
813 name = "vpu_service";
817 compatible = "rockchip,hevc_sub";
819 reg = <0x10104000 0x400>;
820 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
821 interrupt-names = "irq_dec";
823 name = "hevc_service";
826 vpu_combo: vpu_combo@ff9a0000 {
827 compatible = "rockchip,vpu_combo";
829 rockchip,sub = <&vpu>, <&hevc>;
830 clocks = <&clk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>;
831 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
832 resets = <&reset RK3128_RST_VCODEC_H>, <&reset RK3128_RST_VCODEC_A>,
833 <&reset RK3128_RST_HEVC>;
834 reset-names = "video_h", "video_a", "video";
842 compatible = "rockchip,iep";
844 reg = <0x10108000 0x800>;
845 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&clk_gates9 8>, <&clk_gates9 7>;
847 clock-names = "aclk_iep", "hclk_iep";
853 compatible = "rockchip,rk312x-rga";
854 reg = <0x1010c000 0x1000>;
855 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
857 clock-names = "hclk_rga", "aclk_rga";
863 compatible = "rockchip,vop_mmu";
864 reg = <0x1010e300 0x100>;
865 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
866 interrupt-names = "vop_mmu";
871 compatible = "rockchip,hevc_mmu";
872 reg = <0x10104440 0x40>,
874 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
875 interrupt-names = "hevc_mmu";
880 compatible = "rockchip,vpu_mmu";
881 reg = <0x10106800 0x100>;
882 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
883 interrupt-names = "vpu_mmu";
888 compatible = "rockchip,iep_mmu";
889 reg = <0x10108800 0x100>;
890 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
891 interrupt-names = "iep_mmu";
896 regulator_name = "vdd_arm";
898 clk_core_dvfs_table: clk_core {
906 temp-limit-enable = <0>;
909 normal-temp-limit = <
910 /*delta-temp delta-freq*/
916 performance-temp-limit = <
927 lkg_adjust_volt_en = <1>;
929 def_table_lkg = <35>;
930 min_adjust_freq = <1200000>;
931 lkg_adjust_volt_table = <
940 regulator_name = "vdd_logic";
942 clk_ddr_dvfs_table: clk_ddr {
954 clk_gpu_dvfs_table: clk_gpu {
973 compatible = "rockchip,ion";
974 #address-cells = <1>;
977 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
978 compatible = "rockchip,ion-heap";
979 rockchip,ion_heap = <4>;
980 reg = <0x00000000 0x800000>; /* 8MB */
982 rockchip,ion-heap@0 { /* VMALLOC HEAP */
983 compatible = "rockchip,ion-heap";
984 rockchip,ion_heap = <0>;
988 compatible = "rockchip,cif";
989 reg = <0x1010a000 0x2000>;
990 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
991 clocks = <&pd_vip>,<&clk_gates6 5>,<&clk_gates6 4>,<&clk_cif0_in>,<&clk_cif_out>;
992 clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
996 codec_hdmi_spdif: codec-hdmi-spdif {
997 compatible = "hdmi-spdif";
1000 rockchip-hdmi-spdif {
1001 compatible = "rockchip-hdmi-spdif";
1004 audio-codec = <&codec_hdmi_spdif>;
1005 audio-controller = <&spdif>;
1009 codec: codec@20030000 {
1010 compatible = "rk312x-codec";
1011 reg = <0x20030000 0x4000>;
1012 //pinctrl-names = "default";
1013 //pinctrl-0 = <&i2s_gpio>;
1015 pa_enable_time = <1000>;
1016 clocks = <&clk_gates5 14>;
1017 clock-names = "g_pclk_acodec";
1019 rockchip_audio: audio-rk312x {
1020 compatible = "audio-rk312x";
1023 audio-codec = <&codec>;
1024 audio-controller = <&i2s1>;
1027 //bitclock-inversion;
1033 audio-codec = <&codec>;
1034 audio-controller = <&i2s1>;
1037 //bitclock-inversion;