arch/arm/boot/dts/rk3188-clocks.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 / {
  17         clocks {
  18                 #address-cells = <1>;
  19                 #size-cells = <1>;
  20                 ranges;
  21
  22                 /*
  23                  * This is a dummy clock, to be used as placeholder on
  24                  * other mux clocks when a specific parent clock is not
  25                  * yet implemented. It should be dropped when the driver
  26                  * is complete.
  27                  */
  28                 dummy: dummy {
  29                         compatible = "fixed-clock";
  30                         clock-frequency = <0>;
  31                         #clock-cells = <0>;
  32                 };
  33
  34                 dummy48m: dummy48m {
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <48000000>;
  37                         #clock-cells = <0>;
  38                 };
  39
  40                 dummy150m: dummy150m {
  41                         compatible = "fixed-clock";
  42                         clock-frequency = <150000000>;
  43                         #clock-cells = <0>;
  44                 };
  45
  46                 clk_gates0: gate-clk@200000d0 {
  47                         compatible = "rockchip,rk2928-gate-clk";
  48                         reg = <0x200000d0 0x4>;
  49                         clocks = <&dummy150m>, <&dummy>,
  50                                  <&dummy>, <&dummy>,
  51                                  <&dummy>, <&dummy>,
  52                                  <&dummy>, <&dummy>,
  53                                  <&dummy>, <&dummy>,
  54                                  <&dummy>, <&dummy>,
  55                                  <&dummy>, <&dummy>,
  56                                  <&dummy>, <&dummy>;
  57
  58                         clock-output-names =
  59                                 "gate_core_periph", "gate_cpu_gpll",
  60                                 "gate_ddrphy", "gate_aclk_cpu",
  61                                 "gate_hclk_cpu", "gate_pclk_cpu",
  62                                 "gate_atclk_cpu", "gate_aclk_core",
  63                                 "reserved", "gate_i2s0",
  64                                 "gate_i2s0_frac", "reserved",
  65                                 "reserved", "gate_spdif",
  66                                 "gate_spdif_frac", "gate_testclk";
  67
  68                         #clock-cells = <1>;
  69                 };
  70
  71                 clk_gates1: gate-clk@200000d4 {
  72                         compatible = "rockchip,rk2928-gate-clk";
  73                         reg = <0x200000d4 0x4>;
  74                         clocks = <&xin24m>, <&xin24m>,
  75                                  <&xin24m>, <&dummy>,
  76                                  <&dummy>, <&xin24m>,
  77                                  <&xin24m>, <&dummy>,
  78                                  <&xin24m>, <&dummy>,
  79                                  <&xin24m>, <&dummy>,
  80                                  <&xin24m>, <&dummy>,
  81                                  <&xin24m>, <&dummy>;
  82
  83                         clock-output-names =
  84                                 "gate_timer0", "gate_timer1",
  85                                 "gate_timer3", "gate_jtag",
  86                                 "gate_aclk_lcdc1_src", "gate_otgphy0",
  87                                 "gate_otgphy1", "gate_ddr_gpll",
  88                                 "gate_uart0", "gate_frac_uart0",
  89                                 "gate_uart1", "gate_frac_uart1",
  90                                 "gate_uart2", "gate_frac_uart2",
  91                                 "gate_uart3", "gate_frac_uart3";
  92
  93                         #clock-cells = <1>;
  94                 };
  95
  96                 clk_gates2: gate-clk@200000d8 {
  97                         compatible = "rockchip,rk2928-gate-clk";
  98                         reg = <0x200000d8 0x4>;
  99                         clocks = <&clk_gates2 1>, <&dummy>,
 100                                  <&dummy>, <&dummy>,
 101                                  <&dummy>, <&dummy>,
 102                                  <&clk_gates2 3>, <&dummy>,
 103                                  <&dummy>, <&dummy>,
 104                                  <&dummy>, <&dummy48m>,
 105                                  <&dummy>, <&dummy48m>,
 106                                  <&dummy>, <&dummy>;
 107
 108                         clock-output-names =
 109                                 "gate_periph_src", "gate_aclk_periph",
 110                                 "gate_hclk_periph", "gate_pclk_periph",
 111                                 "gate_smc", "gate_mac",
 112                                 "gate_hsadc", "gate_hsadc_frac",
 113                                 "gate_saradc", "gate_spi0",
 114                                 "gate_spi1", "gate_mmc0",
 115                                 "gate_mac_lbtest", "gate_mmc1",
 116                                 "gate_emmc", "reserved";
 117
 118                         #clock-cells = <1>;
 119                 };
 120
 121                 clk_gates3: gate-clk@200000dc {
 122                         compatible = "rockchip,rk2928-gate-clk";
 123                         reg = <0x200000dc 0x4>;
 124                         clocks = <&dummy>, <&dummy>,
 125                                  <&dummy>, <&dummy>,
 126                                  <&xin24m>, <&xin24m>,
 127                                  <&dummy>, <&dummy>,
 128                                  <&xin24m>, <&dummy>,
 129                                  <&dummy>, <&dummy>,
 130                                  <&dummy>, <&dummy>,
 131                                  <&xin24m>, <&dummy>;
 132
 133                         clock-output-names =
 134                                 "gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
 135                                 "gate_dclk_lcdc1", "gate_pclkin_cif0",
 136                                 "gate_timer2", "gate_timer4",
 137                                 "gate_hsicphy", "gate_cif0_out",
 138                                 "gate_timer5", "gate_aclk_vepu",
 139                                 "gate_hclk_vepu", "gate_aclk_vdpu",
 140                                 "gate_hclk_vdpu", "reserved",
 141                                 "gate_timer6", "gate_aclk_gpu_src";
 142
 143                         #clock-cells = <1>;
 144                 };
 145
 146                 clk_gates4: gate-clk@200000e0 {
 147                         compatible = "rockchip,rk2928-gate-clk";
 148                         reg = <0x200000e0 0x4>;
 149                         clocks = <&clk_gates2 2>, <&clk_gates2 3>,
 150                                  <&clk_gates2 1>, <&clk_gates2 1>,
 151                                  <&clk_gates2 1>, <&clk_gates2 2>,
 152                                  <&clk_gates2 2>, <&clk_gates2 2>,
 153                                  <&clk_gates0 4>, <&clk_gates0 4>,
 154                                  <&clk_gates0 3>, <&dummy>,
 155                                  <&clk_gates0 3>, <&dummy>,
 156                                  <&dummy>, <&dummy>;
 157
 158                         clock-output-names =
 159                                 "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
 160                                 "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
 161                                 "gate_aclk_pei_niu", "gate_hclk_usb_peri",
 162                                 "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
 163                                 "gate_hclk_cpubus", "gate_hclk_ahb2apb",
 164                                 "gate_aclk_strc_sys", "reserved",
 165                                 "gate_aclk_intmem", "reserved",
 166                                 "gate_hclk_imem1", "gate_hclk_imem0";
 167
 168                         #clock-cells = <1>;
 169                 };
 170
 171                 clk_gates5: gate-clk@200000e4 {
 172                         compatible = "rockchip,rk2928-gate-clk";
 173                         reg = <0x200000e4 0x4>;
 174                         clocks = <&clk_gates0 3>, <&clk_gates2 1>,
 175                                  <&clk_gates0 5>, <&clk_gates0 5>,
 176                                  <&clk_gates0 5>, <&clk_gates0 5>,
 177                                  <&clk_gates0 4>, <&clk_gates0 5>,
 178                                  <&clk_gates2 1>, <&clk_gates2 2>,
 179                                  <&clk_gates2 2>, <&clk_gates2 2>,
 180                                  <&clk_gates2 2>, <&clk_gates4 5>;
 181
 182                         clock-output-names =
 183                                 "gate_aclk_dmac1", "gate_aclk_dmac2",
 184                                 "gate_pclk_efuse", "gate_pclk_tzpc",
 185                                 "gate_pclk_grf", "gate_pclk_pmu",
 186                                 "gate_hclk_rom", "gate_pclk_ddrupctl",
 187                                 "gate_aclk_smc", "gate_hclk_nandc",
 188                                 "gate_hclk_mmc0", "gate_hclk_mmc1",
 189                                 "gate_hclk_emmc", "gate_hclk_otg0";
 190
 191                         #clock-cells = <1>;
 192                 };
 193
 194                 clk_gates6: gate-clk@200000e8 {
 195                         compatible = "rockchip,rk2928-gate-clk";
 196                         reg = <0x200000e8 0x4>;
 197                         clocks = <&clk_gates3 0>, <&clk_gates0 4>,
 198                                  <&clk_gates0 4>, <&clk_gates1 4>,
 199                                  <&clk_gates0 4>, <&clk_gates3 0>,
 200                                  <&dummy>, <&dummy>,
 201                                  <&clk_gates3 0>, <&clk_gates0 4>,
 202                                  <&clk_gates0 4>, <&clk_gates1 4>,
 203                                  <&clk_gates0 4>, <&clk_gates3 0>;
 204
 205                         clock-output-names =
 206                                 "gate_aclk_lcdc0", "gate_hclk_lcdc0",
 207                                 "gate_hclk_lcdc1", "gate_aclk_lcdc1",
 208                                 "gate_hclk_cif0", "gate_aclk_cif0",
 209                                 "reserved", "reserved",
 210                                 "gate_aclk_ipp", "gate_hclk_ipp",
 211                                 "gate_hclk_rga", "gate_aclk_rga",
 212                                 "gate_hclk_vio_bus", "gate_aclk_vio0";
 213
 214                         #clock-cells = <1>;
 215                 };
 216
 217                 clk_gates7: gate-clk@200000ec {
 218                         compatible = "rockchip,rk2928-gate-clk";
 219                         reg = <0x200000ec 0x4>;
 220                         clocks = <&clk_gates2 2>, <&clk_gates0 4>,
 221                                  <&clk_gates0 4>, <&dummy>,
 222                                  <&dummy>, <&clk_gates2 2>,
 223                                  <&clk_gates2 2>, <&clk_gates0 5>,
 224                                  <&dummy>, <&clk_gates0 5>,
 225                                  <&clk_gates0 5>, <&clk_gates2 3>,
 226                                  <&clk_gates2 3>, <&clk_gates2 3>,
 227                                  <&clk_gates2 3>, <&clk_gates2 3>;
 228
 229                         clock-output-names =
 230                                 "gate_hclk_emac", "gate_hclk_spdif",
 231                                 "gate_hclk_i2s0_2ch", "gate_hclk_otg1",
 232                                 "gate_hclk_hsic", "gate_hclk_hsadc",
 233                                 "gate_hclk_pidf", "gate_pclk_timer0",
 234                                 "reserved", "gate_pclk_timer2",
 235                                 "gate_pclk_pwm01", "gate_pclk_pwm23",
 236                                 "gate_pclk_spi0", "gate_pclk_spi1",
 237                                 "gate_pclk_saradc", "gate_pclk_wdt";
 238
 239                         #clock-cells = <1>;
 240                 };
 241
 242                 clk_gates8: gate-clk@200000f0 {
 243                         compatible = "rockchip,rk2928-gate-clk";
 244                         reg = <0x200000f0 0x4>;
 245                         clocks = <&clk_gates0 5>, <&clk_gates0 5>,
 246                                  <&clk_gates2 3>, <&clk_gates2 3>,
 247                                  <&clk_gates0 5>, <&clk_gates0 5>,
 248                                  <&clk_gates2 3>, <&clk_gates2 3>,
 249                                  <&clk_gates2 3>, <&clk_gates0 5>,
 250                                  <&clk_gates0 5>, <&clk_gates0 5>,
 251                                  <&clk_gates2 3>, <&dummy>;
 252
 253                         clock-output-names =
 254                                 "gate_pclk_uart0", "gate_pclk_uart1",
 255                                 "gate_pclk_uart2", "gate_pclk_uart3",
 256                                 "gate_pclk_i2c0", "gate_pclk_i2c1",
 257                                 "gate_pclk_i2c2", "gate_pclk_i2c3",
 258                                 "gate_pclk_i2c4", "gate_pclk_gpio0",
 259                                 "gate_pclk_gpio1", "gate_pclk_gpio2",
 260                                 "gate_pclk_gpio3", "gate_aclk_gps";
 261
 262                         #clock-cells = <1>;
 263                 };
 264
 265                 clk_gates9: gate-clk@200000f4 {
 266                         compatible = "rockchip,rk2928-gate-clk";
 267                         reg = <0x200000f4 0x4>;
 268                         clocks = <&dummy>, <&dummy>,
 269                                  <&dummy>, <&dummy>,
 270                                  <&dummy>, <&dummy>,
 271                                  <&dummy>, <&dummy>;
 272
 273                         clock-output-names =
 274                                 "gate_clk_core_dbg", "gate_pclk_dbg",
 275                                 "gate_clk_trace", "gate_atclk",
 276                                 "gate_clk_l2c", "gate_aclk_vio1",
 277                                 "gate_pclk_publ", "gate_aclk_gpu";
 278
 279                         #clock-cells = <1>;
 280                 };
 281         };
 282
 283 };