2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/pinctrl/rockchip.h>
46 #include <dt-bindings/clock/rk3188-cru.h>
47 #include "rk3xxx.dtsi"
50 compatible = "rockchip,rk3188";
55 enable-method = "rockchip,rk3066-smp";
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
73 clock-latency = <40000>;
74 clocks = <&cru ARMCLK>;
78 compatible = "arm,cortex-a9";
79 next-level-cache = <&L2>;
84 compatible = "arm,cortex-a9";
85 next-level-cache = <&L2>;
90 compatible = "arm,cortex-a9";
91 next-level-cache = <&L2>;
97 compatible = "mmio-sram";
98 reg = <0x10080000 0x8000>;
101 ranges = <0 0x10080000 0x8000>;
104 compatible = "rockchip,rk3066-smp-sram";
110 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
111 reg = <0x1011a000 0x2000>;
112 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
113 #address-cells = <1>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&i2s0_bus>;
117 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
118 dma-names = "tx", "rx";
119 clock-names = "i2s_hclk", "i2s_clk";
120 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
121 rockchip,playback-channels = <2>;
122 rockchip,capture-channels = <2>;
126 spdif: sound@1011e000 {
127 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
128 reg = <0x1011e000 0x2000>;
129 #sound-dai-cells = <0>;
130 clock-names = "hclk", "mclk";
131 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
134 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&spdif_tx>;
140 cru: clock-controller@20000000 {
141 compatible = "rockchip,rk3188-cru";
142 reg = <0x20000000 0x1000>;
143 rockchip,grf = <&grf>;
150 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
151 rockchip,grf = <&grf>;
152 #address-cells = <1>;
156 usbphy0: usb-phy@10c {
159 clocks = <&cru SCLK_OTGPHY0>;
160 clock-names = "phyclk";
163 usbphy1: usb-phy@11c {
166 clocks = <&cru SCLK_OTGPHY1>;
167 clock-names = "phyclk";
172 compatible = "rockchip,rk3188-pinctrl";
173 rockchip,grf = <&grf>;
174 rockchip,pmu = <&pmu>;
176 #address-cells = <1>;
180 gpio0: gpio0@2000a000 {
181 compatible = "rockchip,rk3188-gpio-bank0";
182 reg = <0x2000a000 0x100>;
183 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&cru PCLK_GPIO0>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
193 gpio1: gpio1@2003c000 {
194 compatible = "rockchip,gpio-bank";
195 reg = <0x2003c000 0x100>;
196 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&cru PCLK_GPIO1>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
206 gpio2: gpio2@2003e000 {
207 compatible = "rockchip,gpio-bank";
208 reg = <0x2003e000 0x100>;
209 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&cru PCLK_GPIO2>;
215 interrupt-controller;
216 #interrupt-cells = <2>;
219 gpio3: gpio3@20080000 {
220 compatible = "rockchip,gpio-bank";
221 reg = <0x20080000 0x100>;
222 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&cru PCLK_GPIO3>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
232 pcfg_pull_up: pcfg_pull_up {
236 pcfg_pull_down: pcfg_pull_down {
240 pcfg_pull_none: pcfg_pull_none {
246 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
250 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
254 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
258 * The data pins are shared between nandc and emmc and
259 * not accessible through pinctrl. Also they should've
260 * been already set correctly by firmware, as
261 * flash/emmc is the boot-device.
266 emac_xfer: emac-xfer {
267 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
268 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
269 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
270 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
271 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
272 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
273 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
274 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
277 emac_mdio: emac-mdio {
278 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
279 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
284 i2c0_xfer: i2c0-xfer {
285 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
286 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
291 i2c1_xfer: i2c1-xfer {
292 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
293 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
298 i2c2_xfer: i2c2-xfer {
299 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
300 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
305 i2c3_xfer: i2c3-xfer {
306 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
307 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
312 i2c4_xfer: i2c4-xfer {
313 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
314 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
320 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
326 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
332 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
338 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
344 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
347 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
350 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
353 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
356 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
362 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
365 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
368 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
371 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
374 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
379 uart0_xfer: uart0-xfer {
380 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
381 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
384 uart0_cts: uart0-cts {
385 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
388 uart0_rts: uart0-rts {
389 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
394 uart1_xfer: uart1-xfer {
395 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
396 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
399 uart1_cts: uart1-cts {
400 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
403 uart1_rts: uart1-rts {
404 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
409 uart2_xfer: uart2-xfer {
410 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
411 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
413 /* no rts / cts for uart2 */
417 uart3_xfer: uart3-xfer {
418 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
419 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
422 uart3_cts: uart3-cts {
423 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
426 uart3_rts: uart3-rts {
427 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
433 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
437 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
441 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
445 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
449 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
452 sd0_bus1: sd0-bus-width1 {
453 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
456 sd0_bus4: sd0-bus-width4 {
457 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
458 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
459 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
460 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
466 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
470 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
474 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
478 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
481 sd1_bus1: sd1-bus-width1 {
482 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
485 sd1_bus4: sd1-bus-width4 {
486 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
487 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
488 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
489 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
495 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
496 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
497 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
498 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
499 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
500 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
506 rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
513 compatible = "rockchip,rk3188-emac";
517 interrupts = <GIC_PPI 11 0xf04>;
521 interrupts = <GIC_PPI 13 0xf04>;
525 compatible = "rockchip,rk3188-i2c";
526 pinctrl-names = "default";
527 pinctrl-0 = <&i2c0_xfer>;
531 compatible = "rockchip,rk3188-i2c";
532 pinctrl-names = "default";
533 pinctrl-0 = <&i2c1_xfer>;
537 compatible = "rockchip,rk3188-i2c";
538 pinctrl-names = "default";
539 pinctrl-0 = <&i2c2_xfer>;
543 compatible = "rockchip,rk3188-i2c";
544 pinctrl-names = "default";
545 pinctrl-0 = <&i2c3_xfer>;
549 compatible = "rockchip,rk3188-i2c";
550 pinctrl-names = "default";
551 pinctrl-0 = <&i2c4_xfer>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&pwm0_out>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&pwm1_out>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&pwm2_out>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&pwm3_out>;
575 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
576 pinctrl-names = "default";
577 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
581 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
582 pinctrl-names = "default";
583 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&uart0_xfer>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&uart1_xfer>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&uart2_xfer>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&uart3_xfer>;
607 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";