2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/rockchip.h>
18 #include <dt-bindings/clock/rk3188-cru.h>
19 #include "rk3xxx.dtsi"
22 compatible = "rockchip,rk3188";
27 enable-method = "rockchip,rk3066-smp";
31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
43 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "mmio-sram";
57 reg = <0x10080000 0x8000>;
60 ranges = <0 0x10080000 0x8000>;
63 compatible = "rockchip,rk3066-smp-sram";
68 cru: clock-controller@20000000 {
69 compatible = "rockchip,rk3188-cru";
70 reg = <0x20000000 0x1000>;
71 rockchip,grf = <&grf>;
78 compatible = "rockchip,rk3188-pinctrl";
79 rockchip,grf = <&grf>;
80 rockchip,pmu = <&pmu>;
86 gpio0: gpio0@0x2000a000 {
87 compatible = "rockchip,rk3188-gpio-bank0";
88 reg = <0x2000a000 0x100>;
89 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&cru PCLK_GPIO0>;
96 #interrupt-cells = <2>;
99 gpio1: gpio1@0x2003c000 {
100 compatible = "rockchip,gpio-bank";
101 reg = <0x2003c000 0x100>;
102 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&cru PCLK_GPIO1>;
108 interrupt-controller;
109 #interrupt-cells = <2>;
112 gpio2: gpio2@2003e000 {
113 compatible = "rockchip,gpio-bank";
114 reg = <0x2003e000 0x100>;
115 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&cru PCLK_GPIO2>;
121 interrupt-controller;
122 #interrupt-cells = <2>;
125 gpio3: gpio3@20080000 {
126 compatible = "rockchip,gpio-bank";
127 reg = <0x20080000 0x100>;
128 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&cru PCLK_GPIO3>;
134 interrupt-controller;
135 #interrupt-cells = <2>;
138 pcfg_pull_up: pcfg_pull_up {
142 pcfg_pull_down: pcfg_pull_down {
146 pcfg_pull_none: pcfg_pull_none {
152 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
156 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
160 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
164 * The data pins are shared between nandc and emmc and
165 * not accessible through pinctrl. Also they should've
166 * been already set correctly by firmware, as
167 * flash/emmc is the boot-device.
172 emac_xfer: emac-xfer {
173 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
174 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
175 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
176 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
177 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
178 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
179 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
180 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
183 emac_mdio: emac-mdio {
184 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
185 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
190 i2c0_xfer: i2c0-xfer {
191 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
192 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
197 i2c1_xfer: i2c1-xfer {
198 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
199 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
204 i2c2_xfer: i2c2-xfer {
205 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
206 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
211 i2c3_xfer: i2c3-xfer {
212 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
213 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
218 i2c4_xfer: i2c4-xfer {
219 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
220 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
226 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
232 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
238 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
244 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
250 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
253 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
256 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
259 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
262 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
268 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
271 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
274 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
277 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
280 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
285 uart0_xfer: uart0-xfer {
286 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
287 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
290 uart0_cts: uart0-cts {
291 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
294 uart0_rts: uart0-rts {
295 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
300 uart1_xfer: uart1-xfer {
301 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
302 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
305 uart1_cts: uart1-cts {
306 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
309 uart1_rts: uart1-rts {
310 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
315 uart2_xfer: uart2-xfer {
316 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
317 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
319 /* no rts / cts for uart2 */
323 uart3_xfer: uart3-xfer {
324 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
325 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
328 uart3_cts: uart3-cts {
329 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
332 uart3_rts: uart3-rts {
333 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
339 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
343 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
347 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
351 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
355 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
358 sd0_bus1: sd0-bus-width1 {
359 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
362 sd0_bus4: sd0-bus-width4 {
363 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
364 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
365 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
366 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
372 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
376 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
380 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
384 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
387 sd1_bus1: sd1-bus-width1 {
388 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
391 sd1_bus4: sd1-bus-width4 {
392 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
393 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
394 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
395 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
402 compatible = "rockchip,rk3188-emac";
406 interrupts = <GIC_PPI 11 0xf04>;
410 interrupts = <GIC_PPI 13 0xf04>;
414 compatible = "rockchip,rk3188-i2c";
415 pinctrl-names = "default";
416 pinctrl-0 = <&i2c0_xfer>;
420 compatible = "rockchip,rk3188-i2c";
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c1_xfer>;
426 compatible = "rockchip,rk3188-i2c";
427 pinctrl-names = "default";
428 pinctrl-0 = <&i2c2_xfer>;
432 compatible = "rockchip,rk3188-i2c";
433 pinctrl-names = "default";
434 pinctrl-0 = <&i2c3_xfer>;
438 compatible = "rockchip,rk3188-i2c";
439 pinctrl-names = "default";
440 pinctrl-0 = <&i2c4_xfer>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&pwm0_out>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&pwm1_out>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&pwm2_out>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&pwm3_out>;
464 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
465 pinctrl-names = "default";
466 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
470 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
471 pinctrl-names = "default";
472 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&uart0_xfer>;
481 pinctrl-names = "default";
482 pinctrl-0 = <&uart1_xfer>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&uart2_xfer>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&uart3_xfer>;
496 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";