2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/rockchip.h>
18 #include <dt-bindings/clock/rk3188-cru.h>
19 #include "rk3xxx.dtsi"
22 compatible = "rockchip,rk3188";
27 enable-method = "rockchip,rk3066-smp";
31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
43 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "mmio-sram";
57 reg = <0x10080000 0x8000>;
60 ranges = <0 0x10080000 0x8000>;
63 compatible = "rockchip,rk3066-smp-sram";
68 cru: clock-controller@20000000 {
69 compatible = "rockchip,rk3188-cru";
70 reg = <0x20000000 0x1000>;
71 rockchip,grf = <&grf>;
78 compatible = "rockchip,rk3188-pinctrl";
79 rockchip,grf = <&grf>;
80 rockchip,pmu = <&pmu>;
86 gpio0: gpio0@0x2000a000 {
87 compatible = "rockchip,rk3188-gpio-bank0";
88 reg = <0x2000a000 0x100>;
89 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&cru PCLK_GPIO0>;
96 #interrupt-cells = <2>;
99 gpio1: gpio1@0x2003c000 {
100 compatible = "rockchip,gpio-bank";
101 reg = <0x2003c000 0x100>;
102 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&cru PCLK_GPIO1>;
108 interrupt-controller;
109 #interrupt-cells = <2>;
112 gpio2: gpio2@2003e000 {
113 compatible = "rockchip,gpio-bank";
114 reg = <0x2003e000 0x100>;
115 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&cru PCLK_GPIO2>;
121 interrupt-controller;
122 #interrupt-cells = <2>;
125 gpio3: gpio3@20080000 {
126 compatible = "rockchip,gpio-bank";
127 reg = <0x20080000 0x100>;
128 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&cru PCLK_GPIO3>;
134 interrupt-controller;
135 #interrupt-cells = <2>;
138 pcfg_pull_up: pcfg_pull_up {
142 pcfg_pull_down: pcfg_pull_down {
146 pcfg_pull_none: pcfg_pull_none {
151 i2c0_xfer: i2c0-xfer {
152 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
153 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
158 i2c1_xfer: i2c1-xfer {
159 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
160 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
165 i2c2_xfer: i2c2-xfer {
166 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
167 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
172 i2c3_xfer: i2c3-xfer {
173 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
174 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
179 i2c4_xfer: i2c4-xfer {
180 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
181 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
187 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
193 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
199 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
205 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
210 uart0_xfer: uart0-xfer {
211 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
212 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
215 uart0_cts: uart0-cts {
216 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
219 uart0_rts: uart0-rts {
220 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
225 uart1_xfer: uart1-xfer {
226 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
227 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
230 uart1_cts: uart1-cts {
231 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
234 uart1_rts: uart1-rts {
235 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
240 uart2_xfer: uart2-xfer {
241 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
242 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
244 /* no rts / cts for uart2 */
248 uart3_xfer: uart3-xfer {
249 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
250 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
253 uart3_cts: uart3-cts {
254 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
257 uart3_rts: uart3-rts {
258 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
264 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
268 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
272 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
276 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
280 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
283 sd0_bus1: sd0-bus-width1 {
284 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
287 sd0_bus4: sd0-bus-width4 {
288 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
289 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
290 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
291 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
297 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
301 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
305 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
309 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
312 sd1_bus1: sd1-bus-width1 {
313 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
316 sd1_bus4: sd1-bus-width4 {
317 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
318 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
319 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
320 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
327 interrupts = <GIC_PPI 11 0xf04>;
331 interrupts = <GIC_PPI 13 0xf04>;
335 compatible = "rockchip,rk3188-i2c";
336 pinctrl-names = "default";
337 pinctrl-0 = <&i2c0_xfer>;
341 compatible = "rockchip,rk3188-i2c";
342 pinctrl-names = "default";
343 pinctrl-0 = <&i2c1_xfer>;
347 compatible = "rockchip,rk3188-i2c";
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c2_xfer>;
353 compatible = "rockchip,rk3188-i2c";
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c3_xfer>;
359 compatible = "rockchip,rk3188-i2c";
360 pinctrl-names = "default";
361 pinctrl-0 = <&i2c4_xfer>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pwm0_out>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&pwm1_out>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pwm2_out>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pwm3_out>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&uart0_xfer>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&uart1_xfer>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&uart2_xfer>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&uart3_xfer>;
405 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";