arch/arm/boot/dts/rk3188.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4
   5 / {
   6         compatible = "rockchip,rk3188";
   7         interrupt-parent = <&gic>;
   8
   9         cpus {
  10                 #address-cells = <1>;
  11                 #size-cells = <0>;
  12
  13                 cpu@0 {
  14                         device_type = "cpu";
  15                         compatible = "arm,cortex-a9";
  16                         reg = <0>;
  17                 };
  18                 cpu@1 {
  19                         device_type = "cpu";
  20                         compatible = "arm,cortex-a9";
  21                         reg = <1>;
  22                 };
  23                 cpu@2 {
  24                         device_type = "cpu";
  25                         compatible = "arm,cortex-a9";
  26                         reg = <2>;
  27                 };
  28                 cpu@3 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a9";
  31                         reg = <3>;
  32                 };
  33         };
  34
  35         twd-wdt@1013c620 {
  36                 compatible = "arm,cortex-a9-twd-wdt";
  37                 reg = <0x1013c620 0x20>;
  38                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  39         };
  40
  41         gic: interrupt-controller@1013d000 {
  42                 compatible = "arm,cortex-a9-gic";
  43                 interrupt-controller;
  44                 #interrupt-cells = <3>;
  45                 reg = <0x1013d000 0x1000>,
  46                       <0x1013c100 0x0100>;
  47         };
  48
  49         L2: cache-controller@10138000 {
  50                 compatible = "arm,pl310-cache";
  51                 reg = <0x10138000 0x1000>;
  52                 cache-unified;
  53                 cache-level = <2>;
  54                 arm,tag-latency = <1 1 1>;
  55                 arm,data-latency = <2 3 1>;
  56                 prefetch-ctrl = <0x70000003>;
  57                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  58                 power-ctrl = <0x3>;
  59 /*
  60                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  61                 (0x1 << 25) |   // Round-robin replacement
  62                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  63                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  64                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  65 */
  66                 aux-ctrl = <0x72000001 (~0x72000001)>;
  67         };
  68
  69         cpu_axi_bus: cpu_axi_bus@10128000 {
  70                 compatible = "rockchip,cpu_axi_bus";
  71                 reg = <0x10128000 0x8000>;
  72                 qos {
  73                         dmac {
  74                                 offset = <0x1000>;
  75                                 priority = <0 0>;
  76                         };
  77                         cpu0 {
  78                                 offset = <0x2000>;
  79                                 priority = <0 0>;
  80                         };
  81                         cpu1r {
  82                                 offset = <0x2080>;
  83                                 priority = <0 0>;
  84                         };
  85                         cpu1w {
  86                                 offset = <0x2100>;
  87                                 priority = <0 0>;
  88                         };
  89                         peri {
  90                                 offset = <0x4000>;
  91                                 priority = <2 2>;
  92                         };
  93                         gpu {
  94                                 offset = <0x5000>;
  95                                 priority = <2 1>;
  96                         };
  97                         vpu {
  98                                 offset = <0x6000>;
  99                         };
 100                         vop0 {
 101                                 offset = <0x7000>;
 102                                 priority = <3 3>;
 103                         };
 104                         cif0 {
 105                                 offset = <0x7080>;
 106                         };
 107                         ipp {
 108                                 offset = <0x7100>;
 109                         };
 110                         vop1 {
 111                                 offset = <0x7180>;
 112                                 priority = <3 3>;
 113                         };
 114                         cif1 {
 115                                 offset = <0x7200>;
 116                         };
 117                         rga {
 118                                 offset = <0x7280>;
 119                         };
 120                 };
 121         };
 122
 123         bootrom@10120000 {
 124                 compatible = "rockchip,bootrom";
 125                 reg = <0x10120000 0x4000>;
 126         };
 127
 128         bootram@10080000 {
 129                 compatible = "rockchip,bootram";
 130                 reg = <0x10080000 0x20>; /* 32 bytes */
 131         };
 132
 133         sram@10080020 {
 134                 compatible = "mmio-sram";
 135                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 136                 map-exec;
 137         };
 138
 139         pmu@20004000 {
 140                 compatible = "rockchip,pmu";
 141                 reg = <0x20004000 0x4000>;
 142         };
 143
 144         timer@200380a0 {
 145                 compatible = "rockchip,timer";
 146                 reg = <0x200380a0 0x20>;
 147                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 148         };
 149
 150         timer@20038000 {
 151                 compatible = "rockchip,timer";
 152                 reg = <0x20038000 0x20>;
 153                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 154         };
 155
 156         timer@20038020 {
 157                 compatible = "rockchip,timer";
 158                 reg = <0x20038020 0x20>;
 159                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 160         };
 161
 162         timer@20038060 {
 163                 compatible = "rockchip,timer";
 164                 reg = <0x20038060 0x20>;
 165                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 166         };
 167
 168         timer@20038080 {
 169                 compatible = "rockchip,timer";
 170                 reg = <0x20038080 0x20>;
 171                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 172         };
 173
 174         uart0: serial@10124000 {
 175                 compatible = "rockchip,serial";
 176                 reg = <0x10124000 0x100>;
 177                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 178                 clock-frequency = <24000000>;
 179                 reg-shift = <2>;
 180                 reg-io-width = <4>;
 181                 id = <0>;
 182                 status = "disabled";
 183         };
 184
 185         uart1: serial@10126000 {
 186                 compatible = "rockchip,serial";
 187                 reg = <0x10126000 0x100>;
 188                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 189                 clock-frequency = <24000000>;
 190                 reg-shift = <2>;
 191                 reg-io-width = <4>;
 192                 id = <1>;
 193                 status = "disabled";
 194         };
 195
 196         uart2: serial@20064000 {
 197                 compatible = "rockchip,serial";
 198                 reg = <0x20064000 0x100>;
 199                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 200                 clock-frequency = <24000000>;
 201                 current-speed = <115200>;
 202                 reg-shift = <2>;
 203                 reg-io-width = <4>;
 204                 id = <2>;
 205                 status = "disabled";
 206         };
 207
 208         uart3: serial@20068000 {
 209                 compatible = "rockchip,serial";
 210                 reg = <0x20068000 0x100>;
 211                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 212                 clock-frequency = <24000000>;
 213                 reg-shift = <2>;
 214                 reg-io-width = <4>;
 215                 id = <3>;
 216                 status = "disabled";
 217         };
 218 };