arch/arm/boot/dts/rk3188.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4
   5 / {
   6         compatible = "rockchip,rk3188";
   7         interrupt-parent = <&gic>;
   8
   9         cpus {
  10                 #address-cells = <1>;
  11                 #size-cells = <0>;
  12
  13                 cpu@0 {
  14                         device_type = "cpu";
  15                         compatible = "arm,cortex-a9";
  16                         reg = <0>;
  17                 };
  18                 cpu@1 {
  19                         device_type = "cpu";
  20                         compatible = "arm,cortex-a9";
  21                         reg = <1>;
  22                 };
  23                 cpu@2 {
  24                         device_type = "cpu";
  25                         compatible = "arm,cortex-a9";
  26                         reg = <2>;
  27                 };
  28                 cpu@3 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a9";
  31                         reg = <3>;
  32                 };
  33         };
  34
  35         twd-wdt@1013c620 {
  36                 compatible = "arm,cortex-a9-twd-wdt";
  37                 reg = <0x1013c620 0x20>;
  38                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  39         };
  40
  41         gic: interrupt-controller@1013d000 {
  42                 compatible = "arm,cortex-a9-gic";
  43                 interrupt-controller;
  44                 #interrupt-cells = <3>;
  45                 reg = <0x1013d000 0x1000>,
  46                       <0x1013c100 0x0100>;
  47         };
  48
  49         L2: cache-controller@10138000 {
  50                 compatible = "arm,pl310-cache";
  51                 reg = <0x10138000 0x1000>;
  52                 cache-unified;
  53                 cache-level = <2>;
  54                 arm,tag-latency = <1 1 1>;
  55                 arm,data-latency = <2 3 1>;
  56         };
  57
  58         sram@10080000 {
  59                 compatible = "rockchip,sram";
  60                 reg = <0x10080000 0x8000>;
  61         };
  62
  63         pmu@20004000 {
  64                 compatible = "rockchip,pmu";
  65                 reg = <0x20004000 0x4000>;
  66         };
  67
  68         timer@200380a0 {
  69                 compatible = "rockchip,timer";
  70                 reg = <0x200380a0 0x20>;
  71                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  72         };
  73
  74         timer@20038000 {
  75                 compatible = "rockchip,timer";
  76                 reg = <0x20038000 0x20>;
  77                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  78         };
  79
  80         timer@20038020 {
  81                 compatible = "rockchip,timer";
  82                 reg = <0x20038020 0x20>;
  83                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  84         };
  85
  86         timer@20038060 {
  87                 compatible = "rockchip,timer";
  88                 reg = <0x20038060 0x20>;
  89                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
  90         };
  91
  92         timer@20038080 {
  93                 compatible = "rockchip,timer";
  94                 reg = <0x20038080 0x20>;
  95                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  96         };
  97
  98         uart0: serial@10124000 {
  99                 compatible = "snps,dw-apb-uart";
 100                 reg = <0x10124000 0x100>;
 101                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 102                 clock-frequency = <24000000>;
 103                 reg-shift = <2>;
 104                 reg-io-width = <4>;
 105                 status = "disabled";
 106         };
 107
 108         uart1: serial@10126000 {
 109                 compatible = "snps,dw-apb-uart";
 110                 reg = <0x10126000 0x100>;
 111                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 112                 clock-frequency = <24000000>;
 113                 reg-shift = <2>;
 114                 reg-io-width = <4>;
 115                 status = "disabled";
 116         };
 117
 118         uart2: serial@20064000 {
 119                 compatible = "snps,dw-apb-uart";
 120                 reg = <0x20064000 0x100>;
 121                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 122                 clock-frequency = <24000000>;
 123                 reg-shift = <2>;
 124                 reg-io-width = <4>;
 125                 status = "disabled";
 126         };
 127
 128         uart3: serial@20068000 {
 129                 compatible = "snps,dw-apb-uart";
 130                 reg = <0x20068000 0x100>;
 131                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 132                 clock-frequency = <24000000>;
 133                 reg-shift = <2>;
 134                 reg-io-width = <4>;
 135                 status = "disabled";
 136         };
 137 };