arch/arm/boot/dts/rk3228-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014-2015 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3228.h>
  15
  16 /{
  17         clocks {
  18                 compatible = "rockchip,rk-clocks";
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges = <0x0  0x110e0000  0x1000>;
  22
  23                 fixed_rate_cons {
  24                         compatible = "rockchip,rk-fixed-rate-cons";
  25
  26                         xin24m: xin24m {
  27                                 compatible = "rockchip,rk-fixed-clock";
  28                                 clock-output-names = "xin24m";
  29                                 clock-frequency = <24000000>;
  30                                 #clock-cells = <0>;
  31                         };
  32
  33                         xin12m: xin12m {
  34                                 compatible = "rockchip,rk-fixed-clock";
  35                                 clocks = <&xin24m>;
  36                                 clock-output-names = "xin12m";
  37                                 clock-frequency = <12000000>;
  38                                 #clock-cells = <0>;
  39                         };
  40
  41                         hdmiphy_out: hdmiphy_out {
  42                                 compatible = "rockchip,rk-fixed-clock";
  43                                 clock-output-names = "hdmiphy_out";
  44                                 clock-frequency = <594000000>;
  45                                 #clock-cells = <0>;
  46                         };
  47
  48                         usbphy0_480m: usbphy0_480m {
  49                                 compatible = "rockchip,rk-fixed-clock";
  50                                 clock-output-names = "usbphy0_480m";
  51                                 clock-frequency = <480000000>;
  52                                 #clock-cells = <0>;
  53                         };
  54
  55                         usbphy1_480m: usbphy1_480m {
  56                                 compatible = "rockchip,rk-fixed-clock";
  57                                 clock-output-names = "usbphy1_480m";
  58                                 clock-frequency = <480000000>;
  59                                 #clock-cells = <0>;
  60                         };
  61
  62                         jtag_clkin: jtag_clkin {
  63                                 compatible = "rockchip,rk-fixed-clock";
  64                                 clock-output-names = "jtag_clkin";
  65                                 clock-frequency = <0>;
  66                                 #clock-cells = <0>;
  67                         };
  68
  69                         dummy: dummy {
  70                                 compatible = "rockchip,rk-fixed-clock";
  71                                 clock-output-names = "dummy";
  72                                 clock-frequency = <0>;
  73                                 #clock-cells = <0>;
  74                         };
  75
  76                         gmac_clkin: gmac_clkin {
  77                                 compatible = "rockchip,rk-fixed-clock";
  78                                 clock-output-names = "gmac_clkin";
  79                                 clock-frequency = <0>;
  80                                 #clock-cells = <0>;
  81                         };
  82
  83                         phy_50m_out: phy_50m_out {
  84                                 compatible = "rockchip,rk-fixed-clock";
  85                                 clock-output-names = "phy_50m_out";
  86                                 clock-frequency = <0>;
  87                                 #clock-cells = <0>;
  88                         };
  89
  90                         phy_rx_out: phy_rx_out {
  91                                 compatible = "rockchip,rk-fixed-clock";
  92                                 clock-output-names = "phy_rx_out";
  93                                 clock-frequency = <0>;
  94                                 #clock-cells = <0>;
  95                         };
  96
  97                         phy_tx_out: phy_tx_out {
  98                                 compatible = "rockchip,rk-fixed-clock";
  99                                 clock-output-names = "phy_tx_out";
 100                                 clock-frequency = <0>;
 101                                 #clock-cells = <0>;
 102                         };
 103
 104                         clkin_hsadc_tsp: clkin_hsadc_tsp {
 105                                 compatible = "rockchip,rk-fixed-clock";
 106                                 clock-output-names = "clkin_hsadc_tsp";
 107                                 clock-frequency = <0>;
 108                                 #clock-cells = <0>;
 109                         };
 110
 111                         i2s_clkin: i2s_clkin {
 112                                 compatible = "rockchip,rk-fixed-clock";
 113                                 clock-output-names = "i2s_clkin";
 114                                 clock-frequency = <0>;
 115                                 #clock-cells = <0>;
 116                         };
 117                 };
 118
 119                 fixed_factor_cons {
 120                         compatible = "rockchip,rk-fixed-factor-cons";
 121
 122                         hclk_rkvdec: hclk_rkvdec {
 123                                 compatible = "rockchip,rk-fixed-factor-clock";
 124                                 clocks = <&aclk_rkvdec>;
 125                                 clock-output-names = "hclk_rkvdec";
 126                                 clock-div = <4>;
 127                                 clock-mult = <1>;
 128                                 #clock-cells = <0>;
 129                         };
 130
 131                         hclk_vpu: hclk_vpu {
 132                                 compatible = "rockchip,rk-fixed-factor-clock";
 133                                 clocks = <&aclk_vpu>;
 134                                 clock-output-names = "hclk_vpu";
 135                                 clock-div = <4>;
 136                                 clock-mult = <1>;
 137                                 #clock-cells = <0>;
 138                         };
 139
 140                         xin32k_out: xin32k_out {
 141                                 compatible = "rockchip,rk-fixed-clock";
 142                                 clocks = <&clk_hdmi_cec>;
 143                                 clock-output-names = "xin32k_out";
 144                                 clock-div = <1>;
 145                                 clock-mult = <1>;
 146                                 #clock-cells = <0>;
 147                         };
 148
 149                 };
 150
 151                 clock_regs {
 152                         compatible = "rockchip,rk-clock-regs";
 153                         #address-cells = <1>;
 154                         #size-cells = <1>;
 155                         reg = <0x0000 0x1000>;
 156                         ranges;
 157
 158                         /* PLL control regs */
 159                         pll_cons {
 160                                 compatible = "rockchip,rk-pll-cons";
 161                                 #address-cells = <1>;
 162                                 #size-cells = <1>;
 163                                 ranges;
 164
 165                                 clk_apll: pll-clk@0000 {
 166                                         compatible = "rockchip,rk3188-pll-clk";
 167                                         reg = <0x0000 0x10>;
 168                                         mode-reg = <0x0040 0>;
 169                                         status-reg = <0x04 10>;
 170                                         clocks = <&xin24m>;
 171                                         clock-output-names = "clk_apll";
 172                                         rockchip,pll-type = <CLK_PLL_3036_APLL>;
 173                                         #clock-cells = <0>;
 174                                 };
 175
 176                                 clk_dpll: pll-clk@000c {
 177                                         compatible = "rockchip,rk3188-pll-clk";
 178                                         reg = <0x000c 0x10>;
 179                                         mode-reg = <0x0040 4>;
 180                                         status-reg = <0x10 10>;
 181                                         clocks = <&xin24m>;
 182                                         clock-output-names = "clk_dpll";
 183                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 184                                         #clock-cells = <0>;
 185                                 };
 186
 187
 188                                 clk_cpll: pll-clk@0018 {
 189                                         compatible = "rockchip,rk3188-pll-clk";
 190                                         reg = <0x0018 0x10>;
 191                                         mode-reg = <0x0040 8>;
 192                                         status-reg = <0x1c 10>;
 193                                         clocks = <&xin24m>;
 194                                         clock-output-names = "clk_cpll";
 195                                         rockchip,pll-type = <CLK_PLL_312XPLUS>;
 196                                         #clock-cells = <0>;
 197                                         #clock-init-cells = <1>;
 198                                 };
 199
 200                                 clk_gpll: pll-clk@0024 {
 201                                         compatible = "rockchip,rk3188-pll-clk";
 202                                         reg = <0x0024 0x10>;
 203                                         mode-reg = <0x0040 12>;
 204                                         status-reg = <0x28 10>;
 205                                         clocks = <&xin24m>;
 206                                         clock-output-names = "clk_gpll";
 207                                         rockchip,pll-type = <CLK_PLL_312XPLUS>;
 208                                         #clock-cells = <0>;
 209                                         #clock-init-cells = <1>;
 210                                 };
 211                         };
 212
 213                         /* Select control regs */
 214                         clk_sel_cons {
 215                                 compatible = "rockchip,rk-sel-cons";
 216                                 #address-cells = <1>;
 217                                 #size-cells = <1>;
 218                                 ranges;
 219
 220                                 clk_sel_con0: sel-con@0044 {
 221                                         compatible = "rockchip,rk3188-selcon";
 222                                         reg = <0x0044 0x4>;
 223                                         #address-cells = <1>;
 224                                         #size-cells = <1>;
 225
 226                                         clk_core_div: clk_core_div {
 227                                                 compatible = "rockchip,rk3188-div-con";
 228                                                 rockchip,bits = <0 5>;
 229                                                 clocks = <&clk_core>;
 230                                                 clock-output-names = "clk_core";
 231                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 232                                                 #clock-cells = <0>;
 233                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 234                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 235                                                                         CLK_SET_RATE_NO_REPARENT)>;
 236                                         };
 237
 238                                         /* 5 reserved */
 239
 240                                         clk_core: clk_core_mux {
 241                                                 compatible = "rockchip,rk3188-mux-con";
 242                                                 rockchip,bits = <6 2>;
 243                                                 clocks = <&clk_apll>, <&clk_gpll>, <&clk_dpll>;
 244                                                 clock-output-names = "clk_core";
 245                                                 #clock-cells = <0>;
 246                                                 #clock-init-cells = <1>;
 247                                         };
 248
 249                                         aclk_bus: aclk_bus_div {
 250                                                 compatible = "rockchip,rk3188-div-con";
 251                                                 rockchip,bits = <8 5>;
 252                                                 clocks = <&aclk_bus_mux>;
 253                                                 clock-output-names = "aclk_bus";
 254                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 255                                                 #clock-cells = <0>;
 256                                                 #clock-init-cells = <1>;
 257                                         };
 258
 259                                         aclk_bus_mux: aclk_bus_mux {
 260                                                 compatible = "rockchip,rk3188-mux-con";
 261                                                 rockchip,bits = <13 2>;
 262                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>;
 263                                                 clock-output-names = "aclk_bus";
 264                                                 #clock-cells = <0>;
 265                                                 #clock-init-cells = <1>;
 266                                         };
 267
 268                                         /* 15 reserved */
 269
 270                                 };
 271
 272                                 clk_sel_con1: sel-con@0048 {
 273                                         compatible = "rockchip,rk3188-selcon";
 274                                         reg = <0x0048 0x4>;
 275                                         #address-cells = <1>;
 276                                         #size-cells = <1>;
 277
 278                                         pclk_dbg:  pclk_dbg_div {
 279                                                 compatible = "rockchip,rk3188-div-con";
 280                                                 rockchip,bits = <0 4>;
 281                                                 clocks = <&clk_core>;
 282                                                 clock-output-names = "pclk_dbg";
 283                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 284                                                 #clock-cells = <0>;
 285                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 286                                         };
 287
 288                                         aclk_core: aclk_core_div {
 289                                                 compatible = "rockchip,rk3188-div-con";
 290                                                 rockchip,bits = <4 3>;
 291                                                 clocks = <&clk_core>;
 292                                                 clock-output-names = "aclk_core";
 293                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 294                                                 #clock-cells = <0>;
 295                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 296                                         };
 297
 298                                         /* 7 reserved */
 299
 300                                         hclk_bus: hclk_bus_div {
 301                                                 compatible = "rockchip,rk3188-div-con";
 302                                                 rockchip,bits = <8 2>;
 303                                                 clocks = <&aclk_bus>;
 304                                                 clock-output-names = "hclk_bus";
 305                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 306                                                 #clock-cells = <0>;
 307                                                 #clock-init-cells = <1>;
 308                                         };
 309
 310                                         /* 11:10 reserved */
 311
 312                                         pclk_bus: pclk_bus_div {
 313                                                 compatible = "rockchip,rk3188-div-con";
 314                                                 rockchip,bits = <12 3>;
 315                                                 clocks = <&aclk_bus>;
 316                                                 clock-output-names = "pclk_bus";
 317                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 318                                                 #clock-cells = <0>;
 319                                                 #clock-init-cells = <1>;
 320                                         };
 321
 322                                         /* 15 reserved */
 323
 324                                 };
 325
 326                                 clk_sel_con2: sel-con@004c {
 327                                         compatible = "rockchip,rk3188-selcon";
 328                                         reg = <0x004c 0x4>;
 329                                         #address-cells = <1>;
 330                                         #size-cells = <1>;
 331
 332                                         hclk_vio: hclk_vio_div {
 333                                                 compatible = "rockchip,rk3188-div-con";
 334                                                 rockchip,bits = <0 5>;
 335                                                 clocks = <&aclk_iep>;
 336                                                 clock-output-names = "hclk_vio";
 337                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 338                                                 #clock-cells = <0>;
 339                                                 #clock-init-cells = <1>;
 340                                         };
 341
 342                                         /* 7:5 reserved */
 343
 344                                         clk_nandc_div: clk_nandc_div {
 345                                                 compatible = "rockchip,rk3188-div-con";
 346                                                 rockchip,bits = <8 5>;
 347                                                 clocks = <&clk_nandc>;
 348                                                 clock-output-names = "clk_nandc";
 349                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 350                                                 #clock-cells = <0>;
 351                                                 rockchip,clkops-idx =
 352                                                         <CLKOPS_RATE_MUX_DIV>;
 353                                         };
 354
 355                                         /* 13: reserved */
 356
 357                                         clk_nandc: clk_nandc_mux {
 358                                                 compatible = "rockchip,rk3188-mux-con";
 359                                                 rockchip,bits = <14 1>;
 360                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 361                                                 clock-output-names = "clk_nandc";
 362                                                 #clock-cells = <0>;
 363                                                 #clock-init-cells = <1>;
 364                                         };
 365
 366                                         /* 15 reserved */
 367
 368                                 };
 369
 370                                 clk_sel_con3: sel-con@0050 {
 371                                         compatible = "rockchip,rk3188-selcon";
 372                                         reg = <0x0050 0x4>;
 373                                         #address-cells = <1>;
 374                                         #size-cells = <1>;
 375
 376                                         clk_i2s1_pll_div: clk_i2s1_pll_div {
 377                                                 compatible = "rockchip,rk3188-div-con";
 378                                                 rockchip,bits = <0 7>;
 379                                                 clocks = <&clk_i2s1_pll>;
 380                                                 clock-output-names = "clk_i2s1_pll";
 381                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 382                                                 #clock-cells = <0>;
 383                                                 rockchip,clkops-idx =
 384                                                         <CLKOPS_RATE_MUX_DIV>;
 385                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 386                                         };
 387
 388                                         /* 7: reserved */
 389
 390                                         clk_i2s1: clk_i2s1_mux {
 391                                                 compatible = "rockchip,rk3188-mux-con";
 392                                                 rockchip,bits = <8 2>;
 393                                                 clocks = <&clk_i2s1_pll_div>, <&i2s1_frac>, <&i2s_clkin>, <&xin12m>;
 394                                                 clock-output-names = "clk_i2s1";
 395                                                 #clock-cells = <0>;
 396                                                 rockchip,clkops-idx =
 397                                                         <CLKOPS_RATE_RK3288_I2S>;
 398                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 399                                         };
 400
 401                                         /* 11:10: reserved */
 402
 403                                         clk_i2s1_out: clk_i2s1_out_mux {
 404                                                 compatible = "rockchip,rk3188-mux-con";
 405                                                 rockchip,bits = <12 1>;
 406                                                 clocks = <&clk_i2s1>, <&xin12m>;
 407                                                 clock-output-names = "i2s_clkout";
 408                                                 #clock-cells = <0>;
 409                                         };
 410
 411                                         /* 14:13: reserved */
 412
 413                                         clk_i2s1_pll: i2s1_pll_mux {
 414                                                 compatible = "rockchip,rk3188-mux-con";
 415                                                 rockchip,bits = <15 1>;
 416                                                 clocks = <&clk_cpll>,<&clk_gpll>;
 417                                                 clock-output-names = "clk_i2s1_pll";
 418                                                 #clock-cells = <0>;
 419                                                 #clock-init-cells = <1>;
 420                                         };
 421
 422                                 };
 423
 424                                 clk_sel_con4: sel-con@0054 {
 425                                         compatible = "rockchip,rk3188-selcon";
 426                                         reg = <0x0054 0x4>;
 427                                         #address-cells = <1>;
 428                                         #size-cells = <1>;
 429
 430                                         testclk_div: testclk_div {
 431                                                 compatible = "rockchip,rk3188-div-con";
 432                                                 rockchip,bits = <0 5>;
 433                                                 clocks = <&testclk>;
 434                                                 clock-output-names = "testclk";
 435                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 436                                                 #clock-cells = <0>;
 437                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 438                                         };
 439
 440                                         /* 7:5 reserved */
 441
 442                                         clk_24m_div: clk_24m_div {
 443                                                 compatible = "rockchip,rk3188-div-con";
 444                                                 rockchip,bits = <8 5>;
 445                                                 clocks = <&xin24m>;
 446                                                 clock-output-names = "clk_24m";
 447                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 448                                                 #clock-cells = <0>;
 449                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 450                                         };
 451
 452                                         /* 15:13 reserved */
 453
 454                                 };
 455
 456                                 clk_sel_con5: sel-con@0058 {
 457                                         compatible = "rockchip,rk3188-selcon";
 458                                         reg = <0x0058 0x4>;
 459                                         #address-cells = <1>;
 460                                         #size-cells = <1>;
 461
 462                                         clk_mac_pll_div: clk_mac_pll_div {
 463                                                 compatible = "rockchip,rk3188-div-con";
 464                                                 rockchip,bits = <0 5>;
 465                                                 clocks = <&clk_mac_pll>;
 466                                                 clock-output-names = "clk_mac_pll";
 467                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 468                                                 #clock-cells = <0>;
 469                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 470                                         };
 471
 472                                         clk_mac: clk_mac_mux {
 473                                                 compatible = "rockchip,rk3188-mux-con";
 474                                                 rockchip,bits = <5 1>;
 475                                                 clocks = <&clk_mac_pll>, <&rmii_clkin>;
 476                                                 clock-output-names = "clk_mac";
 477                                                 #clock-cells = <0>;
 478                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 479                                                 #clock-init-cells = <1>;
 480                                         };
 481
 482                                         /* 6 reserved */
 483
 484                                         clk_mac_pll: clk_mac_pll_mux {
 485                                                 compatible = "rockchip,rk3188-mux-con";
 486                                                 rockchip,bits = <7 1>;
 487                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 488                                                 clock-output-names = "clk_mac_pll";
 489                                                 #clock-cells = <0>;
 490                                         };
 491
 492                                         clk_gmac_div: clk_gmac_div {
 493                                                 compatible = "rockchip,rk3188-div-con";
 494                                                 rockchip,bits = <8 5>;
 495                                                 clocks = <&clk_gmac>;
 496                                                 clock-output-names = "clk_gmac";
 497                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 498                                                 #clock-cells = <0>;
 499                                                 rockchip,clkops-idx =
 500                                                         <CLKOPS_RATE_MUX_DIV>;
 501                                         };
 502
 503                                         /* 14:13 reserved */
 504
 505                                         clk_gmac: clk_gmac_mux {
 506                                                 compatible = "rockchip,rk3188-mux-con";
 507                                                 rockchip,bits = <15 1>;
 508                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 509                                                 clock-output-names = "clk_gmac";
 510                                                 #clock-cells = <0>;
 511                                                 #clock-init-cells = <1>;
 512                                         };
 513
 514                                 };
 515
 516                                 clk_sel_con6: sel-con@005c {
 517                                         compatible = "rockchip,rk3188-selcon";
 518                                         reg = <0x005c 0x4>;
 519                                         #address-cells = <1>;
 520                                         #size-cells = <1>;
 521
 522                                         spdif_div: spdif_div {
 523                                                 compatible = "rockchip,rk3188-div-con";
 524                                                 rockchip,bits = <0 7>;
 525                                                 clocks = <&clk_spdif_pll>;
 526                                                 clock-output-names = "clk_spdif_pll";
 527                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 528                                                 #clock-cells = <0>;
 529                                                 rockchip,clkops-idx =
 530                                                         <CLKOPS_RATE_MUX_DIV>;
 531                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 532                                         };
 533
 534                                         /* 7 reserved */
 535
 536                                         clk_spdif: spdif_mux {
 537                                                 compatible = "rockchip,rk3188-mux-con";
 538                                                 rockchip,bits = <8 2>;
 539                                                 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
 540                                                 clock-output-names = "clk_spdif";
 541                                                 #clock-cells = <0>;
 542                                                 rockchip,clkops-idx =
 543                                                         <CLKOPS_RATE_RK3288_I2S>;
 544                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 545                                         };
 546
 547                                         /* 14:10 reserved */
 548
 549                                         clk_spdif_pll: spdif_pll_mux {
 550                                                 compatible = "rockchip,rk3188-mux-con";
 551                                                 rockchip,bits = <15 1>;
 552                                                 clocks = <&clk_cpll>,<&clk_gpll>;
 553                                                 clock-output-names = "clk_spdif_pll";
 554                                                 #clock-cells = <0>;
 555                                                 #clock-init-cells = <1>;
 556                                         };
 557
 558                                 };
 559
 560                                 clk_sel_con7: sel-con@0060 {
 561                                         compatible = "rockchip,rk3188-selcon";
 562                                         reg = <0x0060 0x4>;
 563                                         #address-cells = <1>;
 564                                         #size-cells = <1>;
 565
 566                                         i2s1_frac: i2s1_frac {
 567                                                 compatible = "rockchip,rk3188-frac-con";
 568                                                 clocks = <&clk_i2s1_pll_div>;
 569                                                 clock-output-names = "i2s1_frac";
 570                                                 /* numerator    denominator */
 571                                                 rockchip,bits = <0 32>;
 572                                                 rockchip,clkops-idx =
 573                                                         <CLKOPS_RATE_FRAC>;
 574                                                 #clock-cells = <0>;
 575                                         };
 576
 577                                 };
 578
 579                                 clk_sel_con8: sel-con@0064 {
 580                                         compatible = "rockchip,rk3188-selcon";
 581                                         reg = <0x0064 0x4>;
 582                                         #address-cells = <1>;
 583                                         #size-cells = <1>;
 584
 585                                         i2s0_frac: i2s0_frac {
 586                                                 compatible = "rockchip,rk3188-frac-con";
 587                                                 clocks = <&clk_i2s0_pll_div>;
 588                                                 clock-output-names = "i2s0_frac";
 589                                                 /* numerator    denominator */
 590                                                 rockchip,bits = <0 32>;
 591                                                 rockchip,clkops-idx =
 592                                                         <CLKOPS_RATE_FRAC>;
 593                                                 #clock-cells = <0>;
 594                                         };
 595
 596                                 };
 597
 598                                 clk_sel_con9: sel-con@0068 {
 599                                         compatible = "rockchip,rk3188-selcon";
 600                                         reg = <0x0068 0x4>;
 601                                         #address-cells = <1>;
 602                                         #size-cells = <1>;
 603
 604                                         clk_i2s0_pll_div: clk_i2s0_pll_div {
 605                                                 compatible = "rockchip,rk3188-div-con";
 606                                                 rockchip,bits = <0 7>;
 607                                                 clocks = <&clk_i2s0_pll>;
 608                                                 clock-output-names = "clk_i2s0_pll";
 609                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 610                                                 #clock-cells = <0>;
 611                                                 rockchip,clkops-idx =
 612                                                         <CLKOPS_RATE_MUX_DIV>;
 613                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 614                                         };
 615
 616                                         /* 7: reserved */
 617
 618                                         clk_i2s0: clk_i2s0_mux {
 619                                                 compatible = "rockchip,rk3188-mux-con";
 620                                                 rockchip,bits = <8 2>;
 621                                                 clocks = <&clk_i2s0_pll_div>, <&i2s0_frac>, <&i2s_clkin>, <&xin12m>;
 622                                                 clock-output-names = "clk_i2s0";
 623                                                 #clock-cells = <0>;
 624                                                 rockchip,clkops-idx =
 625                                                         <CLKOPS_RATE_RK3288_I2S>;
 626                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 627                                         };
 628
 629                                         /* 14:10: reserved */
 630
 631                                         clk_i2s0_pll: i2s0_pll_mux {
 632                                                 compatible = "rockchip,rk3188-mux-con";
 633                                                 rockchip,bits = <15 1>;
 634                                                 clocks = <&clk_cpll>,<&clk_gpll>;
 635                                                 clock-output-names = "clk_i2s0_pll";
 636                                                 #clock-cells = <0>;
 637                                                 #clock-init-cells = <1>;
 638                                         };
 639
 640                                 };
 641
 642                                 clk_sel_con10: sel-con@006c {
 643                                         compatible = "rockchip,rk3188-selcon";
 644                                         reg = <0x006c 0x4>;
 645                                         #address-cells = <1>;
 646                                         #size-cells = <1>;
 647
 648                                         aclk_peri_div: aclk_peri_div {
 649                                                 compatible = "rockchip,rk3188-div-con";
 650                                                 rockchip,bits = <0 5>;
 651                                                 clocks = <&aclk_peri>;
 652                                                 clock-output-names = "aclk_peri";
 653                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 654                                                 #clock-cells = <0>;
 655                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 656                                         };
 657
 658                                         /* 7:5: reserved */
 659
 660                                         hclk_peri: hclk_peri_div {
 661                                                 compatible = "rockchip,rk3188-div-con";
 662                                                 rockchip,bits = <8 2>;
 663                                                 clocks = <&aclk_peri>;
 664                                                 clock-output-names = "hclk_peri";
 665                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 666                                                 rockchip,div-relations =
 667                                                                 <0x0 1
 668                                                                  0x1 2
 669                                                                  0x2 4>;
 670                                                 #clock-cells = <0>;
 671                                                 #clock-init-cells = <1>;
 672                                         };
 673
 674                                         aclk_peri: aclk_peri_mux {
 675                                                 compatible = "rockchip,rk3188-mux-con";
 676                                                 rockchip,bits = <10 2>;
 677                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>;
 678                                                 clock-output-names = "aclk_peri";
 679                                                 #clock-cells = <0>;
 680                                                 #clock-init-cells = <1>;
 681                                         };
 682
 683                                         pclk_peri: pclk_peri_div {
 684                                                 compatible = "rockchip,rk3188-div-con";
 685                                                 rockchip,bits = <12 2>;
 686                                                 clocks = <&aclk_peri>;
 687                                                 clock-output-names = "pclk_peri";
 688                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 689                                                 rockchip,div-relations =
 690                                                                 <0x0 1
 691                                                                  0x1 2
 692                                                                  0x2 4
 693                                                                  0x3 8>;
 694                                                 #clock-cells = <0>;
 695                                                 #clock-init-cells = <1>;
 696                                         };
 697
 698                                         /* 15: reserved */
 699
 700                                 };
 701
 702                                 clk_sel_con11: sel-con@0070 {
 703                                         compatible = "rockchip,rk3188-selcon";
 704                                         reg = <0x0070 0x4>;
 705                                         #address-cells = <1>;
 706                                         #size-cells = <1>;
 707
 708                                         clk_sdmmc0_div: clk_sdmmc0_div {
 709                                                 compatible = "rockchip,rk3188-div-con";
 710                                                 rockchip,bits = <0 8>;
 711                                                 clocks = <&clk_sdmmc0>;
 712                                                 clock-output-names = "clk_sdmmc0";
 713                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 714                                                 #clock-cells = <0>;
 715                                                 rockchip,clkops-idx =
 716                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 717                                         };
 718
 719                                         clk_sdmmc0: clk_sdmmc0_mux {
 720                                                 compatible = "rockchip,rk3188-mux-con";
 721                                                 rockchip,bits = <8 2>;
 722                                                 clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>;
 723                                                 clock-output-names = "clk_sdmmc0";
 724                                                 #clock-cells = <0>;
 725                                                 #clock-init-cells = <1>;
 726                                         };
 727
 728                                         clk_sdio: clk_sdio_mux {
 729                                                 compatible = "rockchip,rk3188-mux-con";
 730                                                 rockchip,bits = <10 2>;
 731                                                 clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>;
 732                                                 clock-output-names = "clk_sdio";
 733                                                 #clock-cells = <0>;
 734                                                 #clock-init-cells = <1>;
 735                                         };
 736
 737                                         clk_emmc: clk_emmc_mux {
 738                                                 compatible = "rockchip,rk3188-mux-con";
 739                                                 rockchip,bits = <12 2>;
 740                                                 clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>;
 741                                                 clock-output-names = "clk_emmc";
 742                                                 #clock-cells = <0>;
 743                                                 #clock-init-cells = <1>;
 744                                         };
 745
 746                                         /* 15:14 reserved */
 747
 748                                 };
 749
 750                                 clk_sel_con12: sel-con@0074 {
 751                                         compatible = "rockchip,rk3188-selcon";
 752                                         reg = <0x0074 0x4>;
 753                                         #address-cells = <1>;
 754                                         #size-cells = <1>;
 755
 756                                         clk_sdio_div: clk_sdio_div {
 757                                                 compatible = "rockchip,rk3188-div-con";
 758                                                 rockchip,bits = <0 8>;
 759                                                 clocks = <&clk_sdio>;
 760                                                 clock-output-names = "clk_sdio";
 761                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 762                                                 #clock-cells = <0>;
 763                                                 rockchip,clkops-idx =
 764                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 765                                         };
 766
 767                                         clk_emmc_div: clk_emmc_div {
 768                                                 compatible = "rockchip,rk3188-div-con";
 769                                                 rockchip,bits = <8 8>;
 770                                                 clocks = <&clk_emmc>;
 771                                                 clock-output-names = "clk_emmc";
 772                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 773                                                 #clock-cells = <0>;
 774                                                 rockchip,clkops-idx =
 775                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 776                                         };
 777
 778                                 };
 779
 780                                 clk_sel_con13: sel-con@0078 {
 781                                         compatible = "rockchip,rk3188-selcon";
 782                                         reg = <0x0078 0x4>;
 783                                         #address-cells = <1>;
 784                                         #size-cells = <1>;
 785
 786                                         clk_uart0_pll_div: clk_uart0_pll_div {
 787                                                 compatible = "rockchip,rk3188-div-con";
 788                                                 rockchip,bits = <0 7>;
 789                                                 clocks = <&clk_uart0_pll>;
 790                                                 clock-output-names = "clk_uart0_pll";
 791                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 792                                                 #clock-cells = <0>;
 793                                         };
 794
 795                                         /* 7 reserved */
 796
 797                                         clk_uart0: clk_uart0_mux {
 798                                                 compatible = "rockchip,rk3188-mux-con";
 799                                                 rockchip,bits = <8 2>;
 800                                                 clocks = <&clk_uart0_pll_div>, <&uart0_frac>, <&xin24m>;
 801                                                 clock-output-names = "clk_uart0";
 802                                                 #clock-cells = <0>;
 803                                                 rockchip,clkops-idx =
 804                                                         <CLKOPS_RATE_RK3288_I2S>;
 805                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 806                                         };
 807
 808                                         /* 11:10 reserved */
 809
 810                                         clk_uart0_pll: clk_uart0_pll_mux {
 811                                                 compatible = "rockchip,rk3188-mux-con";
 812                                                 rockchip,bits = <12 2>;
 813                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>;
 814                                                 clock-output-names = "clk_uart0_pll";
 815                                                 #clock-cells = <0>;
 816                                                 #clock-init-cells = <1>;
 817                                         };
 818
 819                                         /* 15:14 reserved */
 820
 821                                 };
 822
 823                                 clk_sel_con14: sel-con@007c {
 824                                         compatible = "rockchip,rk3188-selcon";
 825                                         reg = <0x007c 0x4>;
 826                                         #address-cells = <1>;
 827                                         #size-cells = <1>;
 828
 829                                         clk_uart1_pll_div: clk_uart1_pll_div {
 830                                                 compatible = "rockchip,rk3188-div-con";
 831                                                 rockchip,bits = <0 7>;
 832                                                 clocks = <&clk_uart1_pll>;
 833                                                 clock-output-names = "clk_uart1_pll";
 834                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 835                                                 #clock-cells = <0>;
 836                                         };
 837
 838                                         /* 7 reserved */
 839
 840                                         clk_uart1: clk_uart1_mux {
 841                                                 compatible = "rockchip,rk3188-mux-con";
 842                                                 rockchip,bits = <8 2>;
 843                                                 clocks = <&clk_uart1_pll_div>, <&uart1_frac>, <&xin24m>;
 844                                                 clock-output-names = "clk_uart1";
 845                                                 #clock-cells = <0>;
 846                                                 rockchip,clkops-idx =
 847                                                         <CLKOPS_RATE_RK3288_I2S>;
 848                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 849                                         };
 850
 851                                         /* 11:10 reserved */
 852
 853                                         clk_uart1_pll: clk_uart1_pll_mux {
 854                                                 compatible = "rockchip,rk3188-mux-con";
 855                                                 rockchip,bits = <12 2>;
 856                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>;
 857                                                 clock-output-names = "clk_uart1_pll";
 858                                                 #clock-cells = <0>;
 859                                                 #clock-init-cells = <1>;
 860                                         };
 861
 862                                         /* 15:14 reserved */
 863                                 };
 864
 865                                 clk_sel_con15: sel-con@0080 {
 866                                         compatible = "rockchip,rk3188-selcon";
 867                                         reg = <0x0080 0x4>;
 868                                         #address-cells = <1>;
 869                                         #size-cells = <1>;
 870
 871                                         clk_uart2_pll_div: clk_uart2_pll_div {
 872                                                 compatible = "rockchip,rk3188-div-con";
 873                                                 rockchip,bits = <0 7>;
 874                                                 clocks = <&clk_uart2_pll>;
 875                                                 clock-output-names = "clk_uart2_pll";
 876                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 877                                                 #clock-cells = <0>;
 878                                         };
 879
 880                                         /* 7 reserved */
 881
 882                                         clk_uart2: clk_uart2_mux {
 883                                                 compatible = "rockchip,rk3188-mux-con";
 884                                                 rockchip,bits = <8 2>;
 885                                                 clocks = <&clk_uart2_pll>, <&uart2_frac>, <&xin24m>;
 886                                                 clock-output-names = "clk_uart2";
 887                                                 #clock-cells = <0>;
 888                                                 rockchip,clkops-idx =
 889                                                         <CLKOPS_RATE_RK3288_I2S>;
 890                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 891                                         };
 892
 893                                         /* 11:10 reserved */
 894
 895                                         clk_uart2_pll: clk_uart2_pll_mux {
 896                                                 compatible = "rockchip,rk3188-mux-con";
 897                                                 rockchip,bits = <12 2>;
 898                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>;
 899                                                 clock-output-names = "clk_uart2_pll";
 900                                                 #clock-cells = <0>;
 901                                                 #clock-init-cells = <1>;
 902                                         };
 903
 904                                         /* 15:14 reserved */
 905
 906                                 };
 907
 908                                 clk_sel_con16: sel-con@0084 {
 909                                         compatible = "rockchip,rk3188-selcon";
 910                                         reg = <0x0084 0x4>;
 911                                         #address-cells = <1>;
 912                                         #size-cells = <1>;
 913
 914                                         i2s2_pll_div: i2s2_pll_div {
 915                                                 compatible = "rockchip,rk3188-div-con";
 916                                                 rockchip,bits = <0 7>;
 917                                                 clocks = <&clk_i2s2_pll>;
 918                                                 clock-output-names = "clk_i2s2_pll";
 919                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 920                                                 #clock-cells = <0>;
 921                                                 rockchip,clkops-idx =
 922                                                         <CLKOPS_RATE_MUX_DIV>;
 923                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 924                                         };
 925
 926                                         /* 7: reserved */
 927
 928                                         clk_i2s2: clk_i2s2_mux {
 929                                                 compatible = "rockchip,rk3188-mux-con";
 930                                                 rockchip,bits = <8 2>;
 931                                                 clocks = <&i2s2_pll_div>, <&i2s2_frac>, <&i2s_clkin>, <&xin12m>;
 932                                                 clock-output-names = "clk_i2s2";
 933                                                 #clock-cells = <0>;
 934                                                 rockchip,clkops-idx =
 935                                                         <CLKOPS_RATE_RK3288_I2S>;
 936                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 937                                         };
 938
 939                                         /* 14:10: reserved */
 940
 941                                         clk_i2s2_pll: i2s2_pll_mux {
 942                                                 compatible = "rockchip,rk3188-mux-con";
 943                                                 rockchip,bits = <15 1>;
 944                                                 clocks = <&clk_cpll>,<&clk_gpll>;
 945                                                 clock-output-names = "clk_i2s2_pll";
 946                                                 #clock-cells = <0>;
 947                                                 #clock-init-cells = <1>;
 948                                         };
 949
 950                                 };
 951
 952                                 clk_sel_con17: sel-con@0088 {
 953                                         compatible = "rockchip,rk3188-selcon";
 954                                         reg = <0x0088 0x4>;
 955                                         #address-cells = <1>;
 956                                         #size-cells = <1>;
 957
 958                                         uart0_frac: uart0_frac {
 959                                                 compatible = "rockchip,rk3188-frac-con";
 960                                                 clocks = <&clk_uart0_pll_div>;
 961                                                 clock-output-names = "uart0_frac";
 962                                                 /* numerator    denominator */
 963                                                 rockchip,bits = <0 32>;
 964                                                 rockchip,clkops-idx =
 965                                                         <CLKOPS_RATE_FRAC>;
 966                                                 #clock-cells = <0>;
 967                                         };
 968
 969                                 };
 970
 971                                 clk_sel_con18: sel-con@008c {
 972                                         compatible = "rockchip,rk3188-selcon";
 973                                         reg = <0x008c 0x4>;
 974                                         #address-cells = <1>;
 975                                         #size-cells = <1>;
 976
 977                                         uart1_frac: uart1_frac {
 978                                                 compatible = "rockchip,rk3188-frac-con";
 979                                                 clocks = <&clk_uart1_pll_div>;
 980                                                 clock-output-names = "uart1_frac";
 981                                                 /* numerator    denominator */
 982                                                 rockchip,bits = <0 32>;
 983                                                 rockchip,clkops-idx =
 984                                                         <CLKOPS_RATE_FRAC>;
 985                                                 #clock-cells = <0>;
 986                                         };
 987
 988                                 };
 989
 990                                 clk_sel_con19: sel-con@0090 {
 991                                         compatible = "rockchip,rk3188-selcon";
 992                                         reg = <0x0090 0x4>;
 993                                         #address-cells = <1>;
 994                                         #size-cells = <1>;
 995
 996                                         uart2_frac: uart2_frac {
 997                                                 compatible = "rockchip,rk3188-frac-con";
 998                                                 clocks = <&clk_uart2_pll_div>;
 999                                                 clock-output-names = "uart2_frac";
1000                                                 /* numerator    denominator */
1001                                                 rockchip,bits = <0 32>;
1002                                                 rockchip,clkops-idx =
1003                                                         <CLKOPS_RATE_FRAC>;
1004                                                 #clock-cells = <0>;
1005                                         };
1006
1007                                 };
1008
1009                                 clk_sel_con20: sel-con@0094 {
1010                                         compatible = "rockchip,rk3188-selcon";
1011                                         reg = <0x0094 0x4>;
1012                                         #address-cells = <1>;
1013                                         #size-cells = <1>;
1014
1015                                         spdif_frac: spdif_frac {
1016                                                 compatible = "rockchip,rk3188-frac-con";
1017                                                 clocks = <&spdif_div>;
1018                                                 clock-output-names = "spdif_frac";
1019                                                 /* numerator    denominator */
1020                                                 rockchip,bits = <0 32>;
1021                                                 rockchip,clkops-idx =
1022                                                         <CLKOPS_RATE_FRAC>;
1023                                                 #clock-cells = <0>;
1024                                         };
1025
1026                                 };
1027
1028                                 clk_sel_con21: sel-con@0098 {
1029                                         compatible = "rockchip,rk3188-selcon";
1030                                         reg = <0x0098 0x4>;
1031                                         #address-cells = <1>;
1032                                         #size-cells = <1>;
1033
1034                                         clk_hdmi_cec: clk_hdmi_cec_div {
1035                                                 compatible = "rockchip,rk3188-div-con";
1036                                                 rockchip,bits = <0 14>;
1037                                                 clocks = <&xin24m>;
1038                                                 clock-output-names = "clk_hdmi_cec";
1039                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1040                                                 #clock-cells = <0>;
1041                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1042                                         };
1043                                         /*
1044                                         clk_hdmi_cec_div: clk_hdmi_cec_div {
1045                                                 compatible = "rockchip,rk3188-div-con";
1046                                                 rockchip,bits = <0 14>;
1047                                                 clocks = <&clk_hdmi_cec>;
1048                                                 clock-output-names = "clk_hdmi_cec";
1049                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1050                                                 #clock-cells = <0>;
1051                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1052                                         };
1053
1054                                         clk_hdmi_cec: clk_hdmi_cec_mux {
1055                                                 compatible = "rockchip,rk3188-mux-con";
1056                                                 rockchip,bits = <14 2>;
1057                                                 clocks = <&dummy>, <&dummy>, <&xin24m>;
1058                                                 clock-output-names = "clk_hdmi_cec";
1059                                                 #clock-cells = <0>;
1060                                         };
1061                                         */
1062                                 };
1063
1064                                 clk_sel_con22: sel-con@009c {
1065                                         compatible = "rockchip,rk3188-selcon";
1066                                         reg = <0x009c 0x4>;
1067                                         #address-cells = <1>;
1068                                         #size-cells = <1>;
1069
1070                                         clk_rga: clk_rga_div {
1071                                                 compatible = "rockchip,rk3188-div-con";
1072                                                 rockchip,bits = <0 5>;
1073                                                 clocks = <&aclk_rga>;
1074                                                 clock-output-names = "clk_rga";
1075                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1076                                                 #clock-cells = <0>;
1077                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1078                                         };
1079
1080                                         /* 7:0 reserved */
1081
1082                                         clk_tsp_div: clk_tsp_div {
1083                                                 compatible = "rockchip,rk3188-div-con";
1084                                                 rockchip,bits = <8 5>;
1085                                                 clocks = <&clk_tsp>;
1086                                                 clock-output-names = "clk_tsp";
1087                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1088                                                 #clock-cells = <0>;
1089                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1090                                         };
1091
1092                                         /* 14:13 reserved */
1093
1094                                         clk_tsp: clk_tsp_mux {
1095                                                 compatible = "rockchip,rk3188-mux-con";
1096                                                 rockchip,bits = <15 1>;
1097                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1098                                                 clock-output-names = "clk_tsp";
1099                                                 #clock-cells = <0>;
1100                                         };
1101
1102                                 };
1103
1104                                 clk_sel_con23: sel-con@00a0 {
1105                                         compatible = "rockchip,rk3188-selcon";
1106                                         reg = <0x00a0 0x4>;
1107                                         #address-cells = <1>;
1108                                         #size-cells = <1>;
1109
1110                                         clk_wifi_div: clk_wifi_div {
1111                                                 compatible = "rockchip,rk3188-div-con";
1112                                                 rockchip,bits = <0 5>;
1113                                                 clocks = <&clk_wifi>;
1114                                                 clock-output-names = "clk_wifi";
1115                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1116                                                 #clock-cells = <0>;
1117                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1118                                         };
1119
1120                                         clk_wifi: clk_wifi_mux {
1121                                                 compatible = "rockchip,rk3188-mux-con";
1122                                                 rockchip,bits = <5 2>;
1123                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>;
1124                                                 clock-output-names = "clk_wifi";
1125                                                 #clock-cells = <0>;
1126                                         };
1127
1128                                         /* 7 reserved */
1129
1130                                         clk_hdcp_div: clk_hdcp_div {
1131                                                 compatible = "rockchip,rk3188-div-con";
1132                                                 rockchip,bits = <8 6>;
1133                                                 clocks = <&clk_hdcp>;
1134                                                 clock-output-names = "clk_hdcp";
1135                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1136                                                 #clock-cells = <0>;
1137                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1138                                         };
1139
1140                                         clk_hdcp: clk_hdcp_mux {
1141                                                 compatible = "rockchip,rk3188-mux-con";
1142                                                 rockchip,bits = <14 2>;
1143                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>;
1144                                                 clock-output-names = "clk_hdcp";
1145                                                 #clock-cells = <0>;
1146                                         };
1147
1148                                 };
1149
1150                                 clk_sel_con24: sel-con@00a4 {
1151                                         compatible = "rockchip,rk3188-selcon";
1152                                         reg = <0x00a4 0x4>;
1153                                         #address-cells = <1>;
1154                                         #size-cells = <1>;
1155
1156                                         clk_crypto_div: clk_crypto_div {
1157                                                 compatible = "rockchip,rk3188-div-con";
1158                                                 rockchip,bits = <0 5>;
1159                                                 clocks = <&clk_crypto>;
1160                                                 clock-output-names = "clk_crypto";
1161                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1162                                                 #clock-cells = <0>;
1163                                                 #clock-init-cells = <1>;
1164                                         };
1165
1166                                         clk_crypto: clk_crypto_mux {
1167                                                 compatible = "rockchip,rk3188-mux-con";
1168                                                 rockchip,bits = <5 1>;
1169                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1170                                                 clock-output-names = "clk_crypto";
1171                                                 #clock-cells = <0>;
1172                                         };
1173
1174                                         clk_tsadc: clk_tsadc_div {
1175                                                 compatible = "rockchip,rk3188-div-con";
1176                                                 rockchip,bits = <6 10>;
1177                                                 clocks = <&xin24m>;
1178                                                 clock-output-names = "clk_tsadc";
1179                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1180                                                 #clock-cells = <0>;
1181                                                 #clock-init-cells = <1>;
1182                                         };
1183
1184                                 };
1185
1186                                 clk_sel_con25: sel-con@00a8 {
1187                                         compatible = "rockchip,rk3188-selcon";
1188                                         reg = <0x00a8 0x4>;
1189                                         #address-cells = <1>;
1190                                         #size-cells = <1>;
1191
1192                                         clk_spi0_div: clk_spi0_div {
1193                                                 compatible = "rockchip,rk3188-div-con";
1194                                                 rockchip,bits = <0 7>;
1195                                                 clocks = <&clk_spi0>;
1196                                                 clock-output-names = "clk_spi0";
1197                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1198                                                 #clock-cells = <0>;
1199                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1200                                         };
1201
1202                                         /* 7 reserved */
1203
1204                                         clk_spi0: clk_spi0_mux {
1205                                                 compatible = "rockchip,rk3188-mux-con";
1206                                                 rockchip,bits = <8 1>;
1207                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1208                                                 clock-output-names = "clk_spi0";
1209                                                 #clock-cells = <0>;
1210                                         };
1211
1212                                         /* 15:9 reserved */
1213
1214                                 };
1215
1216                                 clk_sel_con26: sel-con@00ac {
1217                                         compatible = "rockchip,rk3188-selcon";
1218                                         reg = <0x00ac 0x4>;
1219                                         #address-cells = <1>;
1220                                         #size-cells = <1>;
1221
1222                                         clk_ddr_div: clk_ddr_div {
1223                                                 compatible = "rockchip,rk3188-div-con";
1224                                                 rockchip,bits = <0 2>;
1225                                                 clocks = <&clk_ddr>;
1226                                                 clock-output-names = "clk_ddr";
1227                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1228                                                 rockchip,div-relations =
1229                                                                 <0x0 1
1230                                                                  0x1 2
1231                                                                  0x3 4>;
1232                                                 #clock-cells = <0>;
1233                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1234                                                                         CLK_SET_RATE_NO_REPARENT)>;
1235                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR_DIV2>;
1236                                         };
1237
1238                                         /* 7:2 reserved */
1239
1240                                         clk_ddr: clk_ddr_pll_mux {
1241                                                 compatible = "rockchip,rk3188-mux-con";
1242                                                 rockchip,bits = <8 2>;
1243                                                 clocks = <&clk_dpll>, <&clk_gpll>, <&clk_apll>;
1244                                                 clock-output-names = "clk_ddr";
1245                                                 #clock-cells = <0>;
1246                                         };
1247
1248                                         /* 15:10 reserved */
1249
1250                                 };
1251
1252                                 clk_sel_con27: sel-con@00b0 {
1253                                         compatible = "rockchip,rk3188-selcon";
1254                                         reg = <0x00b0 0x4>;
1255                                         #address-cells = <1>;
1256                                         #size-cells = <1>;
1257
1258                                         dclk_vop0_pll: dclk_vop0_pll_mux {
1259                                                 compatible = "rockchip,rk3188-mux-con";
1260                                                 rockchip,bits = <0 1>;
1261                                                 clocks = <&clk_gpll>, <&clk_cpll>;
1262                                                 clock-output-names = "dclk_vop0_pll";
1263                                                 #clock-cells = <0>;
1264                                                 #clock-init-cells = <1>;
1265                                         };
1266
1267                                         dclk_vop0: dclk_vop0_mux {
1268                                                 compatible = "rockchip,rk3188-mux-con";
1269                                                 rockchip,bits = <1 1>;
1270                                                 clocks = <&hdmi_phy_clk>, <&dummy>;/*dclk_vop0_div*/
1271                                                 clock-output-names = "dclk_vop0";
1272                                                 #clock-cells = <0>;
1273                                                 #clock-init-cells = <1>;
1274                                         };
1275
1276                                         /* 7:2 reserved */
1277
1278                                         dclk_vop0_div: dclk_vop0_div {
1279                                                 compatible = "rockchip,rk3188-div-con";
1280                                                 rockchip,bits = <8 8>;
1281                                                 clocks = <&dclk_vop0_pll>;
1282                                                 clock-output-names = "dclk_vop0";
1283                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1284                                                 #clock-cells = <0>;
1285                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1286                                         };
1287
1288                                 };
1289
1290                                 clk_sel_con28: sel-con@00b4 {
1291                                         compatible = "rockchip,rk3188-selcon";
1292                                         reg = <0x00b4 0x4>;
1293                                         #address-cells = <1>;
1294                                         #size-cells = <1>;
1295
1296                                         aclk_rkvdec_div: aclk_rkvdec_div {
1297                                                 compatible = "rockchip,rk3188-div-con";
1298                                                 rockchip,bits = <0 5>;
1299                                                 clocks = <&aclk_rkvdec>;
1300                                                 clock-output-names = "aclk_rkvdec";
1301                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1302                                                 #clock-cells = <0>;
1303                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1304                                         };
1305
1306                                         /* 5 reserved */
1307
1308                                         aclk_rkvdec: aclk_rkvdec_mux {
1309                                                 compatible = "rockchip,rk3188-mux-con";
1310                                                 rockchip,bits = <6 2>;
1311                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1312                                                 clock-output-names = "aclk_rkvdec";
1313                                                 #clock-cells = <0>;
1314                                                 #clock-init-cells = <1>;
1315                                         };
1316
1317                                         clk_vdec_cabac_div: clk_vdec_cabac_div {
1318                                                 compatible = "rockchip,rk3188-div-con";
1319                                                 rockchip,bits = <8 5>;
1320                                                 clocks = <&clk_vdec_cabac>;
1321                                                 clock-output-names = "clk_vdec_cabac";
1322                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1323                                                 #clock-cells = <0>;
1324                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1325                                         };
1326
1327                                         /* 13 reserved */
1328
1329                                         clk_vdec_cabac: clk_vdec_cabac_mux {
1330                                                 compatible = "rockchip,rk3188-mux-con";
1331                                                 rockchip,bits = <14 2>;
1332                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1333                                                 clock-output-names = "clk_vdec_cabac";
1334                                                 #clock-cells = <0>;
1335                                                 #clock-init-cells = <1>;
1336                                         };
1337                                 };
1338
1339                                 clk_sel_con29: sel-con@00b8 {
1340                                         compatible = "rockchip,rk3188-selcon";
1341                                         reg = <0x00b8 0x4>;
1342                                         #address-cells = <1>;
1343                                         #size-cells = <1>;
1344
1345                                         dclk_hdmiphy_div: dclk_hdmiphy_div {
1346                                                 compatible = "rockchip,rk3188-div-con";
1347                                                 rockchip,bits = <0 3>;
1348                                                 clocks = <&dclk_vop0_pll>;
1349                                                 clock-output-names = "dclk_hdmiphy";
1350                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1351                                                 #clock-cells = <0>;
1352                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1353                                         };
1354
1355                                         /* 7:3 reserved */
1356
1357                                         clk_macphy_div: clk_macphy_div {
1358                                                 compatible = "rockchip,rk3188-div-con";
1359                                                 rockchip,bits = <8 3>;
1360                                                 clocks = <&clk_macphy>;
1361                                                 clock-output-names = "clk_macphy";
1362                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1363                                                 #clock-cells = <0>;
1364                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1365                                         };
1366
1367                                         rmii_clkin: rmii_clkin {
1368                                                 compatible = "rockchip,rk3188-mux-con";
1369                                                 rockchip,bits = <10 1>;
1370                                                 clocks = <&gmac_clkin>, <&phy_50m_out>;
1371                                                 clock-output-names = "rmii_clkin";
1372                                                 #clock-cells = <0>;
1373                                                 #clock-init-cells = <1>;
1374                                         };
1375                                         /*
1376                                         clk_mac_tx: clk_mac_tx {
1377                                                 compatible = "rockchip,rk3188-mux-con";
1378                                                 rockchip,bits = <11 1>;
1379                                                 clocks = <&clk_gates5 6>, <&phy_tx_out>;
1380                                                 clock-output-names = "clk_mac_tx";
1381                                                 #clock-cells = <0>;
1382                                                 #clock-init-cells = <1>;
1383                                         };
1384                                         */
1385                                         clk_macphy: clk_macphy_mux {
1386                                                 compatible = "rockchip,rk3188-mux-con";
1387                                                 rockchip,bits = <12 1>;
1388                                                 clocks = <&clk_mac_pll_div>, <&gmac_clkin>;
1389                                                 clock-output-names = "clk_macphy";
1390                                                 #clock-cells = <0>;
1391                                                 #clock-init-cells = <1>;
1392                                         };
1393
1394                                         /* 15:13 reserved */
1395
1396                                 };
1397
1398                                 clk_sel_con30: sel-con@00bc {
1399                                         compatible = "rockchip,rk3188-selcon";
1400                                         reg = <0x00bc 0x4>;
1401                                         #address-cells = <1>;
1402                                         #size-cells = <1>;
1403
1404                                         i2s2_frac: i2s2_frac {
1405                                                 compatible = "rockchip,rk3188-frac-con";
1406                                                 clocks = <&i2s2_pll_div>;
1407                                                 clock-output-names = "i2s2_frac";
1408                                                 /* numerator    denominator */
1409                                                 rockchip,bits = <0 32>;
1410                                                 rockchip,clkops-idx =
1411                                                         <CLKOPS_RATE_FRAC>;
1412                                                 #clock-cells = <0>;
1413                                         };
1414                                 };
1415
1416                                 clk_sel_con31: sel-con@00c0 {
1417                                         compatible = "rockchip,rk3188-selcon";
1418                                         reg = <0x00c0 0x4>;
1419                                         #address-cells = <1>;
1420                                         #size-cells = <1>;
1421
1422                                         aclk_iep_div: aclk_iep_div {
1423                                                 compatible = "rockchip,rk3188-div-con";
1424                                                 rockchip,bits = <0 5>;
1425                                                 clocks = <&aclk_iep>;
1426                                                 clock-output-names = "aclk_iep";
1427                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1428                                                 #clock-cells = <0>;
1429                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1430                                         };
1431
1432                                         aclk_iep: aclk_iep_mux {
1433                                                 compatible = "rockchip,rk3188-mux-con";
1434                                                 rockchip,bits = <5 2>;
1435                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1436                                                 clock-output-names = "aclk_iep";
1437                                                 #clock-cells = <0>;
1438                                                 #clock-init-cells = <1>;
1439                                         };
1440
1441                                         /* 7: reserved */
1442
1443                                         aclk_hdcp_div: aclk_hdcp_div {
1444                                                 compatible = "rockchip,rk3188-div-con";
1445                                                 rockchip,bits = <8 5>;
1446                                                 clocks = <&aclk_hdcp>;
1447                                                 clock-output-names = "aclk_hdcp";
1448                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1449                                                 #clock-cells = <0>;
1450                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1451                                         };
1452
1453                                         aclk_hdcp: aclk_hdcp_mux {
1454                                             compatible = "rockchip,rk3188-mux-con";
1455                                             rockchip,bits = <13 2>;
1456                                             clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1457                                             clock-output-names = "aclk_hdcp";
1458                                             #clock-cells = <0>;
1459                                         };
1460
1461                                         /* 15: reserved */
1462                                 };
1463
1464                                 clk_sel_con32: sel-con@00c4 {
1465                                         compatible = "rockchip,rk3188-selcon";
1466                                         reg = <0x00c4 0x4>;
1467                                         #address-cells = <1>;
1468                                         #size-cells = <1>;
1469
1470                                         aclk_vpu_div: aclk_vpu_div {
1471                                                 compatible = "rockchip,rk3188-div-con";
1472                                                 rockchip,bits = <0 5>;
1473                                                 clocks = <&aclk_vpu>;
1474                                                 clock-output-names = "aclk_vpu";
1475                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1476                                                 #clock-cells = <0>;
1477                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1478                                         };
1479
1480                                         aclk_vpu: aclk_vpu_mux {
1481                                                 compatible = "rockchip,rk3188-mux-con";
1482                                                 rockchip,bits = <5 2>;
1483                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1484                                                 clock-output-names = "aclk_vpu";
1485                                                 #clock-cells = <0>;
1486                                                 #clock-init-cells = <1>;
1487                                         };
1488
1489                                         /* 15:7 reserved */
1490
1491                                 };
1492
1493                                 clk_sel_con33: sel-con@00c8 {
1494                                         compatible = "rockchip,rk3188-selcon";
1495                                         reg = <0x00c8 0x4>;
1496                                         #address-cells = <1>;
1497                                         #size-cells = <1>;
1498
1499                                         aclk_vop_div: aclk_vop_div {
1500                                                 compatible = "rockchip,rk3188-div-con";
1501                                                 rockchip,bits = <0 5>;
1502                                                 clocks = <&aclk_vop>;
1503                                                 clock-output-names = "aclk_vop";
1504                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1505                                                 #clock-cells = <0>;
1506                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1507                                         };
1508
1509                                         aclk_vop: aclk_vop_mux {
1510                                                 compatible = "rockchip,rk3188-mux-con";
1511                                                 rockchip,bits = <5 2>;
1512                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1513                                                 clock-output-names = "aclk_vop";
1514                                                 #clock-cells = <0>;
1515                                                 #clock-init-cells = <1>;
1516                                         };
1517
1518                                         /* 7 reserved */
1519
1520                                          aclk_rga_div: aclk_rga_div {
1521                                                 compatible = "rockchip,rk3188-div-con";
1522                                                 rockchip,bits = <8 5>;
1523                                                 clocks = <&aclk_rga>;
1524                                                 clock-output-names = "aclk_rga";
1525                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1526                                                 #clock-cells = <0>;
1527                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1528                                         };
1529
1530                                         aclk_rga: aclk_rga_mux {
1531                                                 compatible = "rockchip,rk3188-mux-con";
1532                                                 rockchip,bits = <13 2>;
1533                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1534                                                 clock-output-names = "aclk_rga";
1535                                                 #clock-cells = <0>;
1536                                                 #clock-init-cells = <1>;
1537                                         };
1538
1539                                         /* 15 reserved */
1540
1541                                 };
1542
1543                         clk_sel_con34: sel-con@00cc {
1544                                         compatible = "rockchip,rk3188-selcon";
1545                                         reg = <0x00cc 0x4>;
1546                                         #address-cells = <1>;
1547                                         #size-cells = <1>;
1548
1549                                         aclk_gpu_div: aclk_gpu_div {
1550                                                 compatible = "rockchip,rk3188-div-con";
1551                                                 rockchip,bits = <0 5>;
1552                                                 clocks = <&aclk_gpu>;
1553                                                 clock-output-names = "aclk_gpu";
1554                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1555                                                 #clock-cells = <0>;
1556                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1557                                         };
1558
1559                                         aclk_gpu: aclk_gpu_mux {
1560                                                 compatible = "rockchip,rk3188-mux-con";
1561                                                 rockchip,bits = <5 2>;
1562                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1563                                                 clock-output-names = "aclk_gpu";
1564                                                 #clock-cells = <0>;
1565                                                 #clock-init-cells = <1>;
1566                                         };
1567
1568                                         /* 7 reserved */
1569
1570                                          clk_vdec_core_div: clk_vdec_core_div {
1571                                                 compatible = "rockchip,rk3188-div-con";
1572                                                 rockchip,bits = <8 5>;
1573                                                 clocks = <&clk_vdec_core>;
1574                                                 clock-output-names = "clk_vdec_core";
1575                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1576                                                 #clock-cells = <0>;
1577                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1578                                         };
1579
1580                                         clk_vdec_core: clk_vdec_core_mux {
1581                                                 compatible = "rockchip,rk3188-mux-con";
1582                                                 rockchip,bits = <13 2>;
1583                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1584                                                 clock-output-names = "clk_vdec_core";
1585                                                 #clock-cells = <0>;
1586                                                 #clock-init-cells = <1>;
1587
1588                                         };
1589
1590                                         /* 15 reserved */
1591                                 };
1592
1593                         clk_sel_con35: sel-con@0134 {
1594                                         compatible = "rockchip,rk3188-selcon";
1595                                         reg = <0x0134 0x4>;
1596                                         #address-cells = <1>;
1597                                         #size-cells = <1>;
1598
1599                                         /* 7:0 reserved */
1600
1601                                          testclk: testclk_mux {
1602                                                 compatible = "rockchip,rk3188-mux-con";
1603                                                 rockchip,bits = <8 4>;
1604                                                 clocks = <&clk_wifi>, <&dummy>, <&clk_core>, <&clk_gates7 0>, <&aclk_iep>, <&aclk_gpu>, <&aclk_peri>, <&aclk_core>;
1605                                                 clock-output-names = "testclk";
1606                                                 #clock-cells = <0>;
1607                                                 #clock-init-cells = <1>;
1608                                         };
1609
1610                                         /* 12 reserved */
1611
1612                                          hdmi_phy_clk: hdmi_phy_clk_mux {
1613                                                 compatible = "rockchip,rk3188-mux-con";
1614                                                 rockchip,bits = <13 1>;
1615                                                 clocks = <&hdmiphy_out>, <&xin24m>;
1616                                                 clock-output-names = "hdmi_phy_clk";
1617                                                 #clock-cells = <0>;
1618                                                 #clock-init-cells = <1>;
1619                                         };
1620
1621                                         usb480m_phy: usb480m_phy_mux {
1622                                                 compatible = "rockchip,rk3188-mux-con";
1623                                                 rockchip,bits = <14 1>;
1624                                                 clocks = <&usbphy0_480m>, <&usbphy1_480m>;
1625                                                 clock-output-names = "usb480m_phy";
1626                                                 #clock-cells = <0>;
1627                                                 #clock-init-cells = <1>;
1628                                         };
1629
1630                                         usb480m: usb480m_mux {
1631                                                 compatible = "rockchip,rk3188-mux-con";
1632                                                 rockchip,bits = <15 1>;
1633                                                 clocks = <&usb480m_phy>, <&xin24m>;
1634                                                 clock-output-names = "usb480m";
1635                                                 #clock-cells = <0>;
1636                                                 rockchip,clkops-idx =
1637                                                         <CLKOPS_RATE_RK3288_USB480M>;
1638                                                 #clock-init-cells = <1>;
1639                                                 };
1640                                         };
1641                                 };
1642                         /* Gate control regs */
1643                         clk_gate_cons {
1644                                 compatible = "rockchip,rk-gate-cons";
1645                                 #address-cells = <1>;
1646                                 #size-cells = <1>;
1647                                 ranges;
1648                                 clk_gates0: gate-clk@00d0 {
1649                                         compatible = "rockchip,rk3188-gate-clk";
1650                                         reg = <0x00d0 0x4>;
1651                                         clocks =
1652                                         <&dummy>,       <&dummy>,
1653                                         <&dummy>,       <&clk_i2s0_pll>,
1654
1655                                         <&i2s0_frac>,   <&clk_i2s0>,
1656                                         <&dummy>,       <&clk_i2s2_pll>,
1657
1658                                         <&i2s2_frac>,   <&clk_i2s2>,
1659                                         <&clk_i2s1_pll>,        <&i2s1_frac>,
1660
1661                                         <&dummy>,       <&clk_i2s1_out>,
1662                                         <&clk_i2s1>,    <&testclk>;
1663
1664                                         clock-output-names =
1665                                         "reserved",     "reserved",
1666                                         "reserved",     "clk_i2s0_pll",
1667
1668                                         "i2s0_frac",    "i2s0_8ch",
1669                                         "reserved",     "clk_i2s2_pll",
1670
1671                                         "i2s2_frac",    "i2s2_2ch",
1672                                         "clk_i2s1_pll", "i2s1_frac",
1673
1674                                         "reserved",     "i2s_clkout",
1675                                         "i2s1_8ch",     "testclk";
1676
1677                                         #clock-cells = <1>;
1678                                 };
1679
1680                                 clk_gates1: gate-clk@00d4 {
1681                                         compatible = "rockchip,rk3188-gate-clk";
1682                                         reg = <0x00d4 0x4>;
1683                                         clocks =
1684                                         <&clk_nandc>,   <&aclk_vop>,
1685                                         <&aclk_rga>,    <&jtag_clkin>,
1686
1687                                         <&aclk_hdcp>,   <&xin24m>,
1688                                         <&xin24m>,      <&clk_mac_pll>,
1689
1690                                         <&clk_uart0_pll>,       <&uart0_frac>,
1691                                         <&clk_uart1_pll>,       <&uart1_frac>,
1692
1693                                         <&clk_uart2_pll>,       <&uart2_frac>,
1694                                         <&dummy>,       <&dummy>;
1695
1696                                         clock-output-names =
1697                                         "clk_nandc",    "aclk_vop",
1698                                         "aclk_rga",     "clk_jtag",
1699
1700                                         "aclk_hdcp",    "clk_otgphy0",
1701                                         "clk_otgphy1",  "clk_mac_pll",
1702
1703                                         "clk_uart0_pll",        "uart0_frac",
1704                                         "clk_uart1_pll",        "uart1_frac",
1705
1706                                         "clk_uart2_pll",        "uart2_frac",
1707                                         "reserved",     "reserved";
1708
1709                                         #clock-cells = <1>;
1710                                 };
1711
1712                                 clk_gates2: gate-clk@00d8 {
1713                                         compatible = "rockchip,rk3188-gate-clk";
1714                                         reg = <0x00d8 0x4>;
1715                                         clocks =
1716                                         <&dummy>,       <&dummy>,
1717                                         <&clk_gmac>,    <&dummy>,
1718
1719                                         <&dummy>,       <&dummy>,
1720                                         <&clk_tsp>,     <&clk_crypto>,
1721
1722                                         <&clk_tsadc>,   <&clk_spi0>,
1723                                         <&clk_spdif_pll>,       <&clk_sdmmc0>,
1724
1725                                         <&spdif_frac>,  <&clk_sdio>,
1726                                         <&clk_emmc>,    <&clk_wifi>;
1727
1728                                         clock-output-names =
1729                                         "reserved",     "clk_ddrmon",
1730                                         "clk_gmac",     "reserved",
1731
1732                                         "reserved",     "reserved",
1733                                         "clk_tsp",      "clk_crypto",
1734
1735                                         "clk_tsadc",    "clk_spi0",
1736                                         "clk_spdif_pll",        "clk_sdmmc0",
1737
1738                                         "spdif_frac",   "clk_sdio",
1739                                         "clk_emmc",     "clk_wifi";
1740
1741                                         #clock-cells = <1>;
1742                                 };
1743
1744                                 clk_gates3: gate-clk@00dc {
1745                                         compatible = "rockchip,rk3188-gate-clk";
1746                                         reg = <0x00dc 0x4>;
1747                                         clocks =
1748                                         <&aclk_iep>,    <&dummy>,
1749                                         <&aclk_rkvdec>, <&clk_vdec_cabac>,
1750
1751                                         <&clk_vdec_core>,       <&clk_hdcp>,
1752                                         <&aclk_rga>,    <&xin24m>,
1753
1754                                         <&clk_hdmi_cec>,        <&dummy>,
1755                                         <&dummy>,       <&aclk_vpu>,
1756
1757                                         <&dummy>,       <&dummy>,
1758                                         <&dummy>,       <&dummy>;
1759
1760                                         clock-output-names =
1761                                         "aclk_iep",     "dclk_vop0",
1762                                         "aclk_rkvdec",  "clk_vdec_cabac",
1763
1764                                         "clk_vdec_core",        "clk_hdcp",
1765                                         "clk_rga",      "clk_hdmi_hdcp",
1766
1767                                         "clk_hdmi_cec", "reserved",
1768                                         "reserved",     "aclk_vpu",
1769
1770                                         "reserved",     "reserved",
1771                                         "reserved",     "reserved";
1772
1773                                         #clock-cells = <1>;
1774                                 };
1775
1776                                 clk_gates4: gate-clk@00e0 {
1777                                         compatible = "rockchip,rk3188-gate-clk";
1778                                         reg = <0x00e0 0x4>;
1779                                         clocks =
1780                                         <&clk_core>,    <&clk_core>,
1781                                         <&aclk_core>,   <&dummy>,
1782
1783                                         <&aclk_vpu>,    <&aclk_rkvdec>,
1784                                         <&dummy>,       <&dummy>,
1785
1786                                         <&dummy>,       <&dummy>,
1787                                         <&dummy>,       <&dummy>,
1788
1789                                         <&dummy>,       <&dummy>,
1790                                         <&dummy>,       <&dummy>;
1791
1792                                         clock-output-names =
1793                                         "aclk_core",    "pclk_dbg",
1794                                         "aclk_gic400",  "reserved",
1795
1796                                         "hclk_vpu",     "hclk_rkvdec",
1797                                         "reserved",     "reserved",
1798
1799                                         "reserved",     "reserved",
1800                                         "reserved",     "reserved",
1801
1802                                         "reserved",     "reserved",
1803                                         "reserved",     "reserved";
1804
1805                                         #clock-cells = <1>;
1806                                 };
1807
1808                                 clk_gates5: gate-clk@00e4 {
1809                                         compatible = "rockchip,rk3188-gate-clk";
1810                                         reg = <0x00e4 0x4>;
1811                                         clocks =
1812                                         <&aclk_peri>,   <&aclk_peri>,
1813                                         <&aclk_peri>,   <&clk_mac>,
1814
1815                                         <&clk_mac>,     <&clk_mac>,
1816                                         <&clk_mac>,     <&clk_macphy>,
1817
1818                                         <&dummy>,       <&dummy>,
1819                                         <&dummy>,       <&dummy>,
1820
1821                                         <&dummy>,       <&dummy>,
1822                                         <&dummy>,       <&dummy>;
1823
1824                                         clock-output-names =
1825                                         "aclk_peri",    "hclk_peri",
1826                                         "pclk_peri",    "clk_mac_ref",
1827
1828                                         "clk_mac_refout",       "clk_mac_rx",
1829                                         "clk_mac_tx",   "clk_macphy",
1830
1831                                         "reserved",     "reserved",
1832                                         "reserved",     "reserved",
1833
1834                                         "reserved",     "reserved",
1835                                         "reserved",     "reserved";
1836
1837                                         #clock-cells = <1>;
1838                                 };
1839
1840                                 clk_gates6: gate-clk@00e8 {
1841                                         compatible = "rockchip,rk3188-gate-clk";
1842                                         reg = <0x00e8 0x4>;
1843                                         clocks =
1844                                         <&aclk_bus>,    <&aclk_bus>,
1845                                         <&aclk_bus>,    <&pclk_bus>,
1846
1847                                         <&pclk_bus>,    <&xin24m>,
1848                                         <&xin24m>,      <&xin24m>,
1849
1850                                         <&xin24m>,      <&xin24m>,
1851                                         <&xin24m>,      <&dummy>,
1852
1853                                         <&dummy>,       <&pclk_bus>,
1854                                         <&dummy>,       <&dummy>;
1855
1856                                         clock-output-names =
1857                                         "aclk_bus",     "hclk_bus",
1858                                         "pclk_bus",     "pclk_bus_pre",
1859
1860                                         "pclk_phy",     "clk_timer0",
1861                                         "clk_timer1",   "clk_timer2",
1862
1863                                         "clk_timer3",   "clk_timer4",
1864                                         "clk_timer5",   "reserved",
1865
1866                                         "reserved",     "pclk_ddr",
1867                                         "reserved",     "reserved";
1868
1869                                         #clock-cells = <1>;
1870                                 };
1871
1872                                 clk_gates7: gate-clk@00ec {
1873                                         compatible = "rockchip,rk3188-gate-clk";
1874                                         reg = <0x00ec 0x4>;
1875                                         clocks =
1876                                         <&clk_ddr_div>, <&clk_ddr_div>,
1877                                         <&dummy>,       <&dummy>,
1878
1879                                         <&dummy>,       <&dummy>,
1880                                         <&dummy>,       <&dummy>,
1881
1882                                         <&dummy>,       <&dummy>,
1883                                         <&dummy>,       <&dummy>,
1884
1885                                         <&dummy>,       <&dummy>,
1886                                         <&aclk_gpu>,    <&aclk_gpu>;
1887
1888                                         clock-output-names =
1889                                         "clk_ddrphy",   "clk4x_ddrphy",
1890                                         "reserved",     "reserved",
1891
1892                                         "reserved",     "reserved",
1893                                         "reserved",     "reserved",
1894
1895                                         "reserved",     "reserved",
1896                                         "reserved",     "reserved",
1897
1898                                         "reserved",     "reserved",
1899                                         "g_aclk_gpu",   "g_aclk_gpu_noc";
1900
1901                                         #clock-cells = <1>;
1902                                 };
1903
1904                                 clk_gates8: gate-clk@00f0 {
1905                                         compatible = "rockchip,rk3188-gate-clk";
1906                                         reg = <0x00f0 0x4>;
1907                                         clocks =
1908                                         <&aclk_bus>,    <&aclk_bus>,
1909                                         <&aclk_bus>,    <&hclk_bus>,
1910
1911                                         <&clk_gates6 13>,       <&clk_gates7 0>,
1912                                         <&clk_gates6 13>,       <&hclk_bus>,
1913
1914                                         <&hclk_bus>,    <&hclk_bus>,
1915                                         <&hclk_bus>,    <&hclk_bus>,
1916
1917                                         <&hclk_bus>,    <&pclk_bus>,
1918                                         <&pclk_bus>,    <&pclk_bus>;
1919
1920                                         clock-output-names =
1921                                         "g_aclk_intmem",        "g_intmem_mbist",
1922                                         "g_aclk_dmac_bus",      "g_hclk_rom",
1923
1924                                         "g_p_ddrupctl", "g_clk_ddrupctl",
1925                                         "g_p_ddrmon",   "g_h_i2s0_8ch",
1926
1927                                         "g_h_i2s1_8ch", "g_h_i2s2_2ch",
1928                                         "g_h_spdif_8ch",        "g_h_crypto_mst",
1929
1930                                         "g_h_crypto_slv",       "g_p_efuse_1024",
1931                                         "g_p_efuse_256",        "g_pclk_i2c0";
1932
1933                                         #clock-cells = <1>;
1934                                 };
1935
1936                                 clk_gates9: gate-clk@00f4 {
1937                                         compatible = "rockchip,rk3188-gate-clk";
1938                                         reg = <0x00f4 0x4>;
1939                                         clocks =
1940                                         <&pclk_bus>,    <&pclk_bus>,
1941                                         <&pclk_bus>,    <&dummy>,
1942
1943                                         <&pclk_bus>,    <&pclk_bus>,
1944                                         <&pclk_bus>,    <&pclk_bus>,
1945
1946                                         <&pclk_bus>,    <&pclk_bus>,
1947                                         <&pclk_bus>,    <&pclk_bus>,
1948
1949                                         <&pclk_bus>,    <&pclk_bus>,
1950                                         <&pclk_bus>,    <&pclk_bus>;
1951
1952                                         clock-output-names =
1953                                         "g_pclk_i2c1",  "g_pclk_i2c2",
1954                                         "g_pclk_i2c3",  "reserved",
1955
1956                                         "g_pclk_timer0",        "g_pclk_stimer",
1957                                         "g_pclk_spi0",  "g_pclk_rk_pwm",
1958
1959                                         "g_pclk_gpio0", "g_pclk_gpio1",
1960                                         "g_pclk_gpio2", "g_pclk_gpio3",
1961
1962                                         "g_pclk_uart0", "g_pclk_uart1",
1963                                         "g_pclk_uart2", "g_pclk_tsadc";
1964
1965                                         #clock-cells = <1>;
1966                                 };
1967
1968                                 clk_gates10: gate-clk@00f8 {
1969                                         compatible = "rockchip,rk3188-gate-clk";
1970                                         reg = <0x00f8 0x4>;
1971                                         clocks =
1972                                         <&pclk_bus>,    <&aclk_bus>,
1973                                         <&clk_gates6 13>,       <&clk_gates6 4>,
1974
1975                                         <&pclk_bus>,    <&clk_gates6 4>,
1976                                         <&pclk_bus>,    <&clk_gates6 4>,
1977
1978                                         <&clk_gates6 4>,        <&clk_gates6 4>,
1979                                         <&pclk_bus>,    <&hclk_bus>,
1980
1981                                         <&clkin_hsadc_tsp>,     <&dummy>,
1982                                         <&dummy>,       <&dummy>;
1983
1984                                         clock-output-names =
1985                                         "g_pclk_grf",   "g_aclk_bus",
1986                                         "g_p_mschniu",  "g_p_ddrphy",
1987
1988                                         "g_pclk_cru",   "g_p_acodecphy",
1989                                         "g_pclk_sgrf",  "g_p_hdmiphy",
1990
1991                                         "g_p_vdacphy",  "g_p_phy_noc",
1992                                         "g_pclk_sim",   "g_hclk_tsp",
1993
1994                                         "clk_hsadc_tsp",        "reserved",
1995                                         "reserved",     "reserved";
1996
1997                                         #clock-cells = <1>;
1998                                 };
1999
2000                                 clk_gates11: gate-clk@00fc {
2001                                         compatible = "rockchip,rk3188-gate-clk";
2002                                         reg = <0x00fc 0x4>;
2003                                         clocks =
2004                                         <&hclk_peri>,   <&hclk_peri>,
2005                                         <&hclk_peri>,   <&hclk_peri>,
2006
2007                                         <&aclk_peri>,   <&pclk_peri>,
2008                                         <&hclk_peri>,   <&hclk_peri>,
2009
2010                                         <&hclk_peri>,   <&hclk_peri>,
2011                                         <&hclk_peri>,   <&dummy>,
2012
2013                                         <&hclk_peri>,   <&hclk_peri>,
2014                                         <&hclk_peri>,   <&dummy>;
2015
2016                                         clock-output-names =
2017                                         "g_hclk_sdmmc", "g_hclk_sdio",
2018                                         "g_clk_emmc",   "g_clk_nandc",
2019
2020                                         "g_aclk_gmac",  "g_pclk_gmac",
2021                                         "g_hclk_host0", "g_h_host0_arb",
2022
2023                                         "g_hclk_host1", "g_h_host1_arb",
2024                                         "g_hclk_host2", "reserved",
2025
2026                                         "g_hclk_otg",   "g_hclk_otg_pmu",
2027                                         "g_h_host2_arb",        "reserved";
2028
2029                                         #clock-cells = <1>;
2030                                 };
2031
2032                                 clk_gates12: gate-clk@0100 {
2033                                         compatible = "rockchip,rk3188-gate-clk";
2034                                         reg = <0x0100 0x4>;
2035                                         clocks =
2036                                         <&aclk_peri>,   <&hclk_peri>,
2037                                         <&pclk_peri>,   <&dummy>,
2038
2039                                         <&dummy>,       <&dummy>,
2040                                         <&dummy>,       <&dummy>,
2041
2042                                         <&dummy>,       <&dummy>,
2043                                         <&dummy>,       <&dummy>,
2044
2045                                         <&dummy>,       <&dummy>,
2046                                         <&dummy>,       <&dummy>;
2047
2048                                         clock-output-names =
2049                                         "g_a_peri_noc", "g_h_peri_noc",
2050                                         "g_p_peri_noc", "reserved",
2051
2052                                         "reserved",     "reserved",
2053                                         "reserved",     "reserved",
2054
2055                                         "reserved",     "reserved",
2056                                         "reserved",     "reserved",
2057
2058                                         "reserved",     "reserved",
2059                                         "reserved",     "reserved";
2060
2061                                         #clock-cells = <1>;
2062                                 };
2063
2064                                 clk_gates13: gate-clk@0104 {
2065                                         compatible = "rockchip,rk3188-gate-clk";
2066                                         reg = <0x0104 0x4>;
2067                                         clocks =
2068                                         <&aclk_rga>,    <&hclk_vio>,
2069                                         <&aclk_iep>,    <&hclk_vio>,
2070
2071                                         <&dummy>,       <&aclk_vop>,
2072                                         <&hclk_vio>,    <&hclk_vio>,
2073
2074                                         <&hclk_vio>,    <&aclk_iep>,
2075                                         <&aclk_hdcp>,   <&aclk_rga>,
2076
2077                                         <&aclk_vop>,    <&hclk_vio>,
2078                                         <&dummy>,       <&dummy>;
2079
2080                                         clock-output-names =
2081                                         "g_aclk_rga",   "g_hclk_rga",
2082                                         "g_aclk_iep",   "g_hclk_iep",
2083
2084                                         "reserved",     "g_aclk_vop",
2085                                         "g_hclk_vop",   "g_h_vio_ahbarbi",
2086
2087                                         "g_h_vio_noc",  "g_a_iep_noc",
2088                                         "g_a_hdcp_noc", "g_a_rga_noc",
2089
2090                                         "g_a_vop_noc",  "g_h_vop_noc",
2091                                         "reserved",     "reserved";
2092
2093                                         #clock-cells = <1>;
2094                                 };
2095
2096                                 clk_gates14: gate-clk@0108 {
2097                                         compatible = "rockchip,rk3188-gate-clk";
2098                                         reg = <0x0108 0x4>;
2099                                         clocks =
2100                                         <&dummy>,       <&dummy>,
2101                                         <&dummy>,       <&dummy>,
2102
2103                                         <&dummy>,       <&dummy>,
2104                                         <&hclk_vio>,    <&hclk_vio>,
2105
2106                                         <&dummy>,       <&dummy>,
2107                                         <&aclk_hdcp>,   <&hclk_vio>,
2108
2109                                         <&hclk_vio>,    <&dummy>,
2110                                         <&dummy>,       <&dummy>;
2111
2112                                         clock-output-names =
2113                                         "reserved",     "reserved",
2114                                         "reserved",     "reserved",
2115
2116                                         "reserved",     "reserved",
2117                                         "g_p_hdmi_ctrl",        "g_h_vio_h2p",
2118
2119                                         "reserved",     "reserved",
2120                                         "g_aclk_hdcp",  "g_pclk_hdcp",
2121
2122                                         "g_h_hdcp_mmu", "reserved",
2123                                         "reserved",     "reserved";
2124
2125                                         #clock-cells = <1>;
2126                                 };
2127
2128                                 clk_gates15: gate-clk@010c {
2129                                         compatible = "rockchip,rk3188-gate-clk";
2130                                         reg = <0x010c 0x4>;
2131                                         clocks =
2132                                         <&aclk_vpu>,    <&hclk_vpu>,
2133                                         <&aclk_rkvdec>, <&hclk_rkvdec>,
2134
2135                                         <&aclk_vpu>,    <&hclk_vpu>,
2136                                         <&aclk_rkvdec>, <&hclk_rkvdec>,
2137
2138                                         <&dummy>,       <&dummy>,
2139                                         <&dummy>,       <&dummy>,
2140
2141                                         <&dummy>,       <&dummy>,
2142                                         <&dummy>,       <&dummy>;
2143
2144                                         clock-output-names =
2145                                         "g_aclk_vpu",   "g_hclk_vpu",
2146                                         "g_a_rkvdec",   "g_h_rkvdec",
2147
2148                                         "g_a_vpu_noc",  "g_h_vpu_noc",
2149                                         "g_a_rkvdec_noc",       "g_h_rkvdec_noc",
2150
2151                                         "reserved",     "reserved",
2152                                         "reserved",     "reserved",
2153
2154                                         "reserved",     "reserved",
2155                                         "reserved",     "reserved";
2156
2157                                         #clock-cells = <1>;
2158                                 };
2159                 };
2160         };
2161 };
2162 };